1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/of_address.h> 8 #include <linux/platform_device.h> 9 10 #include "ccu_common.h" 11 #include "ccu_reset.h" 12 13 #include "ccu_div.h" 14 #include "ccu_gate.h" 15 #include "ccu_mp.h" 16 #include "ccu_nm.h" 17 18 #include "ccu-sun8i-r.h" 19 20 static const struct clk_parent_data ar100_parents[] = { 21 { .fw_name = "losc" }, 22 { .fw_name = "hosc" }, 23 { .fw_name = "pll-periph" }, 24 { .fw_name = "iosc" }, 25 }; 26 27 static const struct ccu_mux_var_prediv ar100_predivs[] = { 28 { .index = 2, .shift = 8, .width = 5 }, 29 }; 30 31 static struct ccu_div ar100_clk = { 32 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 33 34 .mux = { 35 .shift = 16, 36 .width = 2, 37 38 .var_predivs = ar100_predivs, 39 .n_var_predivs = ARRAY_SIZE(ar100_predivs), 40 }, 41 42 .common = { 43 .reg = 0x00, 44 .features = CCU_FEATURE_VARIABLE_PREDIV, 45 .hw.init = CLK_HW_INIT_PARENTS_DATA("ar100", 46 ar100_parents, 47 &ccu_div_ops, 48 0), 49 }, 50 }; 51 52 static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0); 53 54 static struct ccu_div apb0_clk = { 55 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 56 57 .common = { 58 .reg = 0x0c, 59 .hw.init = CLK_HW_INIT_HW("apb0", 60 &ahb0_clk.hw, 61 &ccu_div_ops, 62 0), 63 }, 64 }; 65 66 static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0); 67 68 /* 69 * Define the parent as an array that can be reused to save space 70 * instead of having compound literals for each gate. Also have it 71 * non-const so we can change it on the A83T. 72 */ 73 static const struct clk_hw *apb0_gate_parent[] = { &apb0_clk.common.hw }; 74 static SUNXI_CCU_GATE_HWS(apb0_pio_clk, "apb0-pio", 75 apb0_gate_parent, 0x28, BIT(0), 0); 76 static SUNXI_CCU_GATE_HWS(apb0_ir_clk, "apb0-ir", 77 apb0_gate_parent, 0x28, BIT(1), 0); 78 static SUNXI_CCU_GATE_HWS(apb0_timer_clk, "apb0-timer", 79 apb0_gate_parent, 0x28, BIT(2), 0); 80 static SUNXI_CCU_GATE_HWS(apb0_rsb_clk, "apb0-rsb", 81 apb0_gate_parent, 0x28, BIT(3), 0); 82 static SUNXI_CCU_GATE_HWS(apb0_uart_clk, "apb0-uart", 83 apb0_gate_parent, 0x28, BIT(4), 0); 84 static SUNXI_CCU_GATE_HWS(apb0_i2c_clk, "apb0-i2c", 85 apb0_gate_parent, 0x28, BIT(6), 0); 86 static SUNXI_CCU_GATE_HWS(apb0_twd_clk, "apb0-twd", 87 apb0_gate_parent, 0x28, BIT(7), 0); 88 89 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; 90 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", 91 r_mod0_default_parents, 0x54, 92 0, 4, /* M */ 93 16, 2, /* P */ 94 24, 2, /* mux */ 95 BIT(31), /* gate */ 96 0); 97 98 static const struct clk_parent_data a83t_r_mod0_parents[] = { 99 { .fw_name = "iosc" }, 100 { .fw_name = "hosc" }, 101 }; 102 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = { 103 { .index = 0, .div = 16 }, 104 }; 105 static struct ccu_mp a83t_ir_clk = { 106 .enable = BIT(31), 107 108 .m = _SUNXI_CCU_DIV(0, 4), 109 .p = _SUNXI_CCU_DIV(16, 2), 110 111 .mux = { 112 .shift = 24, 113 .width = 2, 114 .fixed_predivs = a83t_ir_predivs, 115 .n_predivs = ARRAY_SIZE(a83t_ir_predivs), 116 }, 117 118 .common = { 119 .reg = 0x54, 120 .features = CCU_FEATURE_VARIABLE_PREDIV, 121 .hw.init = CLK_HW_INIT_PARENTS_DATA("ir", 122 a83t_r_mod0_parents, 123 &ccu_mp_ops, 124 0), 125 }, 126 }; 127 128 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = { 129 &ar100_clk.common, 130 &a83t_apb0_clk.common, 131 &apb0_pio_clk.common, 132 &apb0_ir_clk.common, 133 &apb0_timer_clk.common, 134 &apb0_rsb_clk.common, 135 &apb0_uart_clk.common, 136 &apb0_i2c_clk.common, 137 &apb0_twd_clk.common, 138 &a83t_ir_clk.common, 139 }; 140 141 static struct ccu_common *sun8i_h3_r_ccu_clks[] = { 142 &ar100_clk.common, 143 &apb0_clk.common, 144 &apb0_pio_clk.common, 145 &apb0_ir_clk.common, 146 &apb0_timer_clk.common, 147 &apb0_uart_clk.common, 148 &apb0_i2c_clk.common, 149 &apb0_twd_clk.common, 150 &ir_clk.common, 151 }; 152 153 static struct ccu_common *sun50i_a64_r_ccu_clks[] = { 154 &ar100_clk.common, 155 &apb0_clk.common, 156 &apb0_pio_clk.common, 157 &apb0_ir_clk.common, 158 &apb0_timer_clk.common, 159 &apb0_rsb_clk.common, 160 &apb0_uart_clk.common, 161 &apb0_i2c_clk.common, 162 &apb0_twd_clk.common, 163 &ir_clk.common, 164 }; 165 166 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = { 167 .hws = { 168 [CLK_AR100] = &ar100_clk.common.hw, 169 [CLK_AHB0] = &ahb0_clk.hw, 170 [CLK_APB0] = &a83t_apb0_clk.common.hw, 171 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 172 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 173 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 174 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 175 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 176 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 177 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 178 [CLK_IR] = &a83t_ir_clk.common.hw, 179 }, 180 .num = CLK_NUMBER, 181 }; 182 183 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { 184 .hws = { 185 [CLK_AR100] = &ar100_clk.common.hw, 186 [CLK_AHB0] = &ahb0_clk.hw, 187 [CLK_APB0] = &apb0_clk.common.hw, 188 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 189 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 190 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 191 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 192 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 193 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 194 [CLK_IR] = &ir_clk.common.hw, 195 }, 196 .num = CLK_NUMBER, 197 }; 198 199 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { 200 .hws = { 201 [CLK_AR100] = &ar100_clk.common.hw, 202 [CLK_AHB0] = &ahb0_clk.hw, 203 [CLK_APB0] = &apb0_clk.common.hw, 204 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 205 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 206 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 207 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 208 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 209 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 210 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 211 [CLK_IR] = &ir_clk.common.hw, 212 }, 213 .num = CLK_NUMBER, 214 }; 215 216 static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = { 217 [RST_APB0_IR] = { 0xb0, BIT(1) }, 218 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 219 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 220 [RST_APB0_UART] = { 0xb0, BIT(4) }, 221 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 222 }; 223 224 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { 225 [RST_APB0_IR] = { 0xb0, BIT(1) }, 226 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 227 [RST_APB0_UART] = { 0xb0, BIT(4) }, 228 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 229 }; 230 231 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { 232 [RST_APB0_IR] = { 0xb0, BIT(1) }, 233 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 234 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 235 [RST_APB0_UART] = { 0xb0, BIT(4) }, 236 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 237 }; 238 239 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = { 240 .ccu_clks = sun8i_a83t_r_ccu_clks, 241 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks), 242 243 .hw_clks = &sun8i_a83t_r_hw_clks, 244 245 .resets = sun8i_a83t_r_ccu_resets, 246 .num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets), 247 }; 248 249 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { 250 .ccu_clks = sun8i_h3_r_ccu_clks, 251 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), 252 253 .hw_clks = &sun8i_h3_r_hw_clks, 254 255 .resets = sun8i_h3_r_ccu_resets, 256 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), 257 }; 258 259 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { 260 .ccu_clks = sun50i_a64_r_ccu_clks, 261 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), 262 263 .hw_clks = &sun50i_a64_r_hw_clks, 264 265 .resets = sun50i_a64_r_ccu_resets, 266 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), 267 }; 268 269 static void __init sunxi_r_ccu_init(struct device_node *node, 270 const struct sunxi_ccu_desc *desc) 271 { 272 void __iomem *reg; 273 274 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 275 if (IS_ERR(reg)) { 276 pr_err("%pOF: Could not map the clock registers\n", node); 277 return; 278 } 279 280 sunxi_ccu_probe(node, reg, desc); 281 } 282 283 static void __init sun8i_a83t_r_ccu_setup(struct device_node *node) 284 { 285 /* Fix apb0 bus gate parents here */ 286 apb0_gate_parent[0] = &a83t_apb0_clk.common.hw; 287 288 sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc); 289 } 290 CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu", 291 sun8i_a83t_r_ccu_setup); 292 293 static void __init sun8i_h3_r_ccu_setup(struct device_node *node) 294 { 295 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); 296 } 297 CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", 298 sun8i_h3_r_ccu_setup); 299 300 static void __init sun50i_a64_r_ccu_setup(struct device_node *node) 301 { 302 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); 303 } 304 CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", 305 sun50i_a64_r_ccu_setup); 306