1 /* 2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 18 #include "ccu_common.h" 19 #include "ccu_reset.h" 20 21 #include "ccu_div.h" 22 #include "ccu_gate.h" 23 #include "ccu_mp.h" 24 #include "ccu_nm.h" 25 26 #include "ccu-sun8i-r.h" 27 28 static const char * const ar100_parents[] = { "osc32k", "osc24M", 29 "pll-periph0", "iosc" }; 30 static const char * const a83t_ar100_parents[] = { "osc16M-d512", "osc24M", 31 "pll-periph0", "iosc" }; 32 static const struct ccu_mux_var_prediv ar100_predivs[] = { 33 { .index = 2, .shift = 8, .width = 5 }, 34 }; 35 36 static struct ccu_div ar100_clk = { 37 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 38 39 .mux = { 40 .shift = 16, 41 .width = 2, 42 43 .var_predivs = ar100_predivs, 44 .n_var_predivs = ARRAY_SIZE(ar100_predivs), 45 }, 46 47 .common = { 48 .reg = 0x00, 49 .features = CCU_FEATURE_VARIABLE_PREDIV, 50 .hw.init = CLK_HW_INIT_PARENTS("ar100", 51 ar100_parents, 52 &ccu_div_ops, 53 0), 54 }, 55 }; 56 57 static struct ccu_div a83t_ar100_clk = { 58 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 59 60 .mux = { 61 .shift = 16, 62 .width = 2, 63 64 .var_predivs = ar100_predivs, 65 .n_var_predivs = ARRAY_SIZE(ar100_predivs), 66 }, 67 68 .common = { 69 .reg = 0x00, 70 .features = CCU_FEATURE_VARIABLE_PREDIV, 71 .hw.init = CLK_HW_INIT_PARENTS("ar100", 72 a83t_ar100_parents, 73 &ccu_div_ops, 74 0), 75 }, 76 }; 77 78 static CLK_FIXED_FACTOR(ahb0_clk, "ahb0", "ar100", 1, 1, 0); 79 80 static struct ccu_div apb0_clk = { 81 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 82 83 .common = { 84 .reg = 0x0c, 85 .hw.init = CLK_HW_INIT("apb0", 86 "ahb0", 87 &ccu_div_ops, 88 0), 89 }, 90 }; 91 92 static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0); 93 94 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", 95 0x28, BIT(0), 0); 96 static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", 97 0x28, BIT(1), 0); 98 static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", 99 0x28, BIT(2), 0); 100 static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", 101 0x28, BIT(3), 0); 102 static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", 103 0x28, BIT(4), 0); 104 static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", 105 0x28, BIT(6), 0); 106 static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", 107 0x28, BIT(7), 0); 108 109 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; 110 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", 111 r_mod0_default_parents, 0x54, 112 0, 4, /* M */ 113 16, 2, /* P */ 114 24, 2, /* mux */ 115 BIT(31), /* gate */ 116 0); 117 118 static const char *const a83t_r_mod0_parents[] = { "osc16M", "osc24M" }; 119 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = { 120 { .index = 0, .div = 16 }, 121 }; 122 static struct ccu_mp a83t_ir_clk = { 123 .enable = BIT(31), 124 125 .m = _SUNXI_CCU_DIV(0, 4), 126 .p = _SUNXI_CCU_DIV(16, 2), 127 128 .mux = { 129 .shift = 24, 130 .width = 2, 131 .fixed_predivs = a83t_ir_predivs, 132 .n_predivs = ARRAY_SIZE(a83t_ir_predivs), 133 }, 134 135 .common = { 136 .reg = 0x54, 137 .features = CCU_FEATURE_VARIABLE_PREDIV, 138 .hw.init = CLK_HW_INIT_PARENTS("ir", 139 a83t_r_mod0_parents, 140 &ccu_mp_ops, 141 0), 142 }, 143 }; 144 145 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = { 146 &a83t_ar100_clk.common, 147 &a83t_apb0_clk.common, 148 &apb0_pio_clk.common, 149 &apb0_ir_clk.common, 150 &apb0_timer_clk.common, 151 &apb0_rsb_clk.common, 152 &apb0_uart_clk.common, 153 &apb0_i2c_clk.common, 154 &apb0_twd_clk.common, 155 &a83t_ir_clk.common, 156 }; 157 158 static struct ccu_common *sun8i_h3_r_ccu_clks[] = { 159 &ar100_clk.common, 160 &apb0_clk.common, 161 &apb0_pio_clk.common, 162 &apb0_ir_clk.common, 163 &apb0_timer_clk.common, 164 &apb0_uart_clk.common, 165 &apb0_i2c_clk.common, 166 &apb0_twd_clk.common, 167 &ir_clk.common, 168 }; 169 170 static struct ccu_common *sun50i_a64_r_ccu_clks[] = { 171 &ar100_clk.common, 172 &apb0_clk.common, 173 &apb0_pio_clk.common, 174 &apb0_ir_clk.common, 175 &apb0_timer_clk.common, 176 &apb0_rsb_clk.common, 177 &apb0_uart_clk.common, 178 &apb0_i2c_clk.common, 179 &apb0_twd_clk.common, 180 &ir_clk.common, 181 }; 182 183 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = { 184 .hws = { 185 [CLK_AR100] = &a83t_ar100_clk.common.hw, 186 [CLK_AHB0] = &ahb0_clk.hw, 187 [CLK_APB0] = &a83t_apb0_clk.common.hw, 188 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 189 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 190 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 191 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 192 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 193 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 194 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 195 [CLK_IR] = &a83t_ir_clk.common.hw, 196 }, 197 .num = CLK_NUMBER, 198 }; 199 200 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { 201 .hws = { 202 [CLK_AR100] = &ar100_clk.common.hw, 203 [CLK_AHB0] = &ahb0_clk.hw, 204 [CLK_APB0] = &apb0_clk.common.hw, 205 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 206 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 207 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 208 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 209 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 210 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 211 [CLK_IR] = &ir_clk.common.hw, 212 }, 213 .num = CLK_NUMBER, 214 }; 215 216 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { 217 .hws = { 218 [CLK_AR100] = &ar100_clk.common.hw, 219 [CLK_AHB0] = &ahb0_clk.hw, 220 [CLK_APB0] = &apb0_clk.common.hw, 221 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 222 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 223 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 224 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 225 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 226 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 227 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 228 [CLK_IR] = &ir_clk.common.hw, 229 }, 230 .num = CLK_NUMBER, 231 }; 232 233 static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = { 234 [RST_APB0_IR] = { 0xb0, BIT(1) }, 235 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 236 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 237 [RST_APB0_UART] = { 0xb0, BIT(4) }, 238 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 239 }; 240 241 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { 242 [RST_APB0_IR] = { 0xb0, BIT(1) }, 243 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 244 [RST_APB0_UART] = { 0xb0, BIT(4) }, 245 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 246 }; 247 248 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { 249 [RST_APB0_IR] = { 0xb0, BIT(1) }, 250 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 251 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 252 [RST_APB0_UART] = { 0xb0, BIT(4) }, 253 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 254 }; 255 256 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = { 257 .ccu_clks = sun8i_a83t_r_ccu_clks, 258 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks), 259 260 .hw_clks = &sun8i_a83t_r_hw_clks, 261 262 .resets = sun8i_a83t_r_ccu_resets, 263 .num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets), 264 }; 265 266 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { 267 .ccu_clks = sun8i_h3_r_ccu_clks, 268 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), 269 270 .hw_clks = &sun8i_h3_r_hw_clks, 271 272 .resets = sun8i_h3_r_ccu_resets, 273 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), 274 }; 275 276 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { 277 .ccu_clks = sun50i_a64_r_ccu_clks, 278 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), 279 280 .hw_clks = &sun50i_a64_r_hw_clks, 281 282 .resets = sun50i_a64_r_ccu_resets, 283 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), 284 }; 285 286 static void __init sunxi_r_ccu_init(struct device_node *node, 287 const struct sunxi_ccu_desc *desc) 288 { 289 void __iomem *reg; 290 291 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 292 if (IS_ERR(reg)) { 293 pr_err("%pOF: Could not map the clock registers\n", node); 294 return; 295 } 296 297 sunxi_ccu_probe(node, reg, desc); 298 } 299 300 static void __init sun8i_a83t_r_ccu_setup(struct device_node *node) 301 { 302 sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc); 303 } 304 CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu", 305 sun8i_a83t_r_ccu_setup); 306 307 static void __init sun8i_h3_r_ccu_setup(struct device_node *node) 308 { 309 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); 310 } 311 CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", 312 sun8i_h3_r_ccu_setup); 313 314 static void __init sun50i_a64_r_ccu_setup(struct device_node *node) 315 { 316 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); 317 } 318 CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", 319 sun50i_a64_r_ccu_setup); 320