1 /* 2 * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz> 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 18 #include "ccu_common.h" 19 #include "ccu_reset.h" 20 21 #include "ccu_div.h" 22 #include "ccu_gate.h" 23 #include "ccu_mp.h" 24 #include "ccu_nm.h" 25 26 #include "ccu-sun8i-r.h" 27 28 static const struct clk_parent_data ar100_parents[] = { 29 { .fw_name = "losc" }, 30 { .fw_name = "hosc" }, 31 { .fw_name = "pll-periph" }, 32 { .fw_name = "iosc" }, 33 }; 34 35 static const struct ccu_mux_var_prediv ar100_predivs[] = { 36 { .index = 2, .shift = 8, .width = 5 }, 37 }; 38 39 static struct ccu_div ar100_clk = { 40 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 41 42 .mux = { 43 .shift = 16, 44 .width = 2, 45 46 .var_predivs = ar100_predivs, 47 .n_var_predivs = ARRAY_SIZE(ar100_predivs), 48 }, 49 50 .common = { 51 .reg = 0x00, 52 .features = CCU_FEATURE_VARIABLE_PREDIV, 53 .hw.init = CLK_HW_INIT_PARENTS_DATA("ar100", 54 ar100_parents, 55 &ccu_div_ops, 56 0), 57 }, 58 }; 59 60 static CLK_FIXED_FACTOR_HW(ahb0_clk, "ahb0", &ar100_clk.common.hw, 1, 1, 0); 61 62 static struct ccu_div apb0_clk = { 63 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO), 64 65 .common = { 66 .reg = 0x0c, 67 .hw.init = CLK_HW_INIT_HW("apb0", 68 &ahb0_clk.hw, 69 &ccu_div_ops, 70 0), 71 }, 72 }; 73 74 static SUNXI_CCU_M(a83t_apb0_clk, "apb0", "ahb0", 0x0c, 0, 2, 0); 75 76 static SUNXI_CCU_GATE(apb0_pio_clk, "apb0-pio", "apb0", 77 0x28, BIT(0), 0); 78 static SUNXI_CCU_GATE(apb0_ir_clk, "apb0-ir", "apb0", 79 0x28, BIT(1), 0); 80 static SUNXI_CCU_GATE(apb0_timer_clk, "apb0-timer", "apb0", 81 0x28, BIT(2), 0); 82 static SUNXI_CCU_GATE(apb0_rsb_clk, "apb0-rsb", "apb0", 83 0x28, BIT(3), 0); 84 static SUNXI_CCU_GATE(apb0_uart_clk, "apb0-uart", "apb0", 85 0x28, BIT(4), 0); 86 static SUNXI_CCU_GATE(apb0_i2c_clk, "apb0-i2c", "apb0", 87 0x28, BIT(6), 0); 88 static SUNXI_CCU_GATE(apb0_twd_clk, "apb0-twd", "apb0", 89 0x28, BIT(7), 0); 90 91 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" }; 92 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", 93 r_mod0_default_parents, 0x54, 94 0, 4, /* M */ 95 16, 2, /* P */ 96 24, 2, /* mux */ 97 BIT(31), /* gate */ 98 0); 99 100 static const struct clk_parent_data a83t_r_mod0_parents[] = { 101 { .fw_name = "iosc" }, 102 { .fw_name = "hosc" }, 103 }; 104 static const struct ccu_mux_fixed_prediv a83t_ir_predivs[] = { 105 { .index = 0, .div = 16 }, 106 }; 107 static struct ccu_mp a83t_ir_clk = { 108 .enable = BIT(31), 109 110 .m = _SUNXI_CCU_DIV(0, 4), 111 .p = _SUNXI_CCU_DIV(16, 2), 112 113 .mux = { 114 .shift = 24, 115 .width = 2, 116 .fixed_predivs = a83t_ir_predivs, 117 .n_predivs = ARRAY_SIZE(a83t_ir_predivs), 118 }, 119 120 .common = { 121 .reg = 0x54, 122 .features = CCU_FEATURE_VARIABLE_PREDIV, 123 .hw.init = CLK_HW_INIT_PARENTS_DATA("ir", 124 a83t_r_mod0_parents, 125 &ccu_mp_ops, 126 0), 127 }, 128 }; 129 130 static struct ccu_common *sun8i_a83t_r_ccu_clks[] = { 131 &ar100_clk.common, 132 &a83t_apb0_clk.common, 133 &apb0_pio_clk.common, 134 &apb0_ir_clk.common, 135 &apb0_timer_clk.common, 136 &apb0_rsb_clk.common, 137 &apb0_uart_clk.common, 138 &apb0_i2c_clk.common, 139 &apb0_twd_clk.common, 140 &a83t_ir_clk.common, 141 }; 142 143 static struct ccu_common *sun8i_h3_r_ccu_clks[] = { 144 &ar100_clk.common, 145 &apb0_clk.common, 146 &apb0_pio_clk.common, 147 &apb0_ir_clk.common, 148 &apb0_timer_clk.common, 149 &apb0_uart_clk.common, 150 &apb0_i2c_clk.common, 151 &apb0_twd_clk.common, 152 &ir_clk.common, 153 }; 154 155 static struct ccu_common *sun50i_a64_r_ccu_clks[] = { 156 &ar100_clk.common, 157 &apb0_clk.common, 158 &apb0_pio_clk.common, 159 &apb0_ir_clk.common, 160 &apb0_timer_clk.common, 161 &apb0_rsb_clk.common, 162 &apb0_uart_clk.common, 163 &apb0_i2c_clk.common, 164 &apb0_twd_clk.common, 165 &ir_clk.common, 166 }; 167 168 static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = { 169 .hws = { 170 [CLK_AR100] = &ar100_clk.common.hw, 171 [CLK_AHB0] = &ahb0_clk.hw, 172 [CLK_APB0] = &a83t_apb0_clk.common.hw, 173 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 174 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 175 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 176 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 177 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 178 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 179 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 180 [CLK_IR] = &a83t_ir_clk.common.hw, 181 }, 182 .num = CLK_NUMBER, 183 }; 184 185 static struct clk_hw_onecell_data sun8i_h3_r_hw_clks = { 186 .hws = { 187 [CLK_AR100] = &ar100_clk.common.hw, 188 [CLK_AHB0] = &ahb0_clk.hw, 189 [CLK_APB0] = &apb0_clk.common.hw, 190 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 191 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 192 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 193 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 194 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 195 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 196 [CLK_IR] = &ir_clk.common.hw, 197 }, 198 .num = CLK_NUMBER, 199 }; 200 201 static struct clk_hw_onecell_data sun50i_a64_r_hw_clks = { 202 .hws = { 203 [CLK_AR100] = &ar100_clk.common.hw, 204 [CLK_AHB0] = &ahb0_clk.hw, 205 [CLK_APB0] = &apb0_clk.common.hw, 206 [CLK_APB0_PIO] = &apb0_pio_clk.common.hw, 207 [CLK_APB0_IR] = &apb0_ir_clk.common.hw, 208 [CLK_APB0_TIMER] = &apb0_timer_clk.common.hw, 209 [CLK_APB0_RSB] = &apb0_rsb_clk.common.hw, 210 [CLK_APB0_UART] = &apb0_uart_clk.common.hw, 211 [CLK_APB0_I2C] = &apb0_i2c_clk.common.hw, 212 [CLK_APB0_TWD] = &apb0_twd_clk.common.hw, 213 [CLK_IR] = &ir_clk.common.hw, 214 }, 215 .num = CLK_NUMBER, 216 }; 217 218 static struct ccu_reset_map sun8i_a83t_r_ccu_resets[] = { 219 [RST_APB0_IR] = { 0xb0, BIT(1) }, 220 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 221 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 222 [RST_APB0_UART] = { 0xb0, BIT(4) }, 223 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 224 }; 225 226 static struct ccu_reset_map sun8i_h3_r_ccu_resets[] = { 227 [RST_APB0_IR] = { 0xb0, BIT(1) }, 228 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 229 [RST_APB0_UART] = { 0xb0, BIT(4) }, 230 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 231 }; 232 233 static struct ccu_reset_map sun50i_a64_r_ccu_resets[] = { 234 [RST_APB0_IR] = { 0xb0, BIT(1) }, 235 [RST_APB0_TIMER] = { 0xb0, BIT(2) }, 236 [RST_APB0_RSB] = { 0xb0, BIT(3) }, 237 [RST_APB0_UART] = { 0xb0, BIT(4) }, 238 [RST_APB0_I2C] = { 0xb0, BIT(6) }, 239 }; 240 241 static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = { 242 .ccu_clks = sun8i_a83t_r_ccu_clks, 243 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks), 244 245 .hw_clks = &sun8i_a83t_r_hw_clks, 246 247 .resets = sun8i_a83t_r_ccu_resets, 248 .num_resets = ARRAY_SIZE(sun8i_a83t_r_ccu_resets), 249 }; 250 251 static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = { 252 .ccu_clks = sun8i_h3_r_ccu_clks, 253 .num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks), 254 255 .hw_clks = &sun8i_h3_r_hw_clks, 256 257 .resets = sun8i_h3_r_ccu_resets, 258 .num_resets = ARRAY_SIZE(sun8i_h3_r_ccu_resets), 259 }; 260 261 static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = { 262 .ccu_clks = sun50i_a64_r_ccu_clks, 263 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks), 264 265 .hw_clks = &sun50i_a64_r_hw_clks, 266 267 .resets = sun50i_a64_r_ccu_resets, 268 .num_resets = ARRAY_SIZE(sun50i_a64_r_ccu_resets), 269 }; 270 271 static void __init sunxi_r_ccu_init(struct device_node *node, 272 const struct sunxi_ccu_desc *desc) 273 { 274 void __iomem *reg; 275 276 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 277 if (IS_ERR(reg)) { 278 pr_err("%pOF: Could not map the clock registers\n", node); 279 return; 280 } 281 282 sunxi_ccu_probe(node, reg, desc); 283 } 284 285 static void __init sun8i_a83t_r_ccu_setup(struct device_node *node) 286 { 287 sunxi_r_ccu_init(node, &sun8i_a83t_r_ccu_desc); 288 } 289 CLK_OF_DECLARE(sun8i_a83t_r_ccu, "allwinner,sun8i-a83t-r-ccu", 290 sun8i_a83t_r_ccu_setup); 291 292 static void __init sun8i_h3_r_ccu_setup(struct device_node *node) 293 { 294 sunxi_r_ccu_init(node, &sun8i_h3_r_ccu_desc); 295 } 296 CLK_OF_DECLARE(sun8i_h3_r_ccu, "allwinner,sun8i-h3-r-ccu", 297 sun8i_h3_r_ccu_setup); 298 299 static void __init sun50i_a64_r_ccu_setup(struct device_node *node) 300 { 301 sunxi_r_ccu_init(node, &sun50i_a64_r_ccu_desc); 302 } 303 CLK_OF_DECLARE(sun50i_a64_r_ccu, "allwinner,sun50i-a64-r-ccu", 304 sun50i_a64_r_ccu_setup); 305