1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/of_address.h>
9 
10 #include "ccu_common.h"
11 #include "ccu_reset.h"
12 
13 #include "ccu_div.h"
14 #include "ccu_gate.h"
15 #include "ccu_mp.h"
16 #include "ccu_mult.h"
17 #include "ccu_nk.h"
18 #include "ccu_nkm.h"
19 #include "ccu_nkmp.h"
20 #include "ccu_nm.h"
21 #include "ccu_phase.h"
22 #include "ccu_sdm.h"
23 
24 #include "ccu-sun8i-h3.h"
25 
26 static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
27 				     "osc24M", 0x000,
28 				     8, 5,	/* N */
29 				     4, 2,	/* K */
30 				     0, 2,	/* M */
31 				     16, 2,	/* P */
32 				     BIT(31),	/* gate */
33 				     BIT(28),	/* lock */
34 				     CLK_SET_RATE_UNGATE);
35 
36 /*
37  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
38  * the base (2x, 4x and 8x), and one variable divider (the one true
39  * pll audio).
40  *
41  * With sigma-delta modulation for fractional-N on the audio PLL,
42  * we have to use specific dividers. This means the variable divider
43  * can no longer be used, as the audio codec requests the exact clock
44  * rates we support through this mechanism. So we now hard code the
45  * variable divider to 1. This means the clock rates will no longer
46  * match the clock names.
47  */
48 #define SUN8I_H3_PLL_AUDIO_REG	0x008
49 
50 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
51 	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
52 	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
53 };
54 
55 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
56 				       "osc24M", 0x008,
57 				       8, 7,	/* N */
58 				       0, 5,	/* M */
59 				       pll_audio_sdm_table, BIT(24),
60 				       0x284, BIT(31),
61 				       BIT(31),	/* gate */
62 				       BIT(28),	/* lock */
63 				       CLK_SET_RATE_UNGATE);
64 
65 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video_clk, "pll-video",
66 						"osc24M", 0x0010,
67 						192000000, /* Minimum rate */
68 						912000000, /* Maximum rate */
69 						8, 7,      /* N */
70 						0, 4,	   /* M */
71 						BIT(24),   /* frac enable */
72 						BIT(25),   /* frac select */
73 						270000000, /* frac rate 0 */
74 						297000000, /* frac rate 1 */
75 						BIT(31),   /* gate */
76 						BIT(28),   /* lock */
77 						CLK_SET_RATE_UNGATE);
78 
79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
80 					"osc24M", 0x0018,
81 					8, 7,		/* N */
82 					0, 4,		/* M */
83 					BIT(24),	/* frac enable */
84 					BIT(25),	/* frac select */
85 					270000000,	/* frac rate 0 */
86 					297000000,	/* frac rate 1 */
87 					BIT(31),	/* gate */
88 					BIT(28),	/* lock */
89 					CLK_SET_RATE_UNGATE);
90 
91 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
92 				    "osc24M", 0x020,
93 				    8, 5,	/* N */
94 				    4, 2,	/* K */
95 				    0, 2,	/* M */
96 				    BIT(31),	/* gate */
97 				    BIT(28),	/* lock */
98 				    CLK_SET_RATE_UNGATE);
99 
100 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
101 					   "osc24M", 0x028,
102 					   8, 5,	/* N */
103 					   4, 2,	/* K */
104 					   BIT(31),	/* gate */
105 					   BIT(28),	/* lock */
106 					   2,		/* post-div */
107 					   CLK_SET_RATE_UNGATE);
108 
109 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
110 					"osc24M", 0x0038,
111 					8, 7,		/* N */
112 					0, 4,		/* M */
113 					BIT(24),	/* frac enable */
114 					BIT(25),	/* frac select */
115 					270000000,	/* frac rate 0 */
116 					297000000,	/* frac rate 1 */
117 					BIT(31),	/* gate */
118 					BIT(28),	/* lock */
119 					CLK_SET_RATE_UNGATE);
120 
121 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
122 					   "osc24M", 0x044,
123 					   8, 5,	/* N */
124 					   4, 2,	/* K */
125 					   BIT(31),	/* gate */
126 					   BIT(28),	/* lock */
127 					   2,		/* post-div */
128 					   CLK_SET_RATE_UNGATE);
129 
130 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
131 					"osc24M", 0x0048,
132 					8, 7,		/* N */
133 					0, 4,		/* M */
134 					BIT(24),	/* frac enable */
135 					BIT(25),	/* frac select */
136 					270000000,	/* frac rate 0 */
137 					297000000,	/* frac rate 1 */
138 					BIT(31),	/* gate */
139 					BIT(28),	/* lock */
140 					CLK_SET_RATE_UNGATE);
141 
142 static const char * const cpux_parents[] = { "osc32k", "osc24M",
143 					     "pll-cpux" , "pll-cpux" };
144 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
145 		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
146 
147 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
148 
149 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
150 					     "axi" , "pll-periph0" };
151 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
152 	{ .index = 3, .shift = 6, .width = 2 },
153 };
154 static struct ccu_div ahb1_clk = {
155 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
156 
157 	.mux		= {
158 		.shift	= 12,
159 		.width	= 2,
160 
161 		.var_predivs	= ahb1_predivs,
162 		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
163 	},
164 
165 	.common		= {
166 		.reg		= 0x054,
167 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
168 		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
169 						      ahb1_parents,
170 						      &ccu_div_ops,
171 						      0),
172 	},
173 };
174 
175 static struct clk_div_table apb1_div_table[] = {
176 	{ .val = 0, .div = 2 },
177 	{ .val = 1, .div = 2 },
178 	{ .val = 2, .div = 4 },
179 	{ .val = 3, .div = 8 },
180 	{ /* Sentinel */ },
181 };
182 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
183 			   0x054, 8, 2, apb1_div_table, 0);
184 
185 static const char * const apb2_parents[] = { "osc32k", "osc24M",
186 					     "pll-periph0" , "pll-periph0" };
187 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
188 			     0, 5,	/* M */
189 			     16, 2,	/* P */
190 			     24, 2,	/* mux */
191 			     0);
192 
193 static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
194 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
195 	{ .index = 1, .div = 2 },
196 };
197 static struct ccu_mux ahb2_clk = {
198 	.mux		= {
199 		.shift	= 0,
200 		.width	= 1,
201 		.fixed_predivs	= ahb2_fixed_predivs,
202 		.n_predivs	= ARRAY_SIZE(ahb2_fixed_predivs),
203 	},
204 
205 	.common		= {
206 		.reg		= 0x05c,
207 		.features	= CCU_FEATURE_FIXED_PREDIV,
208 		.hw.init	= CLK_HW_INIT_PARENTS("ahb2",
209 						      ahb2_parents,
210 						      &ccu_mux_ops,
211 						      0),
212 	},
213 };
214 
215 static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
216 		      0x060, BIT(5), 0);
217 static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
218 		      0x060, BIT(6), 0);
219 static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
220 		      0x060, BIT(8), 0);
221 static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
222 		      0x060, BIT(9), 0);
223 static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
224 		      0x060, BIT(10), 0);
225 static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
226 		      0x060, BIT(13), 0);
227 static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
228 		      0x060, BIT(14), 0);
229 static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb2",
230 		      0x060, BIT(17), 0);
231 static SUNXI_CCU_GATE(bus_ts_clk,	"bus-ts",	"ahb1",
232 		      0x060, BIT(18), 0);
233 static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
234 		      0x060, BIT(19), 0);
235 static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
236 		      0x060, BIT(20), 0);
237 static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
238 		      0x060, BIT(21), 0);
239 static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
240 		      0x060, BIT(23), 0);
241 static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
242 		      0x060, BIT(24), 0);
243 static SUNXI_CCU_GATE(bus_ehci1_clk,	"bus-ehci1",	"ahb2",
244 		      0x060, BIT(25), 0);
245 static SUNXI_CCU_GATE(bus_ehci2_clk,	"bus-ehci2",	"ahb2",
246 		      0x060, BIT(26), 0);
247 static SUNXI_CCU_GATE(bus_ehci3_clk,	"bus-ehci3",	"ahb2",
248 		      0x060, BIT(27), 0);
249 static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
250 		      0x060, BIT(28), 0);
251 static SUNXI_CCU_GATE(bus_ohci1_clk,	"bus-ohci1",	"ahb2",
252 		      0x060, BIT(29), 0);
253 static SUNXI_CCU_GATE(bus_ohci2_clk,	"bus-ohci2",	"ahb2",
254 		      0x060, BIT(30), 0);
255 static SUNXI_CCU_GATE(bus_ohci3_clk,	"bus-ohci3",	"ahb2",
256 		      0x060, BIT(31), 0);
257 
258 static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
259 		      0x064, BIT(0), 0);
260 static SUNXI_CCU_GATE(bus_tcon0_clk,	"bus-tcon0",	"ahb1",
261 		      0x064, BIT(3), 0);
262 static SUNXI_CCU_GATE(bus_tcon1_clk,	"bus-tcon1",	"ahb1",
263 		      0x064, BIT(4), 0);
264 static SUNXI_CCU_GATE(bus_deinterlace_clk,	"bus-deinterlace",	"ahb1",
265 		      0x064, BIT(5), 0);
266 static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb1",
267 		      0x064, BIT(8), 0);
268 static SUNXI_CCU_GATE(bus_tve_clk,	"bus-tve",	"ahb1",
269 		      0x064, BIT(9), 0);
270 static SUNXI_CCU_GATE(bus_hdmi_clk,	"bus-hdmi",	"ahb1",
271 		      0x064, BIT(11), 0);
272 static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
273 		      0x064, BIT(12), 0);
274 static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
275 		      0x064, BIT(20), 0);
276 static SUNXI_CCU_GATE(bus_msgbox_clk,	"bus-msgbox",	"ahb1",
277 		      0x064, BIT(21), 0);
278 static SUNXI_CCU_GATE(bus_spinlock_clk,	"bus-spinlock",	"ahb1",
279 		      0x064, BIT(22), 0);
280 
281 static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
282 		      0x068, BIT(0), 0);
283 static SUNXI_CCU_GATE(bus_spdif_clk,	"bus-spdif",	"apb1",
284 		      0x068, BIT(1), 0);
285 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
286 		      0x068, BIT(5), 0);
287 static SUNXI_CCU_GATE(bus_ths_clk,	"bus-ths",	"apb1",
288 		      0x068, BIT(8), 0);
289 static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
290 		      0x068, BIT(12), 0);
291 static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
292 		      0x068, BIT(13), 0);
293 static SUNXI_CCU_GATE(bus_i2s2_clk,	"bus-i2s2",	"apb1",
294 		      0x068, BIT(14), 0);
295 
296 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
297 		      0x06c, BIT(0), 0);
298 static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
299 		      0x06c, BIT(1), 0);
300 static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
301 		      0x06c, BIT(2), 0);
302 static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
303 		      0x06c, BIT(16), 0);
304 static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
305 		      0x06c, BIT(17), 0);
306 static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
307 		      0x06c, BIT(18), 0);
308 static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
309 		      0x06c, BIT(19), 0);
310 static SUNXI_CCU_GATE(bus_scr0_clk,	"bus-scr0",	"apb2",
311 		      0x06c, BIT(20), 0);
312 static SUNXI_CCU_GATE(bus_scr1_clk,	"bus-scr1",	"apb2",
313 		      0x06c, BIT(21), 0);
314 
315 static SUNXI_CCU_GATE(bus_ephy_clk,	"bus-ephy",	"ahb1",
316 		      0x070, BIT(0), 0);
317 static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
318 		      0x070, BIT(7), 0);
319 
320 static struct clk_div_table ths_div_table[] = {
321 	{ .val = 0, .div = 1 },
322 	{ .val = 1, .div = 2 },
323 	{ .val = 2, .div = 4 },
324 	{ .val = 3, .div = 6 },
325 };
326 static SUNXI_CCU_DIV_TABLE_WITH_GATE(ths_clk, "ths", "osc24M",
327 				     0x074, 0, 2, ths_div_table, BIT(31), 0);
328 
329 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
330 						     "pll-periph1" };
331 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
332 				  0, 4,		/* M */
333 				  16, 2,	/* P */
334 				  24, 2,	/* mux */
335 				  BIT(31),	/* gate */
336 				  0);
337 
338 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
339 				  0, 4,		/* M */
340 				  16, 2,	/* P */
341 				  24, 2,	/* mux */
342 				  BIT(31),	/* gate */
343 				  0);
344 
345 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
346 		       0x088, 20, 3, 0);
347 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
348 		       0x088, 8, 3, 0);
349 
350 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
351 				  0, 4,		/* M */
352 				  16, 2,	/* P */
353 				  24, 2,	/* mux */
354 				  BIT(31),	/* gate */
355 				  0);
356 
357 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
358 		       0x08c, 20, 3, 0);
359 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
360 		       0x08c, 8, 3, 0);
361 
362 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
363 				  0, 4,		/* M */
364 				  16, 2,	/* P */
365 				  24, 2,	/* mux */
366 				  BIT(31),	/* gate */
367 				  0);
368 
369 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
370 		       0x090, 20, 3, 0);
371 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
372 		       0x090, 8, 3, 0);
373 
374 static const char * const ts_parents[] = { "osc24M", "pll-periph0", };
375 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098,
376 				  0, 4,		/* M */
377 				  16, 2,	/* P */
378 				  24, 2,	/* mux */
379 				  BIT(31),	/* gate */
380 				  0);
381 
382 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mod0_default_parents, 0x09c,
383 				  0, 4,		/* M */
384 				  16, 2,	/* P */
385 				  24, 2,	/* mux */
386 				  BIT(31),	/* gate */
387 				  0);
388 
389 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
390 				  0, 4,		/* M */
391 				  16, 2,	/* P */
392 				  24, 2,	/* mux */
393 				  BIT(31),	/* gate */
394 				  0);
395 
396 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
397 				  0, 4,		/* M */
398 				  16, 2,	/* P */
399 				  24, 2,	/* mux */
400 				  BIT(31),	/* gate */
401 				  0);
402 
403 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
404 					    "pll-audio-2x", "pll-audio" };
405 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
406 			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
407 
408 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
409 			       0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
410 
411 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents,
412 			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
413 
414 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
415 			     0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
416 
417 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
418 		      0x0cc, BIT(8), 0);
419 static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
420 		      0x0cc, BIT(9), 0);
421 static SUNXI_CCU_GATE(usb_phy2_clk,	"usb-phy2",	"osc24M",
422 		      0x0cc, BIT(10), 0);
423 static SUNXI_CCU_GATE(usb_phy3_clk,	"usb-phy3",	"osc24M",
424 		      0x0cc, BIT(11), 0);
425 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc24M",
426 		      0x0cc, BIT(16), 0);
427 static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"osc24M",
428 		      0x0cc, BIT(17), 0);
429 static SUNXI_CCU_GATE(usb_ohci2_clk,	"usb-ohci2",	"osc24M",
430 		      0x0cc, BIT(18), 0);
431 static SUNXI_CCU_GATE(usb_ohci3_clk,	"usb-ohci3",	"osc24M",
432 		      0x0cc, BIT(19), 0);
433 
434 static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
435 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
436 			    0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
437 
438 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
439 		      0x100, BIT(0), 0);
440 static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"dram",
441 		      0x100, BIT(1), 0);
442 static SUNXI_CCU_GATE(dram_deinterlace_clk,	"dram-deinterlace",	"dram",
443 		      0x100, BIT(2), 0);
444 static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"dram",
445 		      0x100, BIT(3), 0);
446 
447 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
448 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
449 				 0x104, 0, 4, 24, 3, BIT(31),
450 				 CLK_SET_RATE_PARENT);
451 
452 static const char * const tcon_parents[] = { "pll-video" };
453 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
454 				 0x118, 0, 4, 24, 3, BIT(31),
455 				 CLK_SET_RATE_PARENT);
456 
457 static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
458 static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
459 				 0x120, 0, 4, 24, 3, BIT(31), 0);
460 
461 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
462 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
463 				 0x124, 0, 4, 24, 3, BIT(31), 0);
464 
465 static SUNXI_CCU_GATE(csi_misc_clk,	"csi-misc",	"osc24M",
466 		      0x130, BIT(31), 0);
467 
468 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" };
469 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,
470 				 0x134, 16, 4, 24, 3, BIT(31), 0);
471 
472 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", "pll-periph1" };
473 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents,
474 				 0x134, 0, 5, 8, 3, BIT(15), 0);
475 
476 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
477 			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
478 
479 static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
480 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
481 static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
482 		      0x144, BIT(31), 0);
483 
484 static const char * const hdmi_parents[] = { "pll-video" };
485 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
486 				 0x150, 0, 4, 24, 2, BIT(31),
487 				 CLK_SET_RATE_PARENT);
488 
489 static SUNXI_CCU_GATE(hdmi_ddc_clk,	"hdmi-ddc",	"osc24M",
490 		      0x154, BIT(31), 0);
491 
492 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
493 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
494 				 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
495 
496 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
497 			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
498 
499 static struct ccu_common *sun8i_h3_ccu_clks[] = {
500 	&pll_cpux_clk.common,
501 	&pll_audio_base_clk.common,
502 	&pll_video_clk.common,
503 	&pll_ve_clk.common,
504 	&pll_ddr_clk.common,
505 	&pll_periph0_clk.common,
506 	&pll_gpu_clk.common,
507 	&pll_periph1_clk.common,
508 	&pll_de_clk.common,
509 	&cpux_clk.common,
510 	&axi_clk.common,
511 	&ahb1_clk.common,
512 	&apb1_clk.common,
513 	&apb2_clk.common,
514 	&ahb2_clk.common,
515 	&bus_ce_clk.common,
516 	&bus_dma_clk.common,
517 	&bus_mmc0_clk.common,
518 	&bus_mmc1_clk.common,
519 	&bus_mmc2_clk.common,
520 	&bus_nand_clk.common,
521 	&bus_dram_clk.common,
522 	&bus_emac_clk.common,
523 	&bus_ts_clk.common,
524 	&bus_hstimer_clk.common,
525 	&bus_spi0_clk.common,
526 	&bus_spi1_clk.common,
527 	&bus_otg_clk.common,
528 	&bus_ehci0_clk.common,
529 	&bus_ehci1_clk.common,
530 	&bus_ehci2_clk.common,
531 	&bus_ehci3_clk.common,
532 	&bus_ohci0_clk.common,
533 	&bus_ohci1_clk.common,
534 	&bus_ohci2_clk.common,
535 	&bus_ohci3_clk.common,
536 	&bus_ve_clk.common,
537 	&bus_tcon0_clk.common,
538 	&bus_tcon1_clk.common,
539 	&bus_deinterlace_clk.common,
540 	&bus_csi_clk.common,
541 	&bus_tve_clk.common,
542 	&bus_hdmi_clk.common,
543 	&bus_de_clk.common,
544 	&bus_gpu_clk.common,
545 	&bus_msgbox_clk.common,
546 	&bus_spinlock_clk.common,
547 	&bus_codec_clk.common,
548 	&bus_spdif_clk.common,
549 	&bus_pio_clk.common,
550 	&bus_ths_clk.common,
551 	&bus_i2s0_clk.common,
552 	&bus_i2s1_clk.common,
553 	&bus_i2s2_clk.common,
554 	&bus_i2c0_clk.common,
555 	&bus_i2c1_clk.common,
556 	&bus_i2c2_clk.common,
557 	&bus_uart0_clk.common,
558 	&bus_uart1_clk.common,
559 	&bus_uart2_clk.common,
560 	&bus_uart3_clk.common,
561 	&bus_scr0_clk.common,
562 	&bus_ephy_clk.common,
563 	&bus_dbg_clk.common,
564 	&ths_clk.common,
565 	&nand_clk.common,
566 	&mmc0_clk.common,
567 	&mmc0_sample_clk.common,
568 	&mmc0_output_clk.common,
569 	&mmc1_clk.common,
570 	&mmc1_sample_clk.common,
571 	&mmc1_output_clk.common,
572 	&mmc2_clk.common,
573 	&mmc2_sample_clk.common,
574 	&mmc2_output_clk.common,
575 	&ts_clk.common,
576 	&ce_clk.common,
577 	&spi0_clk.common,
578 	&spi1_clk.common,
579 	&i2s0_clk.common,
580 	&i2s1_clk.common,
581 	&i2s2_clk.common,
582 	&spdif_clk.common,
583 	&usb_phy0_clk.common,
584 	&usb_phy1_clk.common,
585 	&usb_phy2_clk.common,
586 	&usb_phy3_clk.common,
587 	&usb_ohci0_clk.common,
588 	&usb_ohci1_clk.common,
589 	&usb_ohci2_clk.common,
590 	&usb_ohci3_clk.common,
591 	&dram_clk.common,
592 	&dram_ve_clk.common,
593 	&dram_csi_clk.common,
594 	&dram_deinterlace_clk.common,
595 	&dram_ts_clk.common,
596 	&de_clk.common,
597 	&tcon_clk.common,
598 	&tve_clk.common,
599 	&deinterlace_clk.common,
600 	&csi_misc_clk.common,
601 	&csi_sclk_clk.common,
602 	&csi_mclk_clk.common,
603 	&ve_clk.common,
604 	&ac_dig_clk.common,
605 	&avs_clk.common,
606 	&hdmi_clk.common,
607 	&hdmi_ddc_clk.common,
608 	&mbus_clk.common,
609 	&gpu_clk.common,
610 };
611 
612 static struct ccu_common *sun50i_h5_ccu_clks[] = {
613 	&pll_cpux_clk.common,
614 	&pll_audio_base_clk.common,
615 	&pll_video_clk.common,
616 	&pll_ve_clk.common,
617 	&pll_ddr_clk.common,
618 	&pll_periph0_clk.common,
619 	&pll_gpu_clk.common,
620 	&pll_periph1_clk.common,
621 	&pll_de_clk.common,
622 	&cpux_clk.common,
623 	&axi_clk.common,
624 	&ahb1_clk.common,
625 	&apb1_clk.common,
626 	&apb2_clk.common,
627 	&ahb2_clk.common,
628 	&bus_ce_clk.common,
629 	&bus_dma_clk.common,
630 	&bus_mmc0_clk.common,
631 	&bus_mmc1_clk.common,
632 	&bus_mmc2_clk.common,
633 	&bus_nand_clk.common,
634 	&bus_dram_clk.common,
635 	&bus_emac_clk.common,
636 	&bus_ts_clk.common,
637 	&bus_hstimer_clk.common,
638 	&bus_spi0_clk.common,
639 	&bus_spi1_clk.common,
640 	&bus_otg_clk.common,
641 	&bus_ehci0_clk.common,
642 	&bus_ehci1_clk.common,
643 	&bus_ehci2_clk.common,
644 	&bus_ehci3_clk.common,
645 	&bus_ohci0_clk.common,
646 	&bus_ohci1_clk.common,
647 	&bus_ohci2_clk.common,
648 	&bus_ohci3_clk.common,
649 	&bus_ve_clk.common,
650 	&bus_tcon0_clk.common,
651 	&bus_tcon1_clk.common,
652 	&bus_deinterlace_clk.common,
653 	&bus_csi_clk.common,
654 	&bus_tve_clk.common,
655 	&bus_hdmi_clk.common,
656 	&bus_de_clk.common,
657 	&bus_gpu_clk.common,
658 	&bus_msgbox_clk.common,
659 	&bus_spinlock_clk.common,
660 	&bus_codec_clk.common,
661 	&bus_spdif_clk.common,
662 	&bus_pio_clk.common,
663 	&bus_ths_clk.common,
664 	&bus_i2s0_clk.common,
665 	&bus_i2s1_clk.common,
666 	&bus_i2s2_clk.common,
667 	&bus_i2c0_clk.common,
668 	&bus_i2c1_clk.common,
669 	&bus_i2c2_clk.common,
670 	&bus_uart0_clk.common,
671 	&bus_uart1_clk.common,
672 	&bus_uart2_clk.common,
673 	&bus_uart3_clk.common,
674 	&bus_scr0_clk.common,
675 	&bus_scr1_clk.common,
676 	&bus_ephy_clk.common,
677 	&bus_dbg_clk.common,
678 	&ths_clk.common,
679 	&nand_clk.common,
680 	&mmc0_clk.common,
681 	&mmc1_clk.common,
682 	&mmc2_clk.common,
683 	&ts_clk.common,
684 	&ce_clk.common,
685 	&spi0_clk.common,
686 	&spi1_clk.common,
687 	&i2s0_clk.common,
688 	&i2s1_clk.common,
689 	&i2s2_clk.common,
690 	&spdif_clk.common,
691 	&usb_phy0_clk.common,
692 	&usb_phy1_clk.common,
693 	&usb_phy2_clk.common,
694 	&usb_phy3_clk.common,
695 	&usb_ohci0_clk.common,
696 	&usb_ohci1_clk.common,
697 	&usb_ohci2_clk.common,
698 	&usb_ohci3_clk.common,
699 	&dram_clk.common,
700 	&dram_ve_clk.common,
701 	&dram_csi_clk.common,
702 	&dram_deinterlace_clk.common,
703 	&dram_ts_clk.common,
704 	&de_clk.common,
705 	&tcon_clk.common,
706 	&tve_clk.common,
707 	&deinterlace_clk.common,
708 	&csi_misc_clk.common,
709 	&csi_sclk_clk.common,
710 	&csi_mclk_clk.common,
711 	&ve_clk.common,
712 	&ac_dig_clk.common,
713 	&avs_clk.common,
714 	&hdmi_clk.common,
715 	&hdmi_ddc_clk.common,
716 	&mbus_clk.common,
717 	&gpu_clk.common,
718 };
719 
720 /* We hardcode the divider to 1 for now */
721 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
722 			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
723 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
724 			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
725 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
726 			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
727 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
728 			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
729 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
730 			"pll-periph0", 1, 2, 0);
731 
732 static struct clk_hw_onecell_data sun8i_h3_hw_clks = {
733 	.hws	= {
734 		[CLK_PLL_CPUX]		= &pll_cpux_clk.common.hw,
735 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
736 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
737 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
738 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
739 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
740 		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
741 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
742 		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
743 		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
744 		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
745 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
746 		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
747 		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
748 		[CLK_CPUX]		= &cpux_clk.common.hw,
749 		[CLK_AXI]		= &axi_clk.common.hw,
750 		[CLK_AHB1]		= &ahb1_clk.common.hw,
751 		[CLK_APB1]		= &apb1_clk.common.hw,
752 		[CLK_APB2]		= &apb2_clk.common.hw,
753 		[CLK_AHB2]		= &ahb2_clk.common.hw,
754 		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
755 		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
756 		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
757 		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
758 		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
759 		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
760 		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
761 		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
762 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
763 		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
764 		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
765 		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
766 		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
767 		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
768 		[CLK_BUS_EHCI1]		= &bus_ehci1_clk.common.hw,
769 		[CLK_BUS_EHCI2]		= &bus_ehci2_clk.common.hw,
770 		[CLK_BUS_EHCI3]		= &bus_ehci3_clk.common.hw,
771 		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
772 		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
773 		[CLK_BUS_OHCI2]		= &bus_ohci2_clk.common.hw,
774 		[CLK_BUS_OHCI3]		= &bus_ohci3_clk.common.hw,
775 		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
776 		[CLK_BUS_TCON0]		= &bus_tcon0_clk.common.hw,
777 		[CLK_BUS_TCON1]		= &bus_tcon1_clk.common.hw,
778 		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
779 		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
780 		[CLK_BUS_TVE]		= &bus_tve_clk.common.hw,
781 		[CLK_BUS_HDMI]		= &bus_hdmi_clk.common.hw,
782 		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
783 		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
784 		[CLK_BUS_MSGBOX]	= &bus_msgbox_clk.common.hw,
785 		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
786 		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
787 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
788 		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
789 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
790 		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
791 		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
792 		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
793 		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
794 		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
795 		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
796 		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
797 		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
798 		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
799 		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
800 		[CLK_BUS_SCR0]		= &bus_scr0_clk.common.hw,
801 		[CLK_BUS_EPHY]		= &bus_ephy_clk.common.hw,
802 		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
803 		[CLK_THS]		= &ths_clk.common.hw,
804 		[CLK_NAND]		= &nand_clk.common.hw,
805 		[CLK_MMC0]		= &mmc0_clk.common.hw,
806 		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
807 		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
808 		[CLK_MMC1]		= &mmc1_clk.common.hw,
809 		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
810 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
811 		[CLK_MMC2]		= &mmc2_clk.common.hw,
812 		[CLK_MMC2_SAMPLE]	= &mmc2_sample_clk.common.hw,
813 		[CLK_MMC2_OUTPUT]	= &mmc2_output_clk.common.hw,
814 		[CLK_TS]		= &ts_clk.common.hw,
815 		[CLK_CE]		= &ce_clk.common.hw,
816 		[CLK_SPI0]		= &spi0_clk.common.hw,
817 		[CLK_SPI1]		= &spi1_clk.common.hw,
818 		[CLK_I2S0]		= &i2s0_clk.common.hw,
819 		[CLK_I2S1]		= &i2s1_clk.common.hw,
820 		[CLK_I2S2]		= &i2s2_clk.common.hw,
821 		[CLK_SPDIF]		= &spdif_clk.common.hw,
822 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
823 		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
824 		[CLK_USB_PHY2]		= &usb_phy2_clk.common.hw,
825 		[CLK_USB_PHY3]		= &usb_phy3_clk.common.hw,
826 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
827 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
828 		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,
829 		[CLK_USB_OHCI3]		= &usb_ohci3_clk.common.hw,
830 		[CLK_DRAM]		= &dram_clk.common.hw,
831 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
832 		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
833 		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
834 		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
835 		[CLK_DE]		= &de_clk.common.hw,
836 		[CLK_TCON0]		= &tcon_clk.common.hw,
837 		[CLK_TVE]		= &tve_clk.common.hw,
838 		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
839 		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
840 		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
841 		[CLK_CSI_MCLK]		= &csi_mclk_clk.common.hw,
842 		[CLK_VE]		= &ve_clk.common.hw,
843 		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
844 		[CLK_AVS]		= &avs_clk.common.hw,
845 		[CLK_HDMI]		= &hdmi_clk.common.hw,
846 		[CLK_HDMI_DDC]		= &hdmi_ddc_clk.common.hw,
847 		[CLK_MBUS]		= &mbus_clk.common.hw,
848 		[CLK_GPU]		= &gpu_clk.common.hw,
849 	},
850 	.num	= CLK_NUMBER_H3,
851 };
852 
853 static struct clk_hw_onecell_data sun50i_h5_hw_clks = {
854 	.hws	= {
855 		[CLK_PLL_CPUX]		= &pll_cpux_clk.common.hw,
856 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
857 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
858 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
859 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
860 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
861 		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
862 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
863 		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
864 		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
865 		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
866 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
867 		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
868 		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
869 		[CLK_CPUX]		= &cpux_clk.common.hw,
870 		[CLK_AXI]		= &axi_clk.common.hw,
871 		[CLK_AHB1]		= &ahb1_clk.common.hw,
872 		[CLK_APB1]		= &apb1_clk.common.hw,
873 		[CLK_APB2]		= &apb2_clk.common.hw,
874 		[CLK_AHB2]		= &ahb2_clk.common.hw,
875 		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
876 		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
877 		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
878 		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
879 		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
880 		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
881 		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
882 		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
883 		[CLK_BUS_TS]		= &bus_ts_clk.common.hw,
884 		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
885 		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
886 		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
887 		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
888 		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
889 		[CLK_BUS_EHCI1]		= &bus_ehci1_clk.common.hw,
890 		[CLK_BUS_EHCI2]		= &bus_ehci2_clk.common.hw,
891 		[CLK_BUS_EHCI3]		= &bus_ehci3_clk.common.hw,
892 		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
893 		[CLK_BUS_OHCI1]		= &bus_ohci1_clk.common.hw,
894 		[CLK_BUS_OHCI2]		= &bus_ohci2_clk.common.hw,
895 		[CLK_BUS_OHCI3]		= &bus_ohci3_clk.common.hw,
896 		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
897 		[CLK_BUS_TCON0]		= &bus_tcon0_clk.common.hw,
898 		[CLK_BUS_TCON1]		= &bus_tcon1_clk.common.hw,
899 		[CLK_BUS_DEINTERLACE]	= &bus_deinterlace_clk.common.hw,
900 		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
901 		[CLK_BUS_TVE]		= &bus_tve_clk.common.hw,
902 		[CLK_BUS_HDMI]		= &bus_hdmi_clk.common.hw,
903 		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
904 		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
905 		[CLK_BUS_MSGBOX]	= &bus_msgbox_clk.common.hw,
906 		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
907 		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
908 		[CLK_BUS_SPDIF]		= &bus_spdif_clk.common.hw,
909 		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
910 		[CLK_BUS_THS]		= &bus_ths_clk.common.hw,
911 		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
912 		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
913 		[CLK_BUS_I2S2]		= &bus_i2s2_clk.common.hw,
914 		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
915 		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
916 		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
917 		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
918 		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
919 		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
920 		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
921 		[CLK_BUS_SCR0]		= &bus_scr0_clk.common.hw,
922 		[CLK_BUS_SCR1]		= &bus_scr1_clk.common.hw,
923 		[CLK_BUS_EPHY]		= &bus_ephy_clk.common.hw,
924 		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
925 		[CLK_THS]		= &ths_clk.common.hw,
926 		[CLK_NAND]		= &nand_clk.common.hw,
927 		[CLK_MMC0]		= &mmc0_clk.common.hw,
928 		[CLK_MMC1]		= &mmc1_clk.common.hw,
929 		[CLK_MMC2]		= &mmc2_clk.common.hw,
930 		[CLK_TS]		= &ts_clk.common.hw,
931 		[CLK_CE]		= &ce_clk.common.hw,
932 		[CLK_SPI0]		= &spi0_clk.common.hw,
933 		[CLK_SPI1]		= &spi1_clk.common.hw,
934 		[CLK_I2S0]		= &i2s0_clk.common.hw,
935 		[CLK_I2S1]		= &i2s1_clk.common.hw,
936 		[CLK_I2S2]		= &i2s2_clk.common.hw,
937 		[CLK_SPDIF]		= &spdif_clk.common.hw,
938 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
939 		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
940 		[CLK_USB_PHY2]		= &usb_phy2_clk.common.hw,
941 		[CLK_USB_PHY3]		= &usb_phy3_clk.common.hw,
942 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
943 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
944 		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,
945 		[CLK_USB_OHCI3]		= &usb_ohci3_clk.common.hw,
946 		[CLK_DRAM]		= &dram_clk.common.hw,
947 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
948 		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
949 		[CLK_DRAM_DEINTERLACE]	= &dram_deinterlace_clk.common.hw,
950 		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
951 		[CLK_DE]		= &de_clk.common.hw,
952 		[CLK_TCON0]		= &tcon_clk.common.hw,
953 		[CLK_TVE]		= &tve_clk.common.hw,
954 		[CLK_DEINTERLACE]	= &deinterlace_clk.common.hw,
955 		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
956 		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
957 		[CLK_CSI_MCLK]		= &csi_mclk_clk.common.hw,
958 		[CLK_VE]		= &ve_clk.common.hw,
959 		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
960 		[CLK_AVS]		= &avs_clk.common.hw,
961 		[CLK_HDMI]		= &hdmi_clk.common.hw,
962 		[CLK_HDMI_DDC]		= &hdmi_ddc_clk.common.hw,
963 		[CLK_MBUS]		= &mbus_clk.common.hw,
964 		[CLK_GPU]		= &gpu_clk.common.hw,
965 	},
966 	.num	= CLK_NUMBER_H5,
967 };
968 
969 static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
970 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
971 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
972 	[RST_USB_PHY2]		=  { 0x0cc, BIT(2) },
973 	[RST_USB_PHY3]		=  { 0x0cc, BIT(3) },
974 
975 	[RST_MBUS]		=  { 0x0fc, BIT(31) },
976 
977 	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
978 	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
979 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
980 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
981 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
982 	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
983 	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
984 	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
985 	[RST_BUS_TS]		=  { 0x2c0, BIT(18) },
986 	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
987 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
988 	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
989 	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
990 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
991 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },
992 	[RST_BUS_EHCI2]		=  { 0x2c0, BIT(26) },
993 	[RST_BUS_EHCI3]		=  { 0x2c0, BIT(27) },
994 	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(28) },
995 	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
996 	[RST_BUS_OHCI2]		=  { 0x2c0, BIT(30) },
997 	[RST_BUS_OHCI3]		=  { 0x2c0, BIT(31) },
998 
999 	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
1000 	[RST_BUS_TCON0]		=  { 0x2c4, BIT(3) },
1001 	[RST_BUS_TCON1]		=  { 0x2c4, BIT(4) },
1002 	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
1003 	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
1004 	[RST_BUS_TVE]		=  { 0x2c4, BIT(9) },
1005 	[RST_BUS_HDMI0]		=  { 0x2c4, BIT(10) },
1006 	[RST_BUS_HDMI1]		=  { 0x2c4, BIT(11) },
1007 	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
1008 	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
1009 	[RST_BUS_MSGBOX]	=  { 0x2c4, BIT(21) },
1010 	[RST_BUS_SPINLOCK]	=  { 0x2c4, BIT(22) },
1011 	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
1012 
1013 	[RST_BUS_EPHY]		=  { 0x2c8, BIT(2) },
1014 
1015 	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
1016 	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
1017 	[RST_BUS_THS]		=  { 0x2d0, BIT(8) },
1018 	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
1019 	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
1020 	[RST_BUS_I2S2]		=  { 0x2d0, BIT(14) },
1021 
1022 	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
1023 	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
1024 	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
1025 	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
1026 	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
1027 	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
1028 	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
1029 	[RST_BUS_SCR0]		=  { 0x2d8, BIT(20) },
1030 };
1031 
1032 static struct ccu_reset_map sun50i_h5_ccu_resets[] = {
1033 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
1034 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
1035 	[RST_USB_PHY2]		=  { 0x0cc, BIT(2) },
1036 	[RST_USB_PHY3]		=  { 0x0cc, BIT(3) },
1037 
1038 	[RST_MBUS]		=  { 0x0fc, BIT(31) },
1039 
1040 	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
1041 	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
1042 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
1043 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
1044 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
1045 	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
1046 	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
1047 	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
1048 	[RST_BUS_TS]		=  { 0x2c0, BIT(18) },
1049 	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
1050 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
1051 	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
1052 	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
1053 	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(24) },
1054 	[RST_BUS_EHCI1]		=  { 0x2c0, BIT(25) },
1055 	[RST_BUS_EHCI2]		=  { 0x2c0, BIT(26) },
1056 	[RST_BUS_EHCI3]		=  { 0x2c0, BIT(27) },
1057 	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(28) },
1058 	[RST_BUS_OHCI1]		=  { 0x2c0, BIT(29) },
1059 	[RST_BUS_OHCI2]		=  { 0x2c0, BIT(30) },
1060 	[RST_BUS_OHCI3]		=  { 0x2c0, BIT(31) },
1061 
1062 	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
1063 	[RST_BUS_TCON0]		=  { 0x2c4, BIT(3) },
1064 	[RST_BUS_TCON1]		=  { 0x2c4, BIT(4) },
1065 	[RST_BUS_DEINTERLACE]	=  { 0x2c4, BIT(5) },
1066 	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
1067 	[RST_BUS_TVE]		=  { 0x2c4, BIT(9) },
1068 	[RST_BUS_HDMI0]		=  { 0x2c4, BIT(10) },
1069 	[RST_BUS_HDMI1]		=  { 0x2c4, BIT(11) },
1070 	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
1071 	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
1072 	[RST_BUS_MSGBOX]	=  { 0x2c4, BIT(21) },
1073 	[RST_BUS_SPINLOCK]	=  { 0x2c4, BIT(22) },
1074 	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
1075 
1076 	[RST_BUS_EPHY]		=  { 0x2c8, BIT(2) },
1077 
1078 	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
1079 	[RST_BUS_SPDIF]		=  { 0x2d0, BIT(1) },
1080 	[RST_BUS_THS]		=  { 0x2d0, BIT(8) },
1081 	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
1082 	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
1083 	[RST_BUS_I2S2]		=  { 0x2d0, BIT(14) },
1084 
1085 	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
1086 	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
1087 	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
1088 	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
1089 	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
1090 	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
1091 	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
1092 	[RST_BUS_SCR0]		=  { 0x2d8, BIT(20) },
1093 	[RST_BUS_SCR1]		=  { 0x2d8, BIT(20) },
1094 };
1095 
1096 static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {
1097 	.ccu_clks	= sun8i_h3_ccu_clks,
1098 	.num_ccu_clks	= ARRAY_SIZE(sun8i_h3_ccu_clks),
1099 
1100 	.hw_clks	= &sun8i_h3_hw_clks,
1101 
1102 	.resets		= sun8i_h3_ccu_resets,
1103 	.num_resets	= ARRAY_SIZE(sun8i_h3_ccu_resets),
1104 };
1105 
1106 static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
1107 	.ccu_clks	= sun50i_h5_ccu_clks,
1108 	.num_ccu_clks	= ARRAY_SIZE(sun50i_h5_ccu_clks),
1109 
1110 	.hw_clks	= &sun50i_h5_hw_clks,
1111 
1112 	.resets		= sun50i_h5_ccu_resets,
1113 	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),
1114 };
1115 
1116 static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
1117 	.common	= &pll_cpux_clk.common,
1118 	/* copy from pll_cpux_clk */
1119 	.enable	= BIT(31),
1120 	.lock	= BIT(28),
1121 };
1122 
1123 static struct ccu_mux_nb sun8i_h3_cpu_nb = {
1124 	.common		= &cpux_clk.common,
1125 	.cm		= &cpux_clk.mux,
1126 	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
1127 	.bypass_index	= 1, /* index of 24 MHz oscillator */
1128 };
1129 
1130 static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
1131 					const struct sunxi_ccu_desc *desc)
1132 {
1133 	void __iomem *reg;
1134 	u32 val;
1135 
1136 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1137 	if (IS_ERR(reg)) {
1138 		pr_err("%pOF: Could not map the clock registers\n", node);
1139 		return;
1140 	}
1141 
1142 	/* Force the PLL-Audio-1x divider to 1 */
1143 	val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
1144 	val &= ~GENMASK(19, 16);
1145 	writel(val | (0 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
1146 
1147 	sunxi_ccu_probe(node, reg, desc);
1148 
1149 	/* Gate then ungate PLL CPU after any rate changes */
1150 	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
1151 
1152 	/* Reparent CPU during PLL CPU rate changes */
1153 	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
1154 				  &sun8i_h3_cpu_nb);
1155 }
1156 
1157 static void __init sun8i_h3_ccu_setup(struct device_node *node)
1158 {
1159 	sunxi_h3_h5_ccu_init(node, &sun8i_h3_ccu_desc);
1160 }
1161 CLK_OF_DECLARE(sun8i_h3_ccu, "allwinner,sun8i-h3-ccu",
1162 	       sun8i_h3_ccu_setup);
1163 
1164 static void __init sun50i_h5_ccu_setup(struct device_node *node)
1165 {
1166 	sunxi_h3_h5_ccu_init(node, &sun50i_h5_ccu_desc);
1167 }
1168 CLK_OF_DECLARE(sun50i_h5_ccu, "allwinner,sun50i-h5-ccu",
1169 	       sun50i_h5_ccu_setup);
1170