1 /* 2 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/clk-provider.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 21 #include "ccu_common.h" 22 #include "ccu_div.h" 23 #include "ccu_gate.h" 24 #include "ccu_reset.h" 25 26 #include "ccu-sun8i-de2.h" 27 28 static SUNXI_CCU_GATE(bus_mixer0_clk, "bus-mixer0", "bus-de", 29 0x04, BIT(0), 0); 30 static SUNXI_CCU_GATE(bus_mixer1_clk, "bus-mixer1", "bus-de", 31 0x04, BIT(1), 0); 32 static SUNXI_CCU_GATE(bus_wb_clk, "bus-wb", "bus-de", 33 0x04, BIT(2), 0); 34 35 static SUNXI_CCU_GATE(mixer0_clk, "mixer0", "mixer0-div", 36 0x00, BIT(0), CLK_SET_RATE_PARENT); 37 static SUNXI_CCU_GATE(mixer1_clk, "mixer1", "mixer1-div", 38 0x00, BIT(1), CLK_SET_RATE_PARENT); 39 static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div", 40 0x00, BIT(2), CLK_SET_RATE_PARENT); 41 42 static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, 43 CLK_SET_RATE_PARENT); 44 static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, 45 CLK_SET_RATE_PARENT); 46 47 static SUNXI_CCU_M(mixer0_div_a83_clk, "mixer0-div", "pll-de", 0x0c, 0, 4, 48 CLK_SET_RATE_PARENT); 49 static SUNXI_CCU_M(mixer1_div_a83_clk, "mixer1-div", "pll-de", 0x0c, 4, 4, 50 CLK_SET_RATE_PARENT); 51 static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de", 0x0c, 8, 4, 52 CLK_SET_RATE_PARENT); 53 54 static struct ccu_common *sun8i_a83t_de2_clks[] = { 55 &mixer0_clk.common, 56 &mixer1_clk.common, 57 &wb_clk.common, 58 59 &bus_mixer0_clk.common, 60 &bus_mixer1_clk.common, 61 &bus_wb_clk.common, 62 63 &mixer0_div_a83_clk.common, 64 &mixer1_div_a83_clk.common, 65 &wb_div_a83_clk.common, 66 }; 67 68 static struct ccu_common *sun8i_v3s_de2_clks[] = { 69 &mixer0_clk.common, 70 &wb_clk.common, 71 72 &bus_mixer0_clk.common, 73 &bus_wb_clk.common, 74 75 &mixer0_div_clk.common, 76 &wb_div_clk.common, 77 }; 78 79 static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { 80 .hws = { 81 [CLK_MIXER0] = &mixer0_clk.common.hw, 82 [CLK_MIXER1] = &mixer1_clk.common.hw, 83 [CLK_WB] = &wb_clk.common.hw, 84 85 [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, 86 [CLK_BUS_MIXER1] = &bus_mixer1_clk.common.hw, 87 [CLK_BUS_WB] = &bus_wb_clk.common.hw, 88 89 [CLK_MIXER0_DIV] = &mixer0_div_a83_clk.common.hw, 90 [CLK_MIXER1_DIV] = &mixer1_div_a83_clk.common.hw, 91 [CLK_WB_DIV] = &wb_div_a83_clk.common.hw, 92 }, 93 .num = CLK_NUMBER, 94 }; 95 96 static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = { 97 .hws = { 98 [CLK_MIXER0] = &mixer0_clk.common.hw, 99 [CLK_WB] = &wb_clk.common.hw, 100 101 [CLK_BUS_MIXER0] = &bus_mixer0_clk.common.hw, 102 [CLK_BUS_WB] = &bus_wb_clk.common.hw, 103 104 [CLK_MIXER0_DIV] = &mixer0_div_clk.common.hw, 105 [CLK_WB_DIV] = &wb_div_clk.common.hw, 106 }, 107 .num = CLK_NUMBER, 108 }; 109 110 static struct ccu_reset_map sun8i_a83t_de2_resets[] = { 111 [RST_MIXER0] = { 0x08, BIT(0) }, 112 /* 113 * For A83T, H3 and R40, mixer1 reset line is shared with wb, so 114 * only RST_WB is exported here. 115 * For V3s there's just no mixer1, so it also shares this struct. 116 */ 117 [RST_WB] = { 0x08, BIT(2) }, 118 }; 119 120 static struct ccu_reset_map sun50i_a64_de2_resets[] = { 121 [RST_MIXER0] = { 0x08, BIT(0) }, 122 [RST_MIXER1] = { 0x08, BIT(1) }, 123 [RST_WB] = { 0x08, BIT(2) }, 124 }; 125 126 static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { 127 .ccu_clks = sun8i_a83t_de2_clks, 128 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), 129 130 .hw_clks = &sun8i_a83t_de2_hw_clks, 131 132 .resets = sun8i_a83t_de2_resets, 133 .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), 134 }; 135 136 static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { 137 .ccu_clks = sun8i_a83t_de2_clks, 138 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), 139 140 .hw_clks = &sun8i_a83t_de2_hw_clks, 141 142 .resets = sun50i_a64_de2_resets, 143 .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), 144 }; 145 146 static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { 147 .ccu_clks = sun8i_v3s_de2_clks, 148 .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks), 149 150 .hw_clks = &sun8i_v3s_de2_hw_clks, 151 152 .resets = sun8i_a83t_de2_resets, 153 .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), 154 }; 155 156 static int sunxi_de2_clk_probe(struct platform_device *pdev) 157 { 158 struct resource *res; 159 struct clk *bus_clk, *mod_clk; 160 struct reset_control *rstc; 161 void __iomem *reg; 162 const struct sunxi_ccu_desc *ccu_desc; 163 int ret; 164 165 ccu_desc = of_device_get_match_data(&pdev->dev); 166 if (!ccu_desc) 167 return -EINVAL; 168 169 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 170 reg = devm_ioremap_resource(&pdev->dev, res); 171 if (IS_ERR(reg)) 172 return PTR_ERR(reg); 173 174 bus_clk = devm_clk_get(&pdev->dev, "bus"); 175 if (IS_ERR(bus_clk)) { 176 ret = PTR_ERR(bus_clk); 177 if (ret != -EPROBE_DEFER) 178 dev_err(&pdev->dev, "Couldn't get bus clk: %d\n", ret); 179 return ret; 180 } 181 182 mod_clk = devm_clk_get(&pdev->dev, "mod"); 183 if (IS_ERR(mod_clk)) { 184 ret = PTR_ERR(mod_clk); 185 if (ret != -EPROBE_DEFER) 186 dev_err(&pdev->dev, "Couldn't get mod clk: %d\n", ret); 187 return ret; 188 } 189 190 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 191 if (IS_ERR(rstc)) { 192 ret = PTR_ERR(rstc); 193 if (ret != -EPROBE_DEFER) 194 dev_err(&pdev->dev, 195 "Couldn't get reset control: %d\n", ret); 196 return ret; 197 } 198 199 /* The clocks need to be enabled for us to access the registers */ 200 ret = clk_prepare_enable(bus_clk); 201 if (ret) { 202 dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret); 203 return ret; 204 } 205 206 ret = clk_prepare_enable(mod_clk); 207 if (ret) { 208 dev_err(&pdev->dev, "Couldn't enable mod clk: %d\n", ret); 209 goto err_disable_bus_clk; 210 } 211 212 /* The reset control needs to be asserted for the controls to work */ 213 ret = reset_control_deassert(rstc); 214 if (ret) { 215 dev_err(&pdev->dev, 216 "Couldn't deassert reset control: %d\n", ret); 217 goto err_disable_mod_clk; 218 } 219 220 ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc); 221 if (ret) 222 goto err_assert_reset; 223 224 return 0; 225 226 err_assert_reset: 227 reset_control_assert(rstc); 228 err_disable_mod_clk: 229 clk_disable_unprepare(mod_clk); 230 err_disable_bus_clk: 231 clk_disable_unprepare(bus_clk); 232 return ret; 233 } 234 235 static const struct of_device_id sunxi_de2_clk_ids[] = { 236 { 237 .compatible = "allwinner,sun8i-a83t-de2-clk", 238 .data = &sun8i_a83t_de2_clk_desc, 239 }, 240 { 241 .compatible = "allwinner,sun8i-v3s-de2-clk", 242 .data = &sun8i_v3s_de2_clk_desc, 243 }, 244 { 245 .compatible = "allwinner,sun50i-h5-de2-clk", 246 .data = &sun50i_a64_de2_clk_desc, 247 }, 248 /* 249 * The Allwinner A64 SoC needs some bit to be poke in syscon to make 250 * DE2 really working. 251 * So there's currently no A64 compatible here. 252 * H5 shares the same reset line with A64, so here H5 is using the 253 * clock description of A64. 254 */ 255 { } 256 }; 257 258 static struct platform_driver sunxi_de2_clk_driver = { 259 .probe = sunxi_de2_clk_probe, 260 .driver = { 261 .name = "sunxi-de2-clks", 262 .of_match_table = sunxi_de2_clk_ids, 263 }, 264 }; 265 builtin_platform_driver(sunxi_de2_clk_driver); 266