1 /* 2 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/io.h> 16 #include <linux/of_address.h> 17 #include <linux/platform_device.h> 18 19 #include "ccu_common.h" 20 #include "ccu_reset.h" 21 22 #include "ccu_div.h" 23 #include "ccu_gate.h" 24 #include "ccu_mp.h" 25 #include "ccu_mux.h" 26 #include "ccu_nkmp.h" 27 #include "ccu_nm.h" 28 #include "ccu_phase.h" 29 30 #include "ccu-sun8i-a83t.h" 31 32 #define CCU_SUN8I_A83T_LOCK_REG 0x20c 33 34 /* 35 * The CPU PLLs are actually NP clocks, with P being /1 or /4. However 36 * P should only be used for output frequencies lower than 228 MHz. 37 * Neither mainline Linux, U-boot, nor the vendor BSPs use these. 38 * 39 * For now we can just model it as a multiplier clock, and force P to /1. 40 */ 41 #define SUN8I_A83T_PLL_C0CPUX_REG 0x000 42 #define SUN8I_A83T_PLL_C1CPUX_REG 0x004 43 44 static struct ccu_mult pll_c0cpux_clk = { 45 .enable = BIT(31), 46 .lock = BIT(0), 47 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 48 .common = { 49 .reg = SUN8I_A83T_PLL_C0CPUX_REG, 50 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 51 .features = CCU_FEATURE_LOCK_REG, 52 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M", 53 &ccu_mult_ops, 54 CLK_SET_RATE_UNGATE), 55 }, 56 }; 57 58 static struct ccu_mult pll_c1cpux_clk = { 59 .enable = BIT(31), 60 .lock = BIT(1), 61 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 62 .common = { 63 .reg = SUN8I_A83T_PLL_C1CPUX_REG, 64 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 65 .features = CCU_FEATURE_LOCK_REG, 66 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M", 67 &ccu_mult_ops, 68 CLK_SET_RATE_UNGATE), 69 }, 70 }; 71 72 /* 73 * The Audio PLL has d1, d2 dividers in addition to the usual N, M 74 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz 75 * and 24.576 MHz, ignore them for now. Enforce the default for them, 76 * which is d1 = 0, d2 = 1. 77 */ 78 #define SUN8I_A83T_PLL_AUDIO_REG 0x008 79 80 /* clock rates doubled for post divider */ 81 static struct ccu_sdm_setting pll_audio_sdm_table[] = { 82 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 }, 83 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 }, 84 }; 85 86 static struct ccu_nm pll_audio_clk = { 87 .enable = BIT(31), 88 .lock = BIT(2), 89 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 90 .m = _SUNXI_CCU_DIV(0, 6), 91 .fixed_post_div = 2, 92 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24), 93 0x284, BIT(31)), 94 .common = { 95 .reg = SUN8I_A83T_PLL_AUDIO_REG, 96 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 97 .features = CCU_FEATURE_LOCK_REG | 98 CCU_FEATURE_FIXED_POSTDIV | 99 CCU_FEATURE_SIGMA_DELTA_MOD, 100 .hw.init = CLK_HW_INIT("pll-audio", "osc24M", 101 &ccu_nm_ops, CLK_SET_RATE_UNGATE), 102 }, 103 }; 104 105 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ 106 static struct ccu_nkmp pll_video0_clk = { 107 .enable = BIT(31), 108 .lock = BIT(3), 109 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 110 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 111 .p = _SUNXI_CCU_DIV(0, 2), /* output divider */ 112 .max_rate = 3000000000UL, 113 .common = { 114 .reg = 0x010, 115 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 116 .features = CCU_FEATURE_LOCK_REG, 117 .hw.init = CLK_HW_INIT("pll-video0", "osc24M", 118 &ccu_nkmp_ops, 119 CLK_SET_RATE_UNGATE), 120 }, 121 }; 122 123 static struct ccu_nkmp pll_ve_clk = { 124 .enable = BIT(31), 125 .lock = BIT(4), 126 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 127 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 128 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 129 .common = { 130 .reg = 0x018, 131 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 132 .features = CCU_FEATURE_LOCK_REG, 133 .hw.init = CLK_HW_INIT("pll-ve", "osc24M", 134 &ccu_nkmp_ops, 135 CLK_SET_RATE_UNGATE), 136 }, 137 }; 138 139 static struct ccu_nkmp pll_ddr_clk = { 140 .enable = BIT(31), 141 .lock = BIT(5), 142 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 143 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 144 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 145 .common = { 146 .reg = 0x020, 147 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 148 .features = CCU_FEATURE_LOCK_REG, 149 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M", 150 &ccu_nkmp_ops, 151 CLK_SET_RATE_UNGATE), 152 }, 153 }; 154 155 static struct ccu_nkmp pll_periph_clk = { 156 .enable = BIT(31), 157 .lock = BIT(6), 158 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 159 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 160 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 161 .common = { 162 .reg = 0x028, 163 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 164 .features = CCU_FEATURE_LOCK_REG, 165 .hw.init = CLK_HW_INIT("pll-periph", "osc24M", 166 &ccu_nkmp_ops, 167 CLK_SET_RATE_UNGATE), 168 }, 169 }; 170 171 static struct ccu_nkmp pll_gpu_clk = { 172 .enable = BIT(31), 173 .lock = BIT(7), 174 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 175 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 176 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 177 .common = { 178 .reg = 0x038, 179 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 180 .features = CCU_FEATURE_LOCK_REG, 181 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", 182 &ccu_nkmp_ops, 183 CLK_SET_RATE_UNGATE), 184 }, 185 }; 186 187 static struct ccu_nkmp pll_hsic_clk = { 188 .enable = BIT(31), 189 .lock = BIT(8), 190 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 191 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 192 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 193 .common = { 194 .reg = 0x044, 195 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 196 .features = CCU_FEATURE_LOCK_REG, 197 .hw.init = CLK_HW_INIT("pll-hsic", "osc24M", 198 &ccu_nkmp_ops, 199 CLK_SET_RATE_UNGATE), 200 }, 201 }; 202 203 static struct ccu_nkmp pll_de_clk = { 204 .enable = BIT(31), 205 .lock = BIT(9), 206 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 207 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 208 .p = _SUNXI_CCU_DIV(18, 1), /* output divider */ 209 .common = { 210 .reg = 0x048, 211 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 212 .features = CCU_FEATURE_LOCK_REG, 213 .hw.init = CLK_HW_INIT("pll-de", "osc24M", 214 &ccu_nkmp_ops, 215 CLK_SET_RATE_UNGATE), 216 }, 217 }; 218 219 static struct ccu_nkmp pll_video1_clk = { 220 .enable = BIT(31), 221 .lock = BIT(10), 222 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 223 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */ 224 .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */ 225 .max_rate = 3000000000UL, 226 .common = { 227 .reg = 0x04c, 228 .lock_reg = CCU_SUN8I_A83T_LOCK_REG, 229 .features = CCU_FEATURE_LOCK_REG, 230 .hw.init = CLK_HW_INIT("pll-video1", "osc24M", 231 &ccu_nkmp_ops, 232 CLK_SET_RATE_UNGATE), 233 }, 234 }; 235 236 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" }; 237 static SUNXI_CCU_MUX(c0cpux_clk, "c0cpux", c0cpux_parents, 238 0x50, 12, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 239 240 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" }; 241 static SUNXI_CCU_MUX(c1cpux_clk, "c1cpux", c1cpux_parents, 242 0x50, 28, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 243 244 static SUNXI_CCU_M(axi0_clk, "axi0", "c0cpux", 0x050, 0, 2, 0); 245 static SUNXI_CCU_M(axi1_clk, "axi1", "c1cpux", 0x050, 16, 2, 0); 246 247 static const char * const ahb1_parents[] = { "osc16M-d512", "osc24M", 248 "pll-periph", 249 "pll-periph" }; 250 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 251 { .index = 2, .shift = 6, .width = 2 }, 252 { .index = 3, .shift = 6, .width = 2 }, 253 }; 254 static struct ccu_div ahb1_clk = { 255 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 256 .mux = { 257 .shift = 12, 258 .width = 2, 259 260 .var_predivs = ahb1_predivs, 261 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 262 }, 263 .common = { 264 .reg = 0x054, 265 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 266 ahb1_parents, 267 &ccu_div_ops, 268 0), 269 }, 270 }; 271 272 static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0); 273 274 static const char * const apb2_parents[] = { "osc16M-d512", "osc24M", 275 "pll-periph", "pll-periph" }; 276 277 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 278 0, 5, /* M */ 279 16, 2, /* P */ 280 24, 2, /* mux */ 281 0); 282 283 static const char * const ahb2_parents[] = { "ahb1", "pll-periph" }; 284 static const struct ccu_mux_fixed_prediv ahb2_prediv = { 285 .index = 1, .div = 2 286 }; 287 static struct ccu_mux ahb2_clk = { 288 .mux = { 289 .shift = 0, 290 .width = 2, 291 .fixed_predivs = &ahb2_prediv, 292 .n_predivs = 1, 293 }, 294 .common = { 295 .reg = 0x05c, 296 .hw.init = CLK_HW_INIT_PARENTS("ahb2", 297 ahb2_parents, 298 &ccu_mux_ops, 299 0), 300 }, 301 }; 302 303 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 304 0x060, BIT(1), 0); 305 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1", 306 0x060, BIT(5), 0); 307 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 308 0x060, BIT(6), 0); 309 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 310 0x060, BIT(8), 0); 311 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 312 0x060, BIT(9), 0); 313 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 314 0x060, BIT(10), 0); 315 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 316 0x060, BIT(13), 0); 317 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 318 0x060, BIT(14), 0); 319 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 320 0x060, BIT(17), 0); 321 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 322 0x060, BIT(19), 0); 323 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 324 0x060, BIT(20), 0); 325 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 326 0x060, BIT(21), 0); 327 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 328 0x060, BIT(24), 0); 329 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb2", 330 0x060, BIT(26), 0); 331 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", 332 0x060, BIT(27), 0); 333 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb2", 334 0x060, BIT(29), 0); 335 336 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 337 0x064, BIT(0), 0); 338 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 339 0x064, BIT(4), 0); 340 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", 341 0x064, BIT(5), 0); 342 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 343 0x064, BIT(8), 0); 344 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", 345 0x064, BIT(11), 0); 346 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 347 0x064, BIT(12), 0); 348 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 349 0x064, BIT(20), 0); 350 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 351 0x064, BIT(21), 0); 352 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 353 0x064, BIT(22), 0); 354 355 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 356 0x068, BIT(1), 0); 357 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 358 0x068, BIT(5), 0); 359 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 360 0x068, BIT(12), 0); 361 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 362 0x068, BIT(13), 0); 363 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 364 0x068, BIT(14), 0); 365 static SUNXI_CCU_GATE(bus_tdm_clk, "bus-tdm", "apb1", 366 0x068, BIT(15), 0); 367 368 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 369 0x06c, BIT(0), 0); 370 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 371 0x06c, BIT(1), 0); 372 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 373 0x06c, BIT(2), 0); 374 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 375 0x06c, BIT(16), 0); 376 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 377 0x06c, BIT(17), 0); 378 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 379 0x06c, BIT(18), 0); 380 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 381 0x06c, BIT(19), 0); 382 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 383 0x06c, BIT(20), 0); 384 385 static const char * const cci400_parents[] = { "osc24M", "pll-periph", 386 "pll-hsic" }; 387 static struct ccu_div cci400_clk = { 388 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, 0), 389 .mux = _SUNXI_CCU_MUX(24, 2), 390 .common = { 391 .reg = 0x078, 392 .hw.init = CLK_HW_INIT_PARENTS("cci400", 393 cci400_parents, 394 &ccu_div_ops, 395 CLK_IS_CRITICAL), 396 }, 397 }; 398 399 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; 400 401 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 402 0x080, 403 0, 4, /* M */ 404 16, 2, /* P */ 405 24, 2, /* mux */ 406 BIT(31), /* gate */ 407 0); 408 409 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 410 0x088, 411 0, 4, /* M */ 412 16, 2, /* P */ 413 24, 2, /* mux */ 414 BIT(31), /* gate */ 415 0); 416 417 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0", 418 0x088, 20, 3, 0); 419 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0", 420 0x088, 8, 3, 0); 421 422 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 423 0x08c, 424 0, 4, /* M */ 425 16, 2, /* P */ 426 24, 2, /* mux */ 427 BIT(31), /* gate */ 428 0); 429 430 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1", 431 0x08c, 20, 3, 0); 432 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1", 433 0x08c, 8, 3, 0); 434 435 static SUNXI_CCU_MP_MMC_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 436 0x090, 0); 437 438 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2", 439 0x090, 20, 3, 0); 440 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2", 441 0x090, 8, 3, 0); 442 443 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 444 0x09c, 445 0, 4, /* M */ 446 16, 2, /* P */ 447 24, 2, /* mux */ 448 BIT(31), /* gate */ 449 0); 450 451 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 452 0x0a0, 453 0, 4, /* M */ 454 16, 2, /* P */ 455 24, 4, /* mux */ 456 BIT(31), /* gate */ 457 0); 458 459 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 460 0x0a4, 461 0, 4, /* M */ 462 16, 2, /* P */ 463 24, 4, /* mux */ 464 BIT(31), /* gate */ 465 0); 466 467 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio", 468 0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 469 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio", 470 0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 471 static SUNXI_CCU_M_WITH_GATE(i2s2_clk, "i2s2", "pll-audio", 472 0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 473 static SUNXI_CCU_M_WITH_GATE(tdm_clk, "tdm", "pll-audio", 474 0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 475 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 476 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 477 478 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 479 0x0cc, BIT(8), 0); 480 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 481 0x0cc, BIT(9), 0); 482 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 483 0x0cc, BIT(10), 0); 484 static struct ccu_gate usb_hsic_12m_clk = { 485 .enable = BIT(11), 486 .common = { 487 .reg = 0x0cc, 488 .prediv = 2, 489 .features = CCU_FEATURE_ALL_PREDIV, 490 .hw.init = CLK_HW_INIT("usb-hsic-12m", "osc24M", 491 &ccu_gate_ops, 0), 492 } 493 }; 494 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 495 0x0cc, BIT(16), 0); 496 497 /* TODO divider has minimum of 2 */ 498 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL); 499 500 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 501 0x100, BIT(0), 0); 502 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 503 0x100, BIT(1), 0); 504 505 static const char * const tcon0_parents[] = { "pll-video0" }; 506 static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 507 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT); 508 509 static const char * const tcon1_parents[] = { "pll-video1" }; 510 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents, 511 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); 512 513 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0); 514 515 static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0); 516 517 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-de", 518 "osc24M" }; 519 static const u8 csi_mclk_table[] = { 0, 3, 5 }; 520 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk", 521 csi_mclk_parents, csi_mclk_table, 522 0x134, 523 0, 5, /* M */ 524 8, 3, /* mux */ 525 BIT(15), /* gate */ 526 0); 527 528 static const char * const csi_sclk_parents[] = { "pll-periph", "pll-ve" }; 529 static const u8 csi_sclk_table[] = { 0, 5 }; 530 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk", 531 csi_sclk_parents, csi_sclk_table, 532 0x134, 533 16, 4, /* M */ 534 24, 3, /* mux */ 535 BIT(31), /* gate */ 536 0); 537 538 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 539 16, 3, BIT(31), CLK_SET_RATE_PARENT); 540 541 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0); 542 543 static const char * const hdmi_parents[] = { "pll-video1" }; 544 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 545 0x150, 546 0, 4, /* M */ 547 24, 2, /* mux */ 548 BIT(31), /* gate */ 549 CLK_SET_RATE_PARENT); 550 551 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0); 552 553 static const char * const mbus_parents[] = { "osc24M", "pll-periph", 554 "pll-ddr" }; 555 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 556 0x15c, 557 0, 3, /* M */ 558 24, 2, /* mux */ 559 BIT(31), /* gate */ 560 CLK_IS_CRITICAL); 561 562 static const char * const mipi_dsi0_parents[] = { "pll-video0" }; 563 static const u8 mipi_dsi0_table[] = { 8 }; 564 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0", 565 mipi_dsi0_parents, mipi_dsi0_table, 566 0x168, 567 0, 4, /* M */ 568 24, 4, /* mux */ 569 BIT(31), /* gate */ 570 CLK_SET_RATE_PARENT); 571 572 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video0" }; 573 static const u8 mipi_dsi1_table[] = { 0, 9 }; 574 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1", 575 mipi_dsi1_parents, mipi_dsi1_table, 576 0x16c, 577 0, 4, /* M */ 578 24, 4, /* mux */ 579 BIT(31), /* gate */ 580 CLK_SET_RATE_PARENT); 581 582 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0, 583 0, 3, BIT(31), CLK_SET_RATE_PARENT); 584 585 static const char * const gpu_memory_parents[] = { "pll-gpu", "pll-ddr" }; 586 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_memory_clk, "gpu-memory", 587 gpu_memory_parents, 588 0x1a4, 589 0, 3, /* M */ 590 24, 1, /* mux */ 591 BIT(31), /* gate */ 592 CLK_SET_RATE_PARENT); 593 594 static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8, 595 0, 3, BIT(31), CLK_SET_RATE_PARENT); 596 597 static struct ccu_common *sun8i_a83t_ccu_clks[] = { 598 &pll_c0cpux_clk.common, 599 &pll_c1cpux_clk.common, 600 &pll_audio_clk.common, 601 &pll_video0_clk.common, 602 &pll_ve_clk.common, 603 &pll_ddr_clk.common, 604 &pll_periph_clk.common, 605 &pll_gpu_clk.common, 606 &pll_hsic_clk.common, 607 &pll_de_clk.common, 608 &pll_video1_clk.common, 609 &c0cpux_clk.common, 610 &c1cpux_clk.common, 611 &axi0_clk.common, 612 &axi1_clk.common, 613 &ahb1_clk.common, 614 &ahb2_clk.common, 615 &apb1_clk.common, 616 &apb2_clk.common, 617 &bus_mipi_dsi_clk.common, 618 &bus_ss_clk.common, 619 &bus_dma_clk.common, 620 &bus_mmc0_clk.common, 621 &bus_mmc1_clk.common, 622 &bus_mmc2_clk.common, 623 &bus_nand_clk.common, 624 &bus_dram_clk.common, 625 &bus_emac_clk.common, 626 &bus_hstimer_clk.common, 627 &bus_spi0_clk.common, 628 &bus_spi1_clk.common, 629 &bus_otg_clk.common, 630 &bus_ehci0_clk.common, 631 &bus_ehci1_clk.common, 632 &bus_ohci0_clk.common, 633 &bus_ve_clk.common, 634 &bus_tcon0_clk.common, 635 &bus_tcon1_clk.common, 636 &bus_csi_clk.common, 637 &bus_hdmi_clk.common, 638 &bus_de_clk.common, 639 &bus_gpu_clk.common, 640 &bus_msgbox_clk.common, 641 &bus_spinlock_clk.common, 642 &bus_spdif_clk.common, 643 &bus_pio_clk.common, 644 &bus_i2s0_clk.common, 645 &bus_i2s1_clk.common, 646 &bus_i2s2_clk.common, 647 &bus_tdm_clk.common, 648 &bus_i2c0_clk.common, 649 &bus_i2c1_clk.common, 650 &bus_i2c2_clk.common, 651 &bus_uart0_clk.common, 652 &bus_uart1_clk.common, 653 &bus_uart2_clk.common, 654 &bus_uart3_clk.common, 655 &bus_uart4_clk.common, 656 &cci400_clk.common, 657 &nand_clk.common, 658 &mmc0_clk.common, 659 &mmc0_sample_clk.common, 660 &mmc0_output_clk.common, 661 &mmc1_clk.common, 662 &mmc1_sample_clk.common, 663 &mmc1_output_clk.common, 664 &mmc2_clk.common, 665 &mmc2_sample_clk.common, 666 &mmc2_output_clk.common, 667 &ss_clk.common, 668 &spi0_clk.common, 669 &spi1_clk.common, 670 &i2s0_clk.common, 671 &i2s1_clk.common, 672 &i2s2_clk.common, 673 &tdm_clk.common, 674 &spdif_clk.common, 675 &usb_phy0_clk.common, 676 &usb_phy1_clk.common, 677 &usb_hsic_clk.common, 678 &usb_hsic_12m_clk.common, 679 &usb_ohci0_clk.common, 680 &dram_clk.common, 681 &dram_ve_clk.common, 682 &dram_csi_clk.common, 683 &tcon0_clk.common, 684 &tcon1_clk.common, 685 &csi_misc_clk.common, 686 &mipi_csi_clk.common, 687 &csi_mclk_clk.common, 688 &csi_sclk_clk.common, 689 &ve_clk.common, 690 &avs_clk.common, 691 &hdmi_clk.common, 692 &hdmi_slow_clk.common, 693 &mbus_clk.common, 694 &mipi_dsi0_clk.common, 695 &mipi_dsi1_clk.common, 696 &gpu_core_clk.common, 697 &gpu_memory_clk.common, 698 &gpu_hyd_clk.common, 699 }; 700 701 static struct clk_hw_onecell_data sun8i_a83t_hw_clks = { 702 .hws = { 703 [CLK_PLL_C0CPUX] = &pll_c0cpux_clk.common.hw, 704 [CLK_PLL_C1CPUX] = &pll_c1cpux_clk.common.hw, 705 [CLK_PLL_AUDIO] = &pll_audio_clk.common.hw, 706 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 707 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 708 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, 709 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, 710 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 711 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 712 [CLK_PLL_DE] = &pll_de_clk.common.hw, 713 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 714 [CLK_C0CPUX] = &c0cpux_clk.common.hw, 715 [CLK_C1CPUX] = &c1cpux_clk.common.hw, 716 [CLK_AXI0] = &axi0_clk.common.hw, 717 [CLK_AXI1] = &axi1_clk.common.hw, 718 [CLK_AHB1] = &ahb1_clk.common.hw, 719 [CLK_AHB2] = &ahb2_clk.common.hw, 720 [CLK_APB1] = &apb1_clk.common.hw, 721 [CLK_APB2] = &apb2_clk.common.hw, 722 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 723 [CLK_BUS_SS] = &bus_ss_clk.common.hw, 724 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 725 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 726 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 727 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 728 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 729 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 730 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 731 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 732 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 733 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 734 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 735 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 736 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 737 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 738 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 739 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 740 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, 741 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 742 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 743 [CLK_BUS_DE] = &bus_de_clk.common.hw, 744 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 745 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 746 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 747 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 748 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 749 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 750 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 751 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 752 [CLK_BUS_TDM] = &bus_tdm_clk.common.hw, 753 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 754 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 755 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 756 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 757 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 758 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 759 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 760 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 761 [CLK_CCI400] = &cci400_clk.common.hw, 762 [CLK_NAND] = &nand_clk.common.hw, 763 [CLK_MMC0] = &mmc0_clk.common.hw, 764 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 765 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 766 [CLK_MMC1] = &mmc1_clk.common.hw, 767 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 768 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 769 [CLK_MMC2] = &mmc2_clk.common.hw, 770 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 771 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 772 [CLK_SS] = &ss_clk.common.hw, 773 [CLK_SPI0] = &spi0_clk.common.hw, 774 [CLK_SPI1] = &spi1_clk.common.hw, 775 [CLK_I2S0] = &i2s0_clk.common.hw, 776 [CLK_I2S1] = &i2s1_clk.common.hw, 777 [CLK_I2S2] = &i2s2_clk.common.hw, 778 [CLK_TDM] = &tdm_clk.common.hw, 779 [CLK_SPDIF] = &spdif_clk.common.hw, 780 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 781 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 782 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 783 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, 784 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 785 [CLK_DRAM] = &dram_clk.common.hw, 786 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 787 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 788 [CLK_TCON0] = &tcon0_clk.common.hw, 789 [CLK_TCON1] = &tcon1_clk.common.hw, 790 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 791 [CLK_MIPI_CSI] = &mipi_csi_clk.common.hw, 792 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 793 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 794 [CLK_VE] = &ve_clk.common.hw, 795 [CLK_AVS] = &avs_clk.common.hw, 796 [CLK_HDMI] = &hdmi_clk.common.hw, 797 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 798 [CLK_MBUS] = &mbus_clk.common.hw, 799 [CLK_MIPI_DSI0] = &mipi_dsi0_clk.common.hw, 800 [CLK_MIPI_DSI1] = &mipi_dsi1_clk.common.hw, 801 [CLK_GPU_CORE] = &gpu_core_clk.common.hw, 802 [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw, 803 [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw, 804 }, 805 .num = CLK_NUMBER, 806 }; 807 808 static struct ccu_reset_map sun8i_a83t_ccu_resets[] = { 809 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 810 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 811 [RST_USB_HSIC] = { 0x0cc, BIT(2) }, 812 [RST_DRAM] = { 0x0f4, BIT(31) }, 813 [RST_MBUS] = { 0x0fc, BIT(31) }, 814 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 815 [RST_BUS_SS] = { 0x2c0, BIT(5) }, 816 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 817 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 818 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 819 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 820 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 821 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 822 [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 823 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 824 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 825 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 826 [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 827 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) }, 828 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) }, 829 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) }, 830 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 831 [RST_BUS_TCON0] = { 0x2c4, BIT(4) }, 832 [RST_BUS_TCON1] = { 0x2c4, BIT(5) }, 833 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 834 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, 835 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, 836 [RST_BUS_DE] = { 0x2c4, BIT(12) }, 837 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 838 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, 839 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, 840 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 841 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, 842 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 843 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 844 [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, 845 [RST_BUS_TDM] = { 0x2d0, BIT(15) }, 846 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 847 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 848 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 849 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 850 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 851 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 852 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 853 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 854 }; 855 856 static const struct sunxi_ccu_desc sun8i_a83t_ccu_desc = { 857 .ccu_clks = sun8i_a83t_ccu_clks, 858 .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_ccu_clks), 859 860 .hw_clks = &sun8i_a83t_hw_clks, 861 862 .resets = sun8i_a83t_ccu_resets, 863 .num_resets = ARRAY_SIZE(sun8i_a83t_ccu_resets), 864 }; 865 866 #define SUN8I_A83T_PLL_P_SHIFT 16 867 #define SUN8I_A83T_PLL_N_SHIFT 8 868 #define SUN8I_A83T_PLL_N_WIDTH 8 869 870 static void sun8i_a83t_cpu_pll_fixup(void __iomem *reg) 871 { 872 u32 val = readl(reg); 873 874 /* bail out if P divider is not used */ 875 if (!(val & BIT(SUN8I_A83T_PLL_P_SHIFT))) 876 return; 877 878 /* 879 * If P is used, output should be less than 288 MHz. When we 880 * set P to 1, we should also decrease the multiplier so the 881 * output doesn't go out of range, but not too much such that 882 * the multiplier stays above 12, the minimal operation value. 883 * 884 * To keep it simple, set the multiplier to 17, the reset value. 885 */ 886 val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1, 887 SUN8I_A83T_PLL_N_SHIFT); 888 val |= 17 << SUN8I_A83T_PLL_N_SHIFT; 889 890 /* And clear P */ 891 val &= ~BIT(SUN8I_A83T_PLL_P_SHIFT); 892 893 writel(val, reg); 894 } 895 896 static int sun8i_a83t_ccu_probe(struct platform_device *pdev) 897 { 898 struct resource *res; 899 void __iomem *reg; 900 u32 val; 901 902 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 903 reg = devm_ioremap_resource(&pdev->dev, res); 904 if (IS_ERR(reg)) 905 return PTR_ERR(reg); 906 907 /* Enforce d1 = 0, d2 = 1 for Audio PLL */ 908 val = readl(reg + SUN8I_A83T_PLL_AUDIO_REG); 909 val &= ~BIT(16); 910 val |= BIT(18); 911 writel(val, reg + SUN8I_A83T_PLL_AUDIO_REG); 912 913 /* Enforce P = 1 for both CPU cluster PLLs */ 914 sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C0CPUX_REG); 915 sun8i_a83t_cpu_pll_fixup(reg + SUN8I_A83T_PLL_C1CPUX_REG); 916 917 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun8i_a83t_ccu_desc); 918 } 919 920 static const struct of_device_id sun8i_a83t_ccu_ids[] = { 921 { .compatible = "allwinner,sun8i-a83t-ccu" }, 922 { } 923 }; 924 925 static struct platform_driver sun8i_a83t_ccu_driver = { 926 .probe = sun8i_a83t_ccu_probe, 927 .driver = { 928 .name = "sun8i-a83t-ccu", 929 .of_match_table = sun8i_a83t_ccu_ids, 930 }, 931 }; 932 builtin_platform_driver(sun8i_a83t_ccu_driver); 933