1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/of_address.h>
9 
10 #include "ccu_common.h"
11 #include "ccu_reset.h"
12 
13 #include "ccu_div.h"
14 #include "ccu_gate.h"
15 #include "ccu_mp.h"
16 #include "ccu_mult.h"
17 #include "ccu_nk.h"
18 #include "ccu_nkm.h"
19 #include "ccu_nkmp.h"
20 #include "ccu_nm.h"
21 #include "ccu_phase.h"
22 
23 #include "ccu-sun8i-a23-a33.h"
24 
25 static struct ccu_nkmp pll_cpux_clk = {
26 	.enable = BIT(31),
27 	.lock	= BIT(28),
28 
29 	.n	= _SUNXI_CCU_MULT(8, 5),
30 	.k	= _SUNXI_CCU_MULT(4, 2),
31 	.m	= _SUNXI_CCU_DIV(0, 2),
32 	.p	= _SUNXI_CCU_DIV_MAX(16, 2, 4),
33 
34 	.common	= {
35 		.reg		= 0x000,
36 		.hw.init	= CLK_HW_INIT("pll-cpux", "osc24M",
37 					      &ccu_nkmp_ops,
38 					      0),
39 	},
40 };
41 
42 /*
43  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
44  * the base (2x, 4x and 8x), and one variable divider (the one true
45  * pll audio).
46  *
47  * With sigma-delta modulation for fractional-N on the audio PLL,
48  * we have to use specific dividers. This means the variable divider
49  * can no longer be used, as the audio codec requests the exact clock
50  * rates we support through this mechanism. So we now hard code the
51  * variable divider to 1. This means the clock rates will no longer
52  * match the clock names.
53  */
54 #define SUN8I_A33_PLL_AUDIO_REG	0x008
55 
56 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
57 	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
59 };
60 
61 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
62 				       "osc24M", 0x008,
63 				       8, 7,	/* N */
64 				       0, 5,	/* M */
65 				       pll_audio_sdm_table, BIT(24),
66 				       0x284, BIT(31),
67 				       BIT(31),	/* gate */
68 				       BIT(28),	/* lock */
69 				       CLK_SET_RATE_UNGATE);
70 
71 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
72 					"osc24M", 0x010,
73 					8, 7,		/* N */
74 					0, 4,		/* M */
75 					BIT(24),	/* frac enable */
76 					BIT(25),	/* frac select */
77 					270000000,	/* frac rate 0 */
78 					297000000,	/* frac rate 1 */
79 					BIT(31),	/* gate */
80 					BIT(28),	/* lock */
81 					CLK_SET_RATE_UNGATE);
82 
83 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
84 					"osc24M", 0x018,
85 					8, 7,		/* N */
86 					0, 4,		/* M */
87 					BIT(24),	/* frac enable */
88 					BIT(25),	/* frac select */
89 					270000000,	/* frac rate 0 */
90 					297000000,	/* frac rate 1 */
91 					BIT(31),	/* gate */
92 					BIT(28),	/* lock */
93 					CLK_SET_RATE_UNGATE);
94 
95 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
96 				    "osc24M", 0x020,
97 				    8, 5,		/* N */
98 				    4, 2,		/* K */
99 				    0, 2,		/* M */
100 				    BIT(31),		/* gate */
101 				    BIT(28),		/* lock */
102 				    0);
103 
104 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
105 					   "osc24M", 0x028,
106 					   8, 5,	/* N */
107 					   4, 2,	/* K */
108 					   BIT(31),	/* gate */
109 					   BIT(28),	/* lock */
110 					   2,		/* post-div */
111 					   CLK_SET_RATE_UNGATE);
112 
113 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
114 					"osc24M", 0x038,
115 					8, 7,		/* N */
116 					0, 4,		/* M */
117 					BIT(24),	/* frac enable */
118 					BIT(25),	/* frac select */
119 					270000000,	/* frac rate 0 */
120 					297000000,	/* frac rate 1 */
121 					BIT(31),	/* gate */
122 					BIT(28),	/* lock */
123 					CLK_SET_RATE_UNGATE);
124 
125 /*
126  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
127  *
128  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
129  * integer / fractional clock with switchable multipliers and dividers.
130  * This is not supported here. We hardcode the PLL to MIPI mode.
131  */
132 #define SUN8I_A33_PLL_MIPI_REG	0x040
133 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
134 				    "pll-video", 0x040,
135 				    8, 4,		/* N */
136 				    4, 2,		/* K */
137 				    0, 4,		/* M */
138 				    BIT(31) | BIT(23) | BIT(22), /* gate */
139 				    BIT(28),		/* lock */
140 				    CLK_SET_RATE_UNGATE);
141 
142 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
143 					"osc24M", 0x044,
144 					8, 7,		/* N */
145 					0, 4,		/* M */
146 					BIT(24),	/* frac enable */
147 					BIT(25),	/* frac select */
148 					270000000,	/* frac rate 0 */
149 					297000000,	/* frac rate 1 */
150 					BIT(31),	/* gate */
151 					BIT(28),	/* lock */
152 					CLK_SET_RATE_UNGATE);
153 
154 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
155 					"osc24M", 0x048,
156 					8, 7,		/* N */
157 					0, 4,		/* M */
158 					BIT(24),	/* frac enable */
159 					BIT(25),	/* frac select */
160 					270000000,	/* frac rate 0 */
161 					297000000,	/* frac rate 1 */
162 					BIT(31),	/* gate */
163 					BIT(28),	/* lock */
164 					CLK_SET_RATE_UNGATE);
165 
166 static struct ccu_mult pll_ddr1_clk = {
167 	.enable	= BIT(31),
168 	.lock	= BIT(28),
169 	.mult	= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
170 	.common	= {
171 		.reg		= 0x04c,
172 		.hw.init	= CLK_HW_INIT("pll-ddr1", "osc24M",
173 					      &ccu_mult_ops,
174 					      CLK_SET_RATE_UNGATE),
175 	},
176 };
177 
178 static const char * const cpux_parents[] = { "osc32k", "osc24M",
179 					     "pll-cpux" , "pll-cpux" };
180 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
181 		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
182 
183 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
184 
185 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
186 					     "axi" , "pll-periph" };
187 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
188 	{ .index = 3, .shift = 6, .width = 2 },
189 };
190 static struct ccu_div ahb1_clk = {
191 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
192 
193 	.mux		= {
194 		.shift	= 12,
195 		.width	= 2,
196 
197 		.var_predivs	= ahb1_predivs,
198 		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
199 	},
200 
201 	.common		= {
202 		.reg		= 0x054,
203 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
204 		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
205 						      ahb1_parents,
206 						      &ccu_div_ops,
207 						      0),
208 	},
209 };
210 
211 static struct clk_div_table apb1_div_table[] = {
212 	{ .val = 0, .div = 2 },
213 	{ .val = 1, .div = 2 },
214 	{ .val = 2, .div = 4 },
215 	{ .val = 3, .div = 8 },
216 	{ /* Sentinel */ },
217 };
218 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
219 			   0x054, 8, 2, apb1_div_table, 0);
220 
221 static const char * const apb2_parents[] = { "osc32k", "osc24M",
222 					     "pll-periph" , "pll-periph" };
223 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
224 			     0, 5,	/* M */
225 			     16, 2,	/* P */
226 			     24, 2,	/* mux */
227 			     0);
228 
229 static SUNXI_CCU_GATE(bus_mipi_dsi_clk,	"bus-mipi-dsi",	"ahb1",
230 		      0x060, BIT(1), 0);
231 static SUNXI_CCU_GATE(bus_ss_clk,	"bus-ss",	"ahb1",
232 		      0x060, BIT(5), 0);
233 static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
234 		      0x060, BIT(6), 0);
235 static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
236 		      0x060, BIT(8), 0);
237 static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
238 		      0x060, BIT(9), 0);
239 static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
240 		      0x060, BIT(10), 0);
241 static SUNXI_CCU_GATE(bus_nand_clk,	"bus-nand",	"ahb1",
242 		      0x060, BIT(13), 0);
243 static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
244 		      0x060, BIT(14), 0);
245 static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
246 		      0x060, BIT(19), 0);
247 static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
248 		      0x060, BIT(20), 0);
249 static SUNXI_CCU_GATE(bus_spi1_clk,	"bus-spi1",	"ahb1",
250 		      0x060, BIT(21), 0);
251 static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
252 		      0x060, BIT(24), 0);
253 static SUNXI_CCU_GATE(bus_ehci_clk,	"bus-ehci",	"ahb1",
254 		      0x060, BIT(26), 0);
255 static SUNXI_CCU_GATE(bus_ohci_clk,	"bus-ohci",	"ahb1",
256 		      0x060, BIT(29), 0);
257 
258 static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
259 		      0x064, BIT(0), 0);
260 static SUNXI_CCU_GATE(bus_lcd_clk,	"bus-lcd",	"ahb1",
261 		      0x064, BIT(4), 0);
262 static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb1",
263 		      0x064, BIT(8), 0);
264 static SUNXI_CCU_GATE(bus_de_be_clk,	"bus-de-be",	"ahb1",
265 		      0x064, BIT(12), 0);
266 static SUNXI_CCU_GATE(bus_de_fe_clk,	"bus-de-fe",	"ahb1",
267 		      0x064, BIT(14), 0);
268 static SUNXI_CCU_GATE(bus_gpu_clk,	"bus-gpu",	"ahb1",
269 		      0x064, BIT(20), 0);
270 static SUNXI_CCU_GATE(bus_msgbox_clk,	"bus-msgbox",	"ahb1",
271 		      0x064, BIT(21), 0);
272 static SUNXI_CCU_GATE(bus_spinlock_clk,	"bus-spinlock",	"ahb1",
273 		      0x064, BIT(22), 0);
274 static SUNXI_CCU_GATE(bus_drc_clk,	"bus-drc",	"ahb1",
275 		      0x064, BIT(25), 0);
276 static SUNXI_CCU_GATE(bus_sat_clk,	"bus-sat",	"ahb1",
277 		      0x064, BIT(26), 0);
278 
279 static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
280 		      0x068, BIT(0), 0);
281 static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
282 		      0x068, BIT(5), 0);
283 static SUNXI_CCU_GATE(bus_i2s0_clk,	"bus-i2s0",	"apb1",
284 		      0x068, BIT(12), 0);
285 static SUNXI_CCU_GATE(bus_i2s1_clk,	"bus-i2s1",	"apb1",
286 		      0x068, BIT(13), 0);
287 
288 static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
289 		      0x06c, BIT(0), 0);
290 static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
291 		      0x06c, BIT(1), 0);
292 static SUNXI_CCU_GATE(bus_i2c2_clk,	"bus-i2c2",	"apb2",
293 		      0x06c, BIT(2), 0);
294 static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
295 		      0x06c, BIT(16), 0);
296 static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
297 		      0x06c, BIT(17), 0);
298 static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
299 		      0x06c, BIT(18), 0);
300 static SUNXI_CCU_GATE(bus_uart3_clk,	"bus-uart3",	"apb2",
301 		      0x06c, BIT(19), 0);
302 static SUNXI_CCU_GATE(bus_uart4_clk,	"bus-uart4",	"apb2",
303 		      0x06c, BIT(20), 0);
304 
305 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
306 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
307 				  0, 4,		/* M */
308 				  16, 2,	/* P */
309 				  24, 2,	/* mux */
310 				  BIT(31),	/* gate */
311 				  0);
312 
313 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
314 				  0, 4,		/* M */
315 				  16, 2,	/* P */
316 				  24, 2,	/* mux */
317 				  BIT(31),	/* gate */
318 				  0);
319 
320 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
321 		       0x088, 20, 3, 0);
322 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
323 		       0x088, 8, 3, 0);
324 
325 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
326 				  0, 4,		/* M */
327 				  16, 2,	/* P */
328 				  24, 2,	/* mux */
329 				  BIT(31),	/* gate */
330 				  0);
331 
332 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
333 		       0x08c, 20, 3, 0);
334 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
335 		       0x08c, 8, 3, 0);
336 
337 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
338 				  0, 4,		/* M */
339 				  16, 2,	/* P */
340 				  24, 2,	/* mux */
341 				  BIT(31),	/* gate */
342 				  0);
343 
344 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
345 		       0x090, 20, 3, 0);
346 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
347 		       0x090, 8, 3, 0);
348 
349 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
350 				  0, 4,		/* M */
351 				  16, 2,	/* P */
352 				  24, 2,	/* mux */
353 				  BIT(31),	/* gate */
354 				  0);
355 
356 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
357 				  0, 4,		/* M */
358 				  16, 2,	/* P */
359 				  24, 2,	/* mux */
360 				  BIT(31),	/* gate */
361 				  0);
362 
363 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
364 				  0, 4,		/* M */
365 				  16, 2,	/* P */
366 				  24, 2,	/* mux */
367 				  BIT(31),	/* gate */
368 				  0);
369 
370 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
371 					    "pll-audio-2x", "pll-audio" };
372 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
373 			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
374 
375 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
376 			       0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
377 
378 /* TODO: the parent for most of the USB clocks is not known */
379 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
380 		      0x0cc, BIT(8), 0);
381 static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
382 		      0x0cc, BIT(9), 0);
383 static SUNXI_CCU_GATE(usb_hsic_clk,	"usb-hsic",	"pll-hsic",
384 		      0x0cc, BIT(10), 0);
385 static SUNXI_CCU_GATE(usb_hsic_12M_clk,	"usb-hsic-12M",	"osc24M",
386 		      0x0cc, BIT(11), 0);
387 static SUNXI_CCU_GATE(usb_ohci_clk,	"usb-ohci",	"osc24M",
388 		      0x0cc, BIT(16), 0);
389 
390 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
391 		   0x0f4, 0, 4, CLK_IS_CRITICAL);
392 
393 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
394 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
395 		     0x0f8, 16, 1, 0);
396 
397 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
398 		      0x100, BIT(0), 0);
399 static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"dram",
400 		      0x100, BIT(1), 0);
401 static SUNXI_CCU_GATE(dram_drc_clk,	"dram-drc",	"dram",
402 		      0x100, BIT(16), 0);
403 static SUNXI_CCU_GATE(dram_de_fe_clk,	"dram-de-fe",	"dram",
404 		      0x100, BIT(24), 0);
405 static SUNXI_CCU_GATE(dram_de_be_clk,	"dram-de-be",	"dram",
406 		      0x100, BIT(26), 0);
407 
408 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
409 					   "pll-gpu", "pll-de" };
410 static const u8 de_table[] = { 0, 2, 3, 5 };
411 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
412 				       de_parents, de_table,
413 				       0x104, 0, 4, 24, 3, BIT(31), 0);
414 
415 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
416 				       de_parents, de_table,
417 				       0x10c, 0, 4, 24, 3, BIT(31), 0);
418 
419 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
420 						"pll-mipi" };
421 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
422 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
423 				     lcd_ch0_parents, lcd_ch0_table,
424 				     0x118, 24, 3, BIT(31),
425 				     CLK_SET_RATE_PARENT);
426 
427 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
428 static const u8 lcd_ch1_table[] = { 0, 2 };
429 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
430 				       lcd_ch1_parents, lcd_ch1_table,
431 				       0x12c, 0, 4, 24, 2, BIT(31), 0);
432 
433 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
434 						 "pll-mipi", "pll-ve" };
435 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
436 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
437 				       csi_sclk_parents, csi_sclk_table,
438 				       0x134, 16, 4, 24, 3, BIT(31), 0);
439 
440 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
441 						 "osc24M" };
442 static const u8 csi_mclk_table[] = { 0, 3, 5 };
443 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
444 				       csi_mclk_parents, csi_mclk_table,
445 				       0x134, 0, 5, 8, 3, BIT(15), 0);
446 
447 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
448 			     0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
449 
450 static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
451 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
452 static SUNXI_CCU_GATE(ac_dig_4x_clk,	"ac-dig-4x",	"pll-audio-4x",
453 		      0x140, BIT(30), CLK_SET_RATE_PARENT);
454 static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
455 		      0x144, BIT(31), 0);
456 
457 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
458 					     "pll-ddr0", "pll-ddr1" };
459 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
460 				 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
461 
462 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
463 static const u8 dsi_sclk_table[] = { 0, 2 };
464 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
465 				       dsi_sclk_parents, dsi_sclk_table,
466 				       0x168, 16, 4, 24, 2, BIT(31), 0);
467 
468 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
469 static const u8 dsi_dphy_table[] = { 0, 2 };
470 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
471 				       dsi_dphy_parents, dsi_dphy_table,
472 				       0x168, 0, 4, 8, 2, BIT(15), 0);
473 
474 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
475 				       de_parents, de_table,
476 				       0x180, 0, 4, 24, 3, BIT(31), 0);
477 
478 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
479 			     0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
480 
481 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
482 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
483 				 0x1b0, 0, 3, 24, 2, BIT(31), 0);
484 
485 static struct ccu_common *sun8i_a33_ccu_clks[] = {
486 	&pll_cpux_clk.common,
487 	&pll_audio_base_clk.common,
488 	&pll_video_clk.common,
489 	&pll_ve_clk.common,
490 	&pll_ddr0_clk.common,
491 	&pll_periph_clk.common,
492 	&pll_gpu_clk.common,
493 	&pll_mipi_clk.common,
494 	&pll_hsic_clk.common,
495 	&pll_de_clk.common,
496 	&pll_ddr1_clk.common,
497 	&pll_ddr_clk.common,
498 	&cpux_clk.common,
499 	&axi_clk.common,
500 	&ahb1_clk.common,
501 	&apb1_clk.common,
502 	&apb2_clk.common,
503 	&bus_mipi_dsi_clk.common,
504 	&bus_ss_clk.common,
505 	&bus_dma_clk.common,
506 	&bus_mmc0_clk.common,
507 	&bus_mmc1_clk.common,
508 	&bus_mmc2_clk.common,
509 	&bus_nand_clk.common,
510 	&bus_dram_clk.common,
511 	&bus_hstimer_clk.common,
512 	&bus_spi0_clk.common,
513 	&bus_spi1_clk.common,
514 	&bus_otg_clk.common,
515 	&bus_ehci_clk.common,
516 	&bus_ohci_clk.common,
517 	&bus_ve_clk.common,
518 	&bus_lcd_clk.common,
519 	&bus_csi_clk.common,
520 	&bus_de_fe_clk.common,
521 	&bus_de_be_clk.common,
522 	&bus_gpu_clk.common,
523 	&bus_msgbox_clk.common,
524 	&bus_spinlock_clk.common,
525 	&bus_drc_clk.common,
526 	&bus_sat_clk.common,
527 	&bus_codec_clk.common,
528 	&bus_pio_clk.common,
529 	&bus_i2s0_clk.common,
530 	&bus_i2s1_clk.common,
531 	&bus_i2c0_clk.common,
532 	&bus_i2c1_clk.common,
533 	&bus_i2c2_clk.common,
534 	&bus_uart0_clk.common,
535 	&bus_uart1_clk.common,
536 	&bus_uart2_clk.common,
537 	&bus_uart3_clk.common,
538 	&bus_uart4_clk.common,
539 	&nand_clk.common,
540 	&mmc0_clk.common,
541 	&mmc0_sample_clk.common,
542 	&mmc0_output_clk.common,
543 	&mmc1_clk.common,
544 	&mmc1_sample_clk.common,
545 	&mmc1_output_clk.common,
546 	&mmc2_clk.common,
547 	&mmc2_sample_clk.common,
548 	&mmc2_output_clk.common,
549 	&ss_clk.common,
550 	&spi0_clk.common,
551 	&spi1_clk.common,
552 	&i2s0_clk.common,
553 	&i2s1_clk.common,
554 	&usb_phy0_clk.common,
555 	&usb_phy1_clk.common,
556 	&usb_hsic_clk.common,
557 	&usb_hsic_12M_clk.common,
558 	&usb_ohci_clk.common,
559 	&dram_clk.common,
560 	&dram_ve_clk.common,
561 	&dram_csi_clk.common,
562 	&dram_drc_clk.common,
563 	&dram_de_fe_clk.common,
564 	&dram_de_be_clk.common,
565 	&de_be_clk.common,
566 	&de_fe_clk.common,
567 	&lcd_ch0_clk.common,
568 	&lcd_ch1_clk.common,
569 	&csi_sclk_clk.common,
570 	&csi_mclk_clk.common,
571 	&ve_clk.common,
572 	&ac_dig_clk.common,
573 	&ac_dig_4x_clk.common,
574 	&avs_clk.common,
575 	&mbus_clk.common,
576 	&dsi_sclk_clk.common,
577 	&dsi_dphy_clk.common,
578 	&drc_clk.common,
579 	&gpu_clk.common,
580 	&ats_clk.common,
581 };
582 
583 static const struct clk_hw *clk_parent_pll_audio[] = {
584 	&pll_audio_base_clk.common.hw
585 };
586 
587 /* We hardcode the divider to 1 for now */
588 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
589 			    clk_parent_pll_audio,
590 			    1, 1, CLK_SET_RATE_PARENT);
591 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
592 			    clk_parent_pll_audio,
593 			    2, 1, CLK_SET_RATE_PARENT);
594 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
595 			    clk_parent_pll_audio,
596 			    1, 1, CLK_SET_RATE_PARENT);
597 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
598 			    clk_parent_pll_audio,
599 			    1, 2, CLK_SET_RATE_PARENT);
600 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
601 			   &pll_periph_clk.common.hw,
602 			   1, 2, 0);
603 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
604 			   &pll_video_clk.common.hw,
605 			   1, 2, 0);
606 
607 static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
608 	.hws	= {
609 		[CLK_PLL_CPUX]		= &pll_cpux_clk.common.hw,
610 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
611 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
612 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
613 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
614 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
615 		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
616 		[CLK_PLL_VIDEO_2X]	= &pll_video_2x_clk.hw,
617 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
618 		[CLK_PLL_DDR0]		= &pll_ddr0_clk.common.hw,
619 		[CLK_PLL_PERIPH]	= &pll_periph_clk.common.hw,
620 		[CLK_PLL_PERIPH_2X]	= &pll_periph_2x_clk.hw,
621 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
622 		[CLK_PLL_MIPI]		= &pll_mipi_clk.common.hw,
623 		[CLK_PLL_HSIC]		= &pll_hsic_clk.common.hw,
624 		[CLK_PLL_DE]		= &pll_de_clk.common.hw,
625 		[CLK_PLL_DDR1]		= &pll_ddr1_clk.common.hw,
626 		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
627 		[CLK_CPUX]		= &cpux_clk.common.hw,
628 		[CLK_AXI]		= &axi_clk.common.hw,
629 		[CLK_AHB1]		= &ahb1_clk.common.hw,
630 		[CLK_APB1]		= &apb1_clk.common.hw,
631 		[CLK_APB2]		= &apb2_clk.common.hw,
632 		[CLK_BUS_MIPI_DSI]	= &bus_mipi_dsi_clk.common.hw,
633 		[CLK_BUS_SS]		= &bus_ss_clk.common.hw,
634 		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
635 		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
636 		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
637 		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
638 		[CLK_BUS_NAND]		= &bus_nand_clk.common.hw,
639 		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
640 		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
641 		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
642 		[CLK_BUS_SPI1]		= &bus_spi1_clk.common.hw,
643 		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
644 		[CLK_BUS_EHCI]		= &bus_ehci_clk.common.hw,
645 		[CLK_BUS_OHCI]		= &bus_ohci_clk.common.hw,
646 		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
647 		[CLK_BUS_LCD]		= &bus_lcd_clk.common.hw,
648 		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
649 		[CLK_BUS_DE_BE]		= &bus_de_be_clk.common.hw,
650 		[CLK_BUS_DE_FE]		= &bus_de_fe_clk.common.hw,
651 		[CLK_BUS_GPU]		= &bus_gpu_clk.common.hw,
652 		[CLK_BUS_MSGBOX]	= &bus_msgbox_clk.common.hw,
653 		[CLK_BUS_SPINLOCK]	= &bus_spinlock_clk.common.hw,
654 		[CLK_BUS_DRC]		= &bus_drc_clk.common.hw,
655 		[CLK_BUS_SAT]		= &bus_sat_clk.common.hw,
656 		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
657 		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
658 		[CLK_BUS_I2S0]		= &bus_i2s0_clk.common.hw,
659 		[CLK_BUS_I2S1]		= &bus_i2s1_clk.common.hw,
660 		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
661 		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
662 		[CLK_BUS_I2C2]		= &bus_i2c2_clk.common.hw,
663 		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
664 		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
665 		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
666 		[CLK_BUS_UART3]		= &bus_uart3_clk.common.hw,
667 		[CLK_BUS_UART4]		= &bus_uart4_clk.common.hw,
668 		[CLK_NAND]		= &nand_clk.common.hw,
669 		[CLK_MMC0]		= &mmc0_clk.common.hw,
670 		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
671 		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
672 		[CLK_MMC1]		= &mmc1_clk.common.hw,
673 		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
674 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
675 		[CLK_MMC2]		= &mmc2_clk.common.hw,
676 		[CLK_MMC2_SAMPLE]	= &mmc2_sample_clk.common.hw,
677 		[CLK_MMC2_OUTPUT]	= &mmc2_output_clk.common.hw,
678 		[CLK_SS]		= &ss_clk.common.hw,
679 		[CLK_SPI0]		= &spi0_clk.common.hw,
680 		[CLK_SPI1]		= &spi1_clk.common.hw,
681 		[CLK_I2S0]		= &i2s0_clk.common.hw,
682 		[CLK_I2S1]		= &i2s1_clk.common.hw,
683 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
684 		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
685 		[CLK_USB_HSIC]		= &usb_hsic_clk.common.hw,
686 		[CLK_USB_HSIC_12M]	= &usb_hsic_12M_clk.common.hw,
687 		[CLK_USB_OHCI]		= &usb_ohci_clk.common.hw,
688 		[CLK_DRAM]		= &dram_clk.common.hw,
689 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
690 		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
691 		[CLK_DRAM_DRC]		= &dram_drc_clk.common.hw,
692 		[CLK_DRAM_DE_FE]	= &dram_de_fe_clk.common.hw,
693 		[CLK_DRAM_DE_BE]	= &dram_de_be_clk.common.hw,
694 		[CLK_DE_BE]		= &de_be_clk.common.hw,
695 		[CLK_DE_FE]		= &de_fe_clk.common.hw,
696 		[CLK_LCD_CH0]		= &lcd_ch0_clk.common.hw,
697 		[CLK_LCD_CH1]		= &lcd_ch1_clk.common.hw,
698 		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
699 		[CLK_CSI_MCLK]		= &csi_mclk_clk.common.hw,
700 		[CLK_VE]		= &ve_clk.common.hw,
701 		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
702 		[CLK_AC_DIG_4X]		= &ac_dig_4x_clk.common.hw,
703 		[CLK_AVS]		= &avs_clk.common.hw,
704 		[CLK_MBUS]		= &mbus_clk.common.hw,
705 		[CLK_DSI_SCLK]		= &dsi_sclk_clk.common.hw,
706 		[CLK_DSI_DPHY]		= &dsi_dphy_clk.common.hw,
707 		[CLK_DRC]		= &drc_clk.common.hw,
708 		[CLK_GPU]		= &gpu_clk.common.hw,
709 		[CLK_ATS]		= &ats_clk.common.hw,
710 	},
711 	.num	= CLK_NUMBER,
712 };
713 
714 static struct ccu_reset_map sun8i_a33_ccu_resets[] = {
715 	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
716 	[RST_USB_PHY1]		=  { 0x0cc, BIT(1) },
717 	[RST_USB_HSIC]		=  { 0x0cc, BIT(2) },
718 
719 	[RST_MBUS]		=  { 0x0fc, BIT(31) },
720 
721 	[RST_BUS_MIPI_DSI]	=  { 0x2c0, BIT(1) },
722 	[RST_BUS_SS]		=  { 0x2c0, BIT(5) },
723 	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
724 	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
725 	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
726 	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
727 	[RST_BUS_NAND]		=  { 0x2c0, BIT(13) },
728 	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
729 	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
730 	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
731 	[RST_BUS_SPI1]		=  { 0x2c0, BIT(21) },
732 	[RST_BUS_OTG]		=  { 0x2c0, BIT(24) },
733 	[RST_BUS_EHCI]		=  { 0x2c0, BIT(26) },
734 	[RST_BUS_OHCI]		=  { 0x2c0, BIT(29) },
735 
736 	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
737 	[RST_BUS_LCD]		=  { 0x2c4, BIT(4) },
738 	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
739 	[RST_BUS_DE_BE]		=  { 0x2c4, BIT(12) },
740 	[RST_BUS_DE_FE]		=  { 0x2c4, BIT(14) },
741 	[RST_BUS_GPU]		=  { 0x2c4, BIT(20) },
742 	[RST_BUS_MSGBOX]	=  { 0x2c4, BIT(21) },
743 	[RST_BUS_SPINLOCK]	=  { 0x2c4, BIT(22) },
744 	[RST_BUS_DRC]		=  { 0x2c4, BIT(25) },
745 	[RST_BUS_SAT]		=  { 0x2c4, BIT(26) },
746 
747 	[RST_BUS_LVDS]		=  { 0x2c8, BIT(0) },
748 
749 	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
750 	[RST_BUS_I2S0]		=  { 0x2d0, BIT(12) },
751 	[RST_BUS_I2S1]		=  { 0x2d0, BIT(13) },
752 
753 	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
754 	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
755 	[RST_BUS_I2C2]		=  { 0x2d8, BIT(2) },
756 	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
757 	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
758 	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
759 	[RST_BUS_UART3]		=  { 0x2d8, BIT(19) },
760 	[RST_BUS_UART4]		=  { 0x2d8, BIT(20) },
761 };
762 
763 static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
764 	.ccu_clks	= sun8i_a33_ccu_clks,
765 	.num_ccu_clks	= ARRAY_SIZE(sun8i_a33_ccu_clks),
766 
767 	.hw_clks	= &sun8i_a33_hw_clks,
768 
769 	.resets		= sun8i_a33_ccu_resets,
770 	.num_resets	= ARRAY_SIZE(sun8i_a33_ccu_resets),
771 };
772 
773 static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
774 	.common	= &pll_cpux_clk.common,
775 	/* copy from pll_cpux_clk */
776 	.enable	= BIT(31),
777 	.lock	= BIT(28),
778 };
779 
780 static struct ccu_mux_nb sun8i_a33_cpu_nb = {
781 	.common		= &cpux_clk.common,
782 	.cm		= &cpux_clk.mux,
783 	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
784 	.bypass_index	= 1, /* index of 24 MHz oscillator */
785 };
786 
787 static void __init sun8i_a33_ccu_setup(struct device_node *node)
788 {
789 	void __iomem *reg;
790 	u32 val;
791 
792 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
793 	if (IS_ERR(reg)) {
794 		pr_err("%pOF: Could not map the clock registers\n", node);
795 		return;
796 	}
797 
798 	/* Force the PLL-Audio-1x divider to 1 */
799 	val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
800 	val &= ~GENMASK(19, 16);
801 	writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
802 
803 	/* Force PLL-MIPI to MIPI mode */
804 	val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
805 	val &= ~BIT(16);
806 	writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
807 
808 	sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc);
809 
810 	/* Gate then ungate PLL CPU after any rate changes */
811 	ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
812 
813 	/* Reparent CPU during PLL CPU rate changes */
814 	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
815 				  &sun8i_a33_cpu_nb);
816 }
817 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu",
818 	       sun8i_a33_ccu_setup);
819