1 /* 2 * Copyright (c) 2016 Maxime Ripard. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/of_address.h> 16 17 #include "ccu_common.h" 18 #include "ccu_reset.h" 19 20 #include "ccu_div.h" 21 #include "ccu_gate.h" 22 #include "ccu_mp.h" 23 #include "ccu_mult.h" 24 #include "ccu_nk.h" 25 #include "ccu_nkm.h" 26 #include "ccu_nkmp.h" 27 #include "ccu_nm.h" 28 #include "ccu_phase.h" 29 30 #include "ccu-sun8i-a23-a33.h" 31 32 static struct ccu_nkmp pll_cpux_clk = { 33 .enable = BIT(31), 34 .lock = BIT(28), 35 36 .n = _SUNXI_CCU_MULT(8, 5), 37 .k = _SUNXI_CCU_MULT(4, 2), 38 .m = _SUNXI_CCU_DIV(0, 2), 39 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 40 41 .common = { 42 .reg = 0x000, 43 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", 44 &ccu_nkmp_ops, 45 0), 46 }, 47 }; 48 49 /* 50 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 51 * the base (2x, 4x and 8x), and one variable divider (the one true 52 * pll audio). 53 * 54 * We don't have any need for the variable divider for now, so we just 55 * hardcode it to match with the clock names 56 */ 57 #define SUN8I_A33_PLL_AUDIO_REG 0x008 58 59 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 60 "osc24M", 0x008, 61 8, 7, /* N */ 62 0, 5, /* M */ 63 BIT(31), /* gate */ 64 BIT(28), /* lock */ 65 CLK_SET_RATE_UNGATE); 66 67 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 68 "osc24M", 0x010, 69 8, 7, /* N */ 70 0, 4, /* M */ 71 BIT(24), /* frac enable */ 72 BIT(25), /* frac select */ 73 270000000, /* frac rate 0 */ 74 297000000, /* frac rate 1 */ 75 BIT(31), /* gate */ 76 BIT(28), /* lock */ 77 CLK_SET_RATE_UNGATE); 78 79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 80 "osc24M", 0x018, 81 8, 7, /* N */ 82 0, 4, /* M */ 83 BIT(24), /* frac enable */ 84 BIT(25), /* frac select */ 85 270000000, /* frac rate 0 */ 86 297000000, /* frac rate 1 */ 87 BIT(31), /* gate */ 88 BIT(28), /* lock */ 89 CLK_SET_RATE_UNGATE); 90 91 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 92 "osc24M", 0x020, 93 8, 5, /* N */ 94 4, 2, /* K */ 95 0, 2, /* M */ 96 BIT(31), /* gate */ 97 BIT(28), /* lock */ 98 0); 99 100 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", 101 "osc24M", 0x028, 102 8, 5, /* N */ 103 4, 2, /* K */ 104 BIT(31), /* gate */ 105 BIT(28), /* lock */ 106 2, /* post-div */ 107 CLK_SET_RATE_UNGATE); 108 109 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 110 "osc24M", 0x038, 111 8, 7, /* N */ 112 0, 4, /* M */ 113 BIT(24), /* frac enable */ 114 BIT(25), /* frac select */ 115 270000000, /* frac rate 0 */ 116 297000000, /* frac rate 1 */ 117 BIT(31), /* gate */ 118 BIT(28), /* lock */ 119 CLK_SET_RATE_UNGATE); 120 121 /* 122 * The MIPI PLL has 2 modes: "MIPI" and "HDMI". 123 * 124 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an 125 * integer / fractional clock with switchable multipliers and dividers. 126 * This is not supported here. We hardcode the PLL to MIPI mode. 127 */ 128 #define SUN8I_A33_PLL_MIPI_REG 0x040 129 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", 130 "pll-video", 0x040, 131 8, 4, /* N */ 132 4, 2, /* K */ 133 0, 4, /* M */ 134 BIT(31) | BIT(23) | BIT(22), /* gate */ 135 BIT(28), /* lock */ 136 CLK_SET_RATE_UNGATE); 137 138 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", 139 "osc24M", 0x044, 140 8, 7, /* N */ 141 0, 4, /* M */ 142 BIT(24), /* frac enable */ 143 BIT(25), /* frac select */ 144 270000000, /* frac rate 0 */ 145 297000000, /* frac rate 1 */ 146 BIT(31), /* gate */ 147 BIT(28), /* lock */ 148 CLK_SET_RATE_UNGATE); 149 150 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 151 "osc24M", 0x048, 152 8, 7, /* N */ 153 0, 4, /* M */ 154 BIT(24), /* frac enable */ 155 BIT(25), /* frac select */ 156 270000000, /* frac rate 0 */ 157 297000000, /* frac rate 1 */ 158 BIT(31), /* gate */ 159 BIT(28), /* lock */ 160 CLK_SET_RATE_UNGATE); 161 162 static struct ccu_mult pll_ddr1_clk = { 163 .enable = BIT(31), 164 .lock = BIT(28), 165 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0), 166 .common = { 167 .reg = 0x04c, 168 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M", 169 &ccu_mult_ops, 170 CLK_SET_RATE_UNGATE), 171 }, 172 }; 173 174 static const char * const cpux_parents[] = { "osc32k", "osc24M", 175 "pll-cpux" , "pll-cpux" }; 176 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 177 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); 178 179 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); 180 181 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 182 "axi" , "pll-periph" }; 183 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 184 { .index = 3, .shift = 6, .width = 2 }, 185 }; 186 static struct ccu_div ahb1_clk = { 187 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 188 189 .mux = { 190 .shift = 12, 191 .width = 2, 192 193 .var_predivs = ahb1_predivs, 194 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 195 }, 196 197 .common = { 198 .reg = 0x054, 199 .features = CCU_FEATURE_VARIABLE_PREDIV, 200 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 201 ahb1_parents, 202 &ccu_div_ops, 203 0), 204 }, 205 }; 206 207 static struct clk_div_table apb1_div_table[] = { 208 { .val = 0, .div = 2 }, 209 { .val = 1, .div = 2 }, 210 { .val = 2, .div = 4 }, 211 { .val = 3, .div = 8 }, 212 { /* Sentinel */ }, 213 }; 214 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 215 0x054, 8, 2, apb1_div_table, 0); 216 217 static const char * const apb2_parents[] = { "osc32k", "osc24M", 218 "pll-periph" , "pll-periph" }; 219 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 220 0, 5, /* M */ 221 16, 2, /* P */ 222 24, 2, /* mux */ 223 0); 224 225 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 226 0x060, BIT(1), 0); 227 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1", 228 0x060, BIT(5), 0); 229 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 230 0x060, BIT(6), 0); 231 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 232 0x060, BIT(8), 0); 233 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 234 0x060, BIT(9), 0); 235 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 236 0x060, BIT(10), 0); 237 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 238 0x060, BIT(13), 0); 239 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 240 0x060, BIT(14), 0); 241 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 242 0x060, BIT(19), 0); 243 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 244 0x060, BIT(20), 0); 245 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 246 0x060, BIT(21), 0); 247 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 248 0x060, BIT(24), 0); 249 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1", 250 0x060, BIT(26), 0); 251 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1", 252 0x060, BIT(29), 0); 253 254 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 255 0x064, BIT(0), 0); 256 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1", 257 0x064, BIT(4), 0); 258 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 259 0x064, BIT(8), 0); 260 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1", 261 0x064, BIT(12), 0); 262 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1", 263 0x064, BIT(14), 0); 264 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 265 0x064, BIT(20), 0); 266 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 267 0x064, BIT(21), 0); 268 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 269 0x064, BIT(22), 0); 270 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1", 271 0x064, BIT(25), 0); 272 static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1", 273 0x064, BIT(26), 0); 274 275 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 276 0x068, BIT(0), 0); 277 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 278 0x068, BIT(5), 0); 279 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 280 0x068, BIT(12), 0); 281 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 282 0x068, BIT(13), 0); 283 284 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 285 0x06c, BIT(0), 0); 286 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 287 0x06c, BIT(1), 0); 288 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 289 0x06c, BIT(2), 0); 290 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 291 0x06c, BIT(16), 0); 292 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 293 0x06c, BIT(17), 0); 294 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 295 0x06c, BIT(18), 0); 296 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 297 0x06c, BIT(19), 0); 298 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 299 0x06c, BIT(20), 0); 300 301 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; 302 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 303 0, 4, /* M */ 304 16, 2, /* P */ 305 24, 2, /* mux */ 306 BIT(31), /* gate */ 307 0); 308 309 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 310 0, 4, /* M */ 311 16, 2, /* P */ 312 24, 2, /* mux */ 313 BIT(31), /* gate */ 314 0); 315 316 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 317 0x088, 20, 3, 0); 318 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 319 0x088, 8, 3, 0); 320 321 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 322 0, 4, /* M */ 323 16, 2, /* P */ 324 24, 2, /* mux */ 325 BIT(31), /* gate */ 326 0); 327 328 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 329 0x08c, 20, 3, 0); 330 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 331 0x08c, 8, 3, 0); 332 333 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 334 0, 4, /* M */ 335 16, 2, /* P */ 336 24, 2, /* mux */ 337 BIT(31), /* gate */ 338 0); 339 340 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", 341 0x090, 20, 3, 0); 342 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", 343 0x090, 8, 3, 0); 344 345 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c, 346 0, 4, /* M */ 347 16, 2, /* P */ 348 24, 2, /* mux */ 349 BIT(31), /* gate */ 350 0); 351 352 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 353 0, 4, /* M */ 354 16, 2, /* P */ 355 24, 2, /* mux */ 356 BIT(31), /* gate */ 357 0); 358 359 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 360 0, 4, /* M */ 361 16, 2, /* P */ 362 24, 2, /* mux */ 363 BIT(31), /* gate */ 364 0); 365 366 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 367 "pll-audio-2x", "pll-audio" }; 368 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 369 0x0b0, 16, 2, BIT(31), 0); 370 371 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 372 0x0b4, 16, 2, BIT(31), 0); 373 374 /* TODO: the parent for most of the USB clocks is not known */ 375 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 376 0x0cc, BIT(8), 0); 377 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 378 0x0cc, BIT(9), 0); 379 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 380 0x0cc, BIT(10), 0); 381 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M", 382 0x0cc, BIT(11), 0); 383 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M", 384 0x0cc, BIT(16), 0); 385 386 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 387 0x0f4, 0, 4, CLK_IS_CRITICAL); 388 389 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" }; 390 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents, 391 0x0f8, 16, 1, 0); 392 393 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 394 0x100, BIT(0), 0); 395 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 396 0x100, BIT(1), 0); 397 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram", 398 0x100, BIT(16), 0); 399 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram", 400 0x100, BIT(24), 0); 401 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram", 402 0x100, BIT(26), 0); 403 404 static const char * const de_parents[] = { "pll-video", "pll-periph-2x", 405 "pll-gpu", "pll-de" }; 406 static const u8 de_table[] = { 0, 2, 3, 5 }; 407 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", 408 de_parents, de_table, 409 0x104, 0, 4, 24, 3, BIT(31), 0); 410 411 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", 412 de_parents, de_table, 413 0x10c, 0, 4, 24, 3, BIT(31), 0); 414 415 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x", 416 "pll-mipi" }; 417 static const u8 lcd_ch0_table[] = { 0, 2, 4 }; 418 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0", 419 lcd_ch0_parents, lcd_ch0_table, 420 0x118, 24, 3, BIT(31), 421 CLK_SET_RATE_PARENT); 422 423 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" }; 424 static const u8 lcd_ch1_table[] = { 0, 2 }; 425 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1", 426 lcd_ch1_parents, lcd_ch1_table, 427 0x12c, 0, 4, 24, 2, BIT(31), 0); 428 429 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de", 430 "pll-mipi", "pll-ve" }; 431 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 }; 432 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk", 433 csi_sclk_parents, csi_sclk_table, 434 0x134, 16, 4, 24, 3, BIT(31), 0); 435 436 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de", 437 "osc24M" }; 438 static const u8 csi_mclk_table[] = { 0, 3, 5 }; 439 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk", 440 csi_mclk_parents, csi_mclk_table, 441 0x134, 0, 5, 8, 3, BIT(15), 0); 442 443 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 444 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); 445 446 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 447 0x140, BIT(31), CLK_SET_RATE_PARENT); 448 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 449 0x140, BIT(30), 0); 450 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 451 0x144, BIT(31), 0); 452 453 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x", 454 "pll-ddr0", "pll-ddr1" }; 455 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 456 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 457 458 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" }; 459 static const u8 dsi_sclk_table[] = { 0, 2 }; 460 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk", 461 dsi_sclk_parents, dsi_sclk_table, 462 0x168, 16, 4, 24, 2, BIT(31), 0); 463 464 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" }; 465 static const u8 dsi_dphy_table[] = { 0, 2 }; 466 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", 467 dsi_dphy_parents, dsi_dphy_table, 468 0x168, 0, 4, 8, 2, BIT(15), 0); 469 470 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc", 471 de_parents, de_table, 472 0x180, 0, 4, 24, 3, BIT(31), 0); 473 474 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 475 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 476 477 static const char * const ats_parents[] = { "osc24M", "pll-periph" }; 478 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents, 479 0x1b0, 0, 3, 24, 2, BIT(31), 0); 480 481 static struct ccu_common *sun8i_a33_ccu_clks[] = { 482 &pll_cpux_clk.common, 483 &pll_audio_base_clk.common, 484 &pll_video_clk.common, 485 &pll_ve_clk.common, 486 &pll_ddr0_clk.common, 487 &pll_periph_clk.common, 488 &pll_gpu_clk.common, 489 &pll_mipi_clk.common, 490 &pll_hsic_clk.common, 491 &pll_de_clk.common, 492 &pll_ddr1_clk.common, 493 &pll_ddr_clk.common, 494 &cpux_clk.common, 495 &axi_clk.common, 496 &ahb1_clk.common, 497 &apb1_clk.common, 498 &apb2_clk.common, 499 &bus_mipi_dsi_clk.common, 500 &bus_ss_clk.common, 501 &bus_dma_clk.common, 502 &bus_mmc0_clk.common, 503 &bus_mmc1_clk.common, 504 &bus_mmc2_clk.common, 505 &bus_nand_clk.common, 506 &bus_dram_clk.common, 507 &bus_hstimer_clk.common, 508 &bus_spi0_clk.common, 509 &bus_spi1_clk.common, 510 &bus_otg_clk.common, 511 &bus_ehci_clk.common, 512 &bus_ohci_clk.common, 513 &bus_ve_clk.common, 514 &bus_lcd_clk.common, 515 &bus_csi_clk.common, 516 &bus_de_fe_clk.common, 517 &bus_de_be_clk.common, 518 &bus_gpu_clk.common, 519 &bus_msgbox_clk.common, 520 &bus_spinlock_clk.common, 521 &bus_drc_clk.common, 522 &bus_sat_clk.common, 523 &bus_codec_clk.common, 524 &bus_pio_clk.common, 525 &bus_i2s0_clk.common, 526 &bus_i2s1_clk.common, 527 &bus_i2c0_clk.common, 528 &bus_i2c1_clk.common, 529 &bus_i2c2_clk.common, 530 &bus_uart0_clk.common, 531 &bus_uart1_clk.common, 532 &bus_uart2_clk.common, 533 &bus_uart3_clk.common, 534 &bus_uart4_clk.common, 535 &nand_clk.common, 536 &mmc0_clk.common, 537 &mmc0_sample_clk.common, 538 &mmc0_output_clk.common, 539 &mmc1_clk.common, 540 &mmc1_sample_clk.common, 541 &mmc1_output_clk.common, 542 &mmc2_clk.common, 543 &mmc2_sample_clk.common, 544 &mmc2_output_clk.common, 545 &ss_clk.common, 546 &spi0_clk.common, 547 &spi1_clk.common, 548 &i2s0_clk.common, 549 &i2s1_clk.common, 550 &usb_phy0_clk.common, 551 &usb_phy1_clk.common, 552 &usb_hsic_clk.common, 553 &usb_hsic_12M_clk.common, 554 &usb_ohci_clk.common, 555 &dram_clk.common, 556 &dram_ve_clk.common, 557 &dram_csi_clk.common, 558 &dram_drc_clk.common, 559 &dram_de_fe_clk.common, 560 &dram_de_be_clk.common, 561 &de_be_clk.common, 562 &de_fe_clk.common, 563 &lcd_ch0_clk.common, 564 &lcd_ch1_clk.common, 565 &csi_sclk_clk.common, 566 &csi_mclk_clk.common, 567 &ve_clk.common, 568 &ac_dig_clk.common, 569 &ac_dig_4x_clk.common, 570 &avs_clk.common, 571 &mbus_clk.common, 572 &dsi_sclk_clk.common, 573 &dsi_dphy_clk.common, 574 &drc_clk.common, 575 &gpu_clk.common, 576 &ats_clk.common, 577 }; 578 579 /* We hardcode the divider to 4 for now */ 580 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 581 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 582 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 583 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 584 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 585 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 586 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 587 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 588 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", 589 "pll-periph", 1, 2, 0); 590 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", 591 "pll-video", 1, 2, 0); 592 593 static struct clk_hw_onecell_data sun8i_a33_hw_clks = { 594 .hws = { 595 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 596 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 597 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 598 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 599 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 600 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 601 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 602 [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, 603 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 604 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 605 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, 606 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw, 607 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 608 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 609 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 610 [CLK_PLL_DE] = &pll_de_clk.common.hw, 611 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 612 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, 613 [CLK_CPUX] = &cpux_clk.common.hw, 614 [CLK_AXI] = &axi_clk.common.hw, 615 [CLK_AHB1] = &ahb1_clk.common.hw, 616 [CLK_APB1] = &apb1_clk.common.hw, 617 [CLK_APB2] = &apb2_clk.common.hw, 618 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 619 [CLK_BUS_SS] = &bus_ss_clk.common.hw, 620 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 621 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 622 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 623 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 624 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 625 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 626 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 627 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 628 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 629 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 630 [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw, 631 [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw, 632 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 633 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, 634 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 635 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, 636 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, 637 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 638 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 639 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 640 [CLK_BUS_DRC] = &bus_drc_clk.common.hw, 641 [CLK_BUS_SAT] = &bus_sat_clk.common.hw, 642 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 643 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 644 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 645 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 646 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 647 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 648 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 649 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 650 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 651 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 652 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 653 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 654 [CLK_NAND] = &nand_clk.common.hw, 655 [CLK_MMC0] = &mmc0_clk.common.hw, 656 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 657 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 658 [CLK_MMC1] = &mmc1_clk.common.hw, 659 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 660 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 661 [CLK_MMC2] = &mmc2_clk.common.hw, 662 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 663 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 664 [CLK_SS] = &ss_clk.common.hw, 665 [CLK_SPI0] = &spi0_clk.common.hw, 666 [CLK_SPI1] = &spi1_clk.common.hw, 667 [CLK_I2S0] = &i2s0_clk.common.hw, 668 [CLK_I2S1] = &i2s1_clk.common.hw, 669 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 670 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 671 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 672 [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw, 673 [CLK_USB_OHCI] = &usb_ohci_clk.common.hw, 674 [CLK_DRAM] = &dram_clk.common.hw, 675 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 676 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 677 [CLK_DRAM_DRC] = &dram_drc_clk.common.hw, 678 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, 679 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, 680 [CLK_DE_BE] = &de_be_clk.common.hw, 681 [CLK_DE_FE] = &de_fe_clk.common.hw, 682 [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw, 683 [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw, 684 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 685 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 686 [CLK_VE] = &ve_clk.common.hw, 687 [CLK_AC_DIG] = &ac_dig_clk.common.hw, 688 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, 689 [CLK_AVS] = &avs_clk.common.hw, 690 [CLK_MBUS] = &mbus_clk.common.hw, 691 [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw, 692 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, 693 [CLK_DRC] = &drc_clk.common.hw, 694 [CLK_GPU] = &gpu_clk.common.hw, 695 [CLK_ATS] = &ats_clk.common.hw, 696 }, 697 .num = CLK_NUMBER, 698 }; 699 700 static struct ccu_reset_map sun8i_a33_ccu_resets[] = { 701 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 702 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 703 [RST_USB_HSIC] = { 0x0cc, BIT(2) }, 704 705 [RST_MBUS] = { 0x0fc, BIT(31) }, 706 707 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 708 [RST_BUS_SS] = { 0x2c0, BIT(5) }, 709 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 710 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 711 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 712 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 713 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 714 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 715 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 716 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 717 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 718 [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 719 [RST_BUS_EHCI] = { 0x2c0, BIT(26) }, 720 [RST_BUS_OHCI] = { 0x2c0, BIT(29) }, 721 722 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 723 [RST_BUS_LCD] = { 0x2c4, BIT(4) }, 724 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 725 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, 726 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, 727 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 728 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, 729 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, 730 [RST_BUS_DRC] = { 0x2c4, BIT(25) }, 731 [RST_BUS_SAT] = { 0x2c4, BIT(26) }, 732 733 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 734 735 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 736 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 737 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 738 739 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 740 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 741 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 742 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 743 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 744 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 745 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 746 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 747 }; 748 749 static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = { 750 .ccu_clks = sun8i_a33_ccu_clks, 751 .num_ccu_clks = ARRAY_SIZE(sun8i_a33_ccu_clks), 752 753 .hw_clks = &sun8i_a33_hw_clks, 754 755 .resets = sun8i_a33_ccu_resets, 756 .num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets), 757 }; 758 759 static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = { 760 .common = &pll_cpux_clk.common, 761 /* copy from pll_cpux_clk */ 762 .enable = BIT(31), 763 .lock = BIT(28), 764 }; 765 766 static struct ccu_mux_nb sun8i_a33_cpu_nb = { 767 .common = &cpux_clk.common, 768 .cm = &cpux_clk.mux, 769 .delay_us = 1, /* > 8 clock cycles at 24 MHz */ 770 .bypass_index = 1, /* index of 24 MHz oscillator */ 771 }; 772 773 static void __init sun8i_a33_ccu_setup(struct device_node *node) 774 { 775 void __iomem *reg; 776 u32 val; 777 778 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 779 if (IS_ERR(reg)) { 780 pr_err("%pOF: Could not map the clock registers\n", node); 781 return; 782 } 783 784 /* Force the PLL-Audio-1x divider to 4 */ 785 val = readl(reg + SUN8I_A33_PLL_AUDIO_REG); 786 val &= ~GENMASK(19, 16); 787 writel(val | (3 << 16), reg + SUN8I_A33_PLL_AUDIO_REG); 788 789 /* Force PLL-MIPI to MIPI mode */ 790 val = readl(reg + SUN8I_A33_PLL_MIPI_REG); 791 val &= ~BIT(16); 792 writel(val, reg + SUN8I_A33_PLL_MIPI_REG); 793 794 sunxi_ccu_probe(node, reg, &sun8i_a33_ccu_desc); 795 796 /* Gate then ungate PLL CPU after any rate changes */ 797 ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb); 798 799 /* Reparent CPU during PLL CPU rate changes */ 800 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk, 801 &sun8i_a33_cpu_nb); 802 } 803 CLK_OF_DECLARE(sun8i_a33_ccu, "allwinner,sun8i-a33-ccu", 804 sun8i_a33_ccu_setup); 805