1 /* 2 * Copyright (c) 2016 Maxime Ripard. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/io.h> 16 #include <linux/of_address.h> 17 18 #include "ccu_common.h" 19 #include "ccu_reset.h" 20 21 #include "ccu_div.h" 22 #include "ccu_gate.h" 23 #include "ccu_mp.h" 24 #include "ccu_mult.h" 25 #include "ccu_nk.h" 26 #include "ccu_nkm.h" 27 #include "ccu_nkmp.h" 28 #include "ccu_nm.h" 29 #include "ccu_phase.h" 30 #include "ccu_sdm.h" 31 32 #include "ccu-sun8i-a23-a33.h" 33 34 35 static struct ccu_nkmp pll_cpux_clk = { 36 .enable = BIT(31), 37 .lock = BIT(28), 38 39 .n = _SUNXI_CCU_MULT(8, 5), 40 .k = _SUNXI_CCU_MULT(4, 2), 41 .m = _SUNXI_CCU_DIV(0, 2), 42 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 43 44 .common = { 45 .reg = 0x000, 46 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", 47 &ccu_nkmp_ops, 48 0), 49 }, 50 }; 51 52 /* 53 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 54 * the base (2x, 4x and 8x), and one variable divider (the one true 55 * pll audio). 56 * 57 * With sigma-delta modulation for fractional-N on the audio PLL, 58 * we have to use specific dividers. This means the variable divider 59 * can no longer be used, as the audio codec requests the exact clock 60 * rates we support through this mechanism. So we now hard code the 61 * variable divider to 1. This means the clock rates will no longer 62 * match the clock names. 63 */ 64 #define SUN8I_A23_PLL_AUDIO_REG 0x008 65 66 static struct ccu_sdm_setting pll_audio_sdm_table[] = { 67 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 68 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 69 }; 70 71 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 72 "osc24M", 0x008, 73 8, 7, /* N */ 74 0, 5, /* M */ 75 pll_audio_sdm_table, BIT(24), 76 0x284, BIT(31), 77 BIT(31), /* gate */ 78 BIT(28), /* lock */ 79 CLK_SET_RATE_UNGATE); 80 81 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video", 82 "osc24M", 0x010, 83 8, 7, /* N */ 84 0, 4, /* M */ 85 BIT(24), /* frac enable */ 86 BIT(25), /* frac select */ 87 270000000, /* frac rate 0 */ 88 297000000, /* frac rate 1 */ 89 BIT(31), /* gate */ 90 BIT(28), /* lock */ 91 CLK_SET_RATE_UNGATE); 92 93 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 94 "osc24M", 0x018, 95 8, 7, /* N */ 96 0, 4, /* M */ 97 BIT(24), /* frac enable */ 98 BIT(25), /* frac select */ 99 270000000, /* frac rate 0 */ 100 297000000, /* frac rate 1 */ 101 BIT(31), /* gate */ 102 BIT(28), /* lock */ 103 CLK_SET_RATE_UNGATE); 104 105 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", 106 "osc24M", 0x020, 107 8, 5, /* N */ 108 4, 2, /* K */ 109 0, 2, /* M */ 110 BIT(31), /* gate */ 111 BIT(28), /* lock */ 112 0); 113 114 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", 115 "osc24M", 0x028, 116 8, 5, /* N */ 117 4, 2, /* K */ 118 BIT(31), /* gate */ 119 BIT(28), /* lock */ 120 2, /* post-div */ 121 CLK_SET_RATE_UNGATE); 122 123 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 124 "osc24M", 0x038, 125 8, 7, /* N */ 126 0, 4, /* M */ 127 BIT(24), /* frac enable */ 128 BIT(25), /* frac select */ 129 270000000, /* frac rate 0 */ 130 297000000, /* frac rate 1 */ 131 BIT(31), /* gate */ 132 BIT(28), /* lock */ 133 CLK_SET_RATE_UNGATE); 134 135 /* 136 * The MIPI PLL has 2 modes: "MIPI" and "HDMI". 137 * 138 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an 139 * integer / fractional clock with switchable multipliers and dividers. 140 * This is not supported here. We hardcode the PLL to MIPI mode. 141 */ 142 #define SUN8I_A23_PLL_MIPI_REG 0x040 143 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi", 144 "pll-video", 0x040, 145 8, 4, /* N */ 146 4, 2, /* K */ 147 0, 4, /* M */ 148 BIT(31) | BIT(23) | BIT(22), /* gate */ 149 BIT(28), /* lock */ 150 CLK_SET_RATE_UNGATE); 151 152 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", 153 "osc24M", 0x044, 154 8, 7, /* N */ 155 0, 4, /* M */ 156 BIT(24), /* frac enable */ 157 BIT(25), /* frac select */ 158 270000000, /* frac rate 0 */ 159 297000000, /* frac rate 1 */ 160 BIT(31), /* gate */ 161 BIT(28), /* lock */ 162 CLK_SET_RATE_UNGATE); 163 164 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 165 "osc24M", 0x048, 166 8, 7, /* N */ 167 0, 4, /* M */ 168 BIT(24), /* frac enable */ 169 BIT(25), /* frac select */ 170 270000000, /* frac rate 0 */ 171 297000000, /* frac rate 1 */ 172 BIT(31), /* gate */ 173 BIT(28), /* lock */ 174 CLK_SET_RATE_UNGATE); 175 176 static const char * const cpux_parents[] = { "osc32k", "osc24M", 177 "pll-cpux" , "pll-cpux" }; 178 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 179 0x050, 16, 2, CLK_IS_CRITICAL); 180 181 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); 182 183 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 184 "axi" , "pll-periph" }; 185 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 186 { .index = 3, .shift = 6, .width = 2 }, 187 }; 188 static struct ccu_div ahb1_clk = { 189 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 190 191 .mux = { 192 .shift = 12, 193 .width = 2, 194 195 .var_predivs = ahb1_predivs, 196 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 197 }, 198 199 .common = { 200 .reg = 0x054, 201 .features = CCU_FEATURE_VARIABLE_PREDIV, 202 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 203 ahb1_parents, 204 &ccu_div_ops, 205 0), 206 }, 207 }; 208 209 static struct clk_div_table apb1_div_table[] = { 210 { .val = 0, .div = 2 }, 211 { .val = 1, .div = 2 }, 212 { .val = 2, .div = 4 }, 213 { .val = 3, .div = 8 }, 214 { /* Sentinel */ }, 215 }; 216 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 217 0x054, 8, 2, apb1_div_table, 0); 218 219 static const char * const apb2_parents[] = { "osc32k", "osc24M", 220 "pll-periph" , "pll-periph" }; 221 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 222 0, 5, /* M */ 223 16, 2, /* P */ 224 24, 2, /* mux */ 225 0); 226 227 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 228 0x060, BIT(1), 0); 229 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 230 0x060, BIT(6), 0); 231 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 232 0x060, BIT(8), 0); 233 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 234 0x060, BIT(9), 0); 235 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 236 0x060, BIT(10), 0); 237 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 238 0x060, BIT(13), 0); 239 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 240 0x060, BIT(14), 0); 241 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 242 0x060, BIT(19), 0); 243 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 244 0x060, BIT(20), 0); 245 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 246 0x060, BIT(21), 0); 247 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 248 0x060, BIT(24), 0); 249 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1", 250 0x060, BIT(26), 0); 251 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1", 252 0x060, BIT(29), 0); 253 254 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 255 0x064, BIT(0), 0); 256 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1", 257 0x064, BIT(4), 0); 258 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 259 0x064, BIT(8), 0); 260 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1", 261 0x064, BIT(12), 0); 262 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1", 263 0x064, BIT(14), 0); 264 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 265 0x064, BIT(20), 0); 266 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 267 0x064, BIT(21), 0); 268 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 269 0x064, BIT(22), 0); 270 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1", 271 0x064, BIT(25), 0); 272 273 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 274 0x068, BIT(0), 0); 275 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 276 0x068, BIT(5), 0); 277 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 278 0x068, BIT(12), 0); 279 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 280 0x068, BIT(13), 0); 281 282 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 283 0x06c, BIT(0), 0); 284 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 285 0x06c, BIT(1), 0); 286 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 287 0x06c, BIT(2), 0); 288 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 289 0x06c, BIT(16), 0); 290 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 291 0x06c, BIT(17), 0); 292 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 293 0x06c, BIT(18), 0); 294 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 295 0x06c, BIT(19), 0); 296 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 297 0x06c, BIT(20), 0); 298 299 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; 300 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 301 0, 4, /* M */ 302 16, 2, /* P */ 303 24, 2, /* mux */ 304 BIT(31), /* gate */ 305 0); 306 307 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088, 308 0, 4, /* M */ 309 16, 2, /* P */ 310 24, 2, /* mux */ 311 BIT(31), /* gate */ 312 0); 313 314 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 315 0x088, 20, 3, 0); 316 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 317 0x088, 8, 3, 0); 318 319 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c, 320 0, 4, /* M */ 321 16, 2, /* P */ 322 24, 2, /* mux */ 323 BIT(31), /* gate */ 324 0); 325 326 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 327 0x08c, 20, 3, 0); 328 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 329 0x08c, 8, 3, 0); 330 331 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090, 332 0, 4, /* M */ 333 16, 2, /* P */ 334 24, 2, /* mux */ 335 BIT(31), /* gate */ 336 0); 337 338 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", 339 0x090, 20, 3, 0); 340 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", 341 0x090, 8, 3, 0); 342 343 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 344 0, 4, /* M */ 345 16, 2, /* P */ 346 24, 2, /* mux */ 347 BIT(31), /* gate */ 348 0); 349 350 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 351 0, 4, /* M */ 352 16, 2, /* P */ 353 24, 2, /* mux */ 354 BIT(31), /* gate */ 355 0); 356 357 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 358 "pll-audio-2x", "pll-audio" }; 359 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 360 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 361 362 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 363 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 364 365 /* TODO: the parent for most of the USB clocks is not known */ 366 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 367 0x0cc, BIT(8), 0); 368 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 369 0x0cc, BIT(9), 0); 370 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 371 0x0cc, BIT(10), 0); 372 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M", 373 0x0cc, BIT(11), 0); 374 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M", 375 0x0cc, BIT(16), 0); 376 377 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr", 378 0x100, BIT(0), 0); 379 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr", 380 0x100, BIT(1), 0); 381 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr", 382 0x100, BIT(16), 0); 383 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr", 384 0x100, BIT(24), 0); 385 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr", 386 0x100, BIT(26), 0); 387 388 static const char * const de_parents[] = { "pll-video", "pll-periph-2x", 389 "pll-gpu", "pll-de" }; 390 static const u8 de_table[] = { 0, 2, 3, 5 }; 391 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be", 392 de_parents, de_table, 393 0x104, 0, 4, 24, 3, BIT(31), 0); 394 395 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe", 396 de_parents, de_table, 397 0x10c, 0, 4, 24, 3, BIT(31), 0); 398 399 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x", 400 "pll-mipi" }; 401 static const u8 lcd_ch0_table[] = { 0, 2, 4 }; 402 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0", 403 lcd_ch0_parents, lcd_ch0_table, 404 0x118, 24, 3, BIT(31), 405 CLK_SET_RATE_PARENT); 406 407 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" }; 408 static const u8 lcd_ch1_table[] = { 0, 2 }; 409 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1", 410 lcd_ch1_parents, lcd_ch1_table, 411 0x12c, 0, 4, 24, 2, BIT(31), 0); 412 413 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de", 414 "pll-mipi", "pll-ve" }; 415 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 }; 416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk", 417 csi_sclk_parents, csi_sclk_table, 418 0x134, 16, 4, 24, 3, BIT(31), 0); 419 420 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de", 421 "osc24M" }; 422 static const u8 csi_mclk_table[] = { 0, 3, 5 }; 423 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk", 424 csi_mclk_parents, csi_mclk_table, 425 0x134, 0, 5, 8, 3, BIT(15), 0); 426 427 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 428 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); 429 430 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 431 0x140, BIT(31), CLK_SET_RATE_PARENT); 432 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 433 0x144, BIT(31), 0); 434 435 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x", 436 "pll-ddr" }; 437 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 438 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 439 440 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" }; 441 static const u8 dsi_sclk_table[] = { 0, 2 }; 442 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk", 443 dsi_sclk_parents, dsi_sclk_table, 444 0x168, 16, 4, 24, 2, BIT(31), 0); 445 446 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" }; 447 static const u8 dsi_dphy_table[] = { 0, 2 }; 448 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", 449 dsi_dphy_parents, dsi_dphy_table, 450 0x168, 0, 4, 8, 2, BIT(15), 0); 451 452 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc", 453 de_parents, de_table, 454 0x180, 0, 4, 24, 3, BIT(31), 0); 455 456 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 457 0x1a0, 0, 3, BIT(31), 0); 458 459 static const char * const ats_parents[] = { "osc24M", "pll-periph" }; 460 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents, 461 0x1b0, 0, 3, 24, 2, BIT(31), 0); 462 463 static struct ccu_common *sun8i_a23_ccu_clks[] = { 464 &pll_cpux_clk.common, 465 &pll_audio_base_clk.common, 466 &pll_video_clk.common, 467 &pll_ve_clk.common, 468 &pll_ddr_clk.common, 469 &pll_periph_clk.common, 470 &pll_gpu_clk.common, 471 &pll_mipi_clk.common, 472 &pll_hsic_clk.common, 473 &pll_de_clk.common, 474 &cpux_clk.common, 475 &axi_clk.common, 476 &ahb1_clk.common, 477 &apb1_clk.common, 478 &apb2_clk.common, 479 &bus_mipi_dsi_clk.common, 480 &bus_dma_clk.common, 481 &bus_mmc0_clk.common, 482 &bus_mmc1_clk.common, 483 &bus_mmc2_clk.common, 484 &bus_nand_clk.common, 485 &bus_dram_clk.common, 486 &bus_hstimer_clk.common, 487 &bus_spi0_clk.common, 488 &bus_spi1_clk.common, 489 &bus_otg_clk.common, 490 &bus_ehci_clk.common, 491 &bus_ohci_clk.common, 492 &bus_ve_clk.common, 493 &bus_lcd_clk.common, 494 &bus_csi_clk.common, 495 &bus_de_fe_clk.common, 496 &bus_de_be_clk.common, 497 &bus_gpu_clk.common, 498 &bus_msgbox_clk.common, 499 &bus_spinlock_clk.common, 500 &bus_drc_clk.common, 501 &bus_codec_clk.common, 502 &bus_pio_clk.common, 503 &bus_i2s0_clk.common, 504 &bus_i2s1_clk.common, 505 &bus_i2c0_clk.common, 506 &bus_i2c1_clk.common, 507 &bus_i2c2_clk.common, 508 &bus_uart0_clk.common, 509 &bus_uart1_clk.common, 510 &bus_uart2_clk.common, 511 &bus_uart3_clk.common, 512 &bus_uart4_clk.common, 513 &nand_clk.common, 514 &mmc0_clk.common, 515 &mmc0_sample_clk.common, 516 &mmc0_output_clk.common, 517 &mmc1_clk.common, 518 &mmc1_sample_clk.common, 519 &mmc1_output_clk.common, 520 &mmc2_clk.common, 521 &mmc2_sample_clk.common, 522 &mmc2_output_clk.common, 523 &spi0_clk.common, 524 &spi1_clk.common, 525 &i2s0_clk.common, 526 &i2s1_clk.common, 527 &usb_phy0_clk.common, 528 &usb_phy1_clk.common, 529 &usb_hsic_clk.common, 530 &usb_hsic_12M_clk.common, 531 &usb_ohci_clk.common, 532 &dram_ve_clk.common, 533 &dram_csi_clk.common, 534 &dram_drc_clk.common, 535 &dram_de_fe_clk.common, 536 &dram_de_be_clk.common, 537 &de_be_clk.common, 538 &de_fe_clk.common, 539 &lcd_ch0_clk.common, 540 &lcd_ch1_clk.common, 541 &csi_sclk_clk.common, 542 &csi_mclk_clk.common, 543 &ve_clk.common, 544 &ac_dig_clk.common, 545 &avs_clk.common, 546 &mbus_clk.common, 547 &dsi_sclk_clk.common, 548 &dsi_dphy_clk.common, 549 &drc_clk.common, 550 &gpu_clk.common, 551 &ats_clk.common, 552 }; 553 554 /* We hardcode the divider to 1 for now */ 555 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 556 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 557 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 558 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 559 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 560 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 561 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 562 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 563 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", 564 "pll-periph", 1, 2, 0); 565 static CLK_FIXED_FACTOR(pll_video_2x_clk, "pll-video-2x", 566 "pll-video", 1, 2, 0); 567 568 static struct clk_hw_onecell_data sun8i_a23_hw_clks = { 569 .hws = { 570 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 571 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 572 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 573 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 574 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 575 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 576 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw, 577 [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw, 578 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 579 [CLK_PLL_DDR0] = &pll_ddr_clk.common.hw, 580 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, 581 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw, 582 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 583 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 584 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 585 [CLK_PLL_DE] = &pll_de_clk.common.hw, 586 [CLK_CPUX] = &cpux_clk.common.hw, 587 [CLK_AXI] = &axi_clk.common.hw, 588 [CLK_AHB1] = &ahb1_clk.common.hw, 589 [CLK_APB1] = &apb1_clk.common.hw, 590 [CLK_APB2] = &apb2_clk.common.hw, 591 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 592 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 593 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 594 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 595 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 596 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 597 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 598 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 599 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 600 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 601 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 602 [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw, 603 [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw, 604 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 605 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw, 606 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 607 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw, 608 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw, 609 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 610 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 611 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 612 [CLK_BUS_DRC] = &bus_drc_clk.common.hw, 613 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 614 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 615 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 616 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 617 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 618 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 619 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 620 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 621 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 622 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 623 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 624 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 625 [CLK_NAND] = &nand_clk.common.hw, 626 [CLK_MMC0] = &mmc0_clk.common.hw, 627 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 628 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 629 [CLK_MMC1] = &mmc1_clk.common.hw, 630 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 631 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 632 [CLK_MMC2] = &mmc2_clk.common.hw, 633 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 634 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 635 [CLK_SPI0] = &spi0_clk.common.hw, 636 [CLK_SPI1] = &spi1_clk.common.hw, 637 [CLK_I2S0] = &i2s0_clk.common.hw, 638 [CLK_I2S1] = &i2s1_clk.common.hw, 639 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 640 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 641 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 642 [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw, 643 [CLK_USB_OHCI] = &usb_ohci_clk.common.hw, 644 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 645 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 646 [CLK_DRAM_DRC] = &dram_drc_clk.common.hw, 647 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw, 648 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw, 649 [CLK_DE_BE] = &de_be_clk.common.hw, 650 [CLK_DE_FE] = &de_fe_clk.common.hw, 651 [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw, 652 [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw, 653 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 654 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 655 [CLK_VE] = &ve_clk.common.hw, 656 [CLK_AC_DIG] = &ac_dig_clk.common.hw, 657 [CLK_AVS] = &avs_clk.common.hw, 658 [CLK_MBUS] = &mbus_clk.common.hw, 659 [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw, 660 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, 661 [CLK_DRC] = &drc_clk.common.hw, 662 [CLK_GPU] = &gpu_clk.common.hw, 663 [CLK_ATS] = &ats_clk.common.hw, 664 }, 665 .num = CLK_NUMBER, 666 }; 667 668 static struct ccu_reset_map sun8i_a23_ccu_resets[] = { 669 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 670 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 671 [RST_USB_HSIC] = { 0x0cc, BIT(2) }, 672 673 [RST_MBUS] = { 0x0fc, BIT(31) }, 674 675 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 676 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 677 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 678 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 679 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 680 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 681 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 682 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 683 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 684 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 685 [RST_BUS_OTG] = { 0x2c0, BIT(24) }, 686 [RST_BUS_EHCI] = { 0x2c0, BIT(26) }, 687 [RST_BUS_OHCI] = { 0x2c0, BIT(29) }, 688 689 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 690 [RST_BUS_LCD] = { 0x2c4, BIT(4) }, 691 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 692 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) }, 693 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) }, 694 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 695 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, 696 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, 697 [RST_BUS_DRC] = { 0x2c4, BIT(25) }, 698 699 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 700 701 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 702 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 703 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 704 705 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 706 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 707 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 708 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 709 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 710 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 711 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 712 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 713 }; 714 715 static const struct sunxi_ccu_desc sun8i_a23_ccu_desc = { 716 .ccu_clks = sun8i_a23_ccu_clks, 717 .num_ccu_clks = ARRAY_SIZE(sun8i_a23_ccu_clks), 718 719 .hw_clks = &sun8i_a23_hw_clks, 720 721 .resets = sun8i_a23_ccu_resets, 722 .num_resets = ARRAY_SIZE(sun8i_a23_ccu_resets), 723 }; 724 725 static void __init sun8i_a23_ccu_setup(struct device_node *node) 726 { 727 void __iomem *reg; 728 u32 val; 729 730 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 731 if (IS_ERR(reg)) { 732 pr_err("%pOF: Could not map the clock registers\n", node); 733 return; 734 } 735 736 /* Force the PLL-Audio-1x divider to 1 */ 737 val = readl(reg + SUN8I_A23_PLL_AUDIO_REG); 738 val &= ~GENMASK(19, 16); 739 writel(val | (0 << 16), reg + SUN8I_A23_PLL_AUDIO_REG); 740 741 /* Force PLL-MIPI to MIPI mode */ 742 val = readl(reg + SUN8I_A23_PLL_MIPI_REG); 743 val &= ~BIT(16); 744 writel(val, reg + SUN8I_A23_PLL_MIPI_REG); 745 746 sunxi_ccu_probe(node, reg, &sun8i_a23_ccu_desc); 747 } 748 CLK_OF_DECLARE(sun8i_a23_ccu, "allwinner,sun8i-a23-ccu", 749 sun8i_a23_ccu_setup); 750