1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 2016 Maxime Ripard
4  *
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  */
7 
8 #ifndef _CCU_SUN8I_A23_A33_H_
9 #define _CCU_SUN8I_A23_A33_H_
10 
11 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
12 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
13 
14 #define CLK_PLL_CPUX		0
15 #define CLK_PLL_AUDIO_BASE	1
16 #define CLK_PLL_AUDIO		2
17 #define CLK_PLL_AUDIO_2X	3
18 #define CLK_PLL_AUDIO_4X	4
19 #define CLK_PLL_AUDIO_8X	5
20 #define CLK_PLL_VIDEO		6
21 #define CLK_PLL_VIDEO_2X	7
22 #define CLK_PLL_VE		8
23 #define CLK_PLL_DDR0		9
24 #define CLK_PLL_PERIPH		10
25 #define CLK_PLL_PERIPH_2X	11
26 #define CLK_PLL_GPU		12
27 
28 /* The PLL MIPI clock is exported */
29 
30 #define CLK_PLL_HSIC		14
31 #define CLK_PLL_DE		15
32 #define CLK_PLL_DDR1		16
33 #define CLK_PLL_DDR		17
34 
35 /* The CPUX clock is exported */
36 
37 #define CLK_AXI			19
38 #define CLK_AHB1		20
39 #define CLK_APB1		21
40 #define CLK_APB2		22
41 
42 /* All the bus gates are exported */
43 
44 /* The first part of the mod clocks is exported */
45 
46 #define CLK_DRAM		79
47 
48 /* Some more module clocks are exported */
49 
50 #define CLK_MBUS		95
51 
52 /* And the last module clocks are exported */
53 
54 #define CLK_NUMBER		(CLK_ATS + 1)
55 
56 #endif /* _CCU_SUN8I_A23_A33_H_ */
57