1 /* 2 * Copyright 2016 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _CCU_SUN6I_A31_H_ 18 #define _CCU_SUN6I_A31_H_ 19 20 #include <dt-bindings/clock/sun6i-a31-ccu.h> 21 #include <dt-bindings/reset/sun6i-a31-ccu.h> 22 23 #define CLK_PLL_CPU 0 24 #define CLK_PLL_AUDIO_BASE 1 25 #define CLK_PLL_AUDIO 2 26 #define CLK_PLL_AUDIO_2X 3 27 #define CLK_PLL_AUDIO_4X 4 28 #define CLK_PLL_AUDIO_8X 5 29 #define CLK_PLL_VIDEO0 6 30 #define CLK_PLL_VIDEO0_2X 7 31 #define CLK_PLL_VE 8 32 #define CLK_PLL_DDR 9 33 34 /* The PLL_PERIPH clock is exported */ 35 36 #define CLK_PLL_PERIPH_2X 11 37 #define CLK_PLL_VIDEO1 12 38 #define CLK_PLL_VIDEO1_2X 13 39 #define CLK_PLL_GPU 14 40 #define CLK_PLL_MIPI 15 41 #define CLK_PLL9 16 42 #define CLK_PLL10 17 43 44 /* The CPUX clock is exported */ 45 46 #define CLK_AXI 19 47 #define CLK_AHB1 20 48 #define CLK_APB1 21 49 #define CLK_APB2 22 50 51 /* All the bus gates are exported */ 52 53 /* The first bunch of module clocks are exported */ 54 55 /* EMAC clock is not implemented */ 56 57 #define CLK_MDFS 107 58 #define CLK_SDRAM0 108 59 #define CLK_SDRAM1 109 60 61 /* All the DRAM gates are exported */ 62 63 /* Some more module clocks are exported */ 64 65 #define CLK_MBUS0 141 66 #define CLK_MBUS1 142 67 68 /* Some more module clocks and external clock outputs are exported */ 69 70 #define CLK_NUMBER (CLK_OUT_C + 1) 71 72 #endif /* _CCU_SUN6I_A31_H_ */ 73