1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2016 Chen-Yu Tsai
4  *
5  * Chen-Yu Tsai <wens@csie.org>
6  *
7  * Based on ccu-sun8i-h3.c by Maxime Ripard.
8  */
9 
10 #include <linux/clk-provider.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 
15 #include "ccu_common.h"
16 #include "ccu_reset.h"
17 
18 #include "ccu_div.h"
19 #include "ccu_gate.h"
20 #include "ccu_mp.h"
21 #include "ccu_mult.h"
22 #include "ccu_mux.h"
23 #include "ccu_nk.h"
24 #include "ccu_nkm.h"
25 #include "ccu_nkmp.h"
26 #include "ccu_nm.h"
27 #include "ccu_phase.h"
28 #include "ccu_sdm.h"
29 
30 #include "ccu-sun6i-a31.h"
31 
32 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
33 				     "osc24M", 0x000,
34 				     8, 5,	/* N */
35 				     4, 2,	/* K */
36 				     0, 2,	/* M */
37 				     BIT(31),	/* gate */
38 				     BIT(28),	/* lock */
39 				     0);
40 
41 /*
42  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
43  * the base (2x, 4x and 8x), and one variable divider (the one true
44  * pll audio).
45  *
46  * With sigma-delta modulation for fractional-N on the audio PLL,
47  * we have to use specific dividers. This means the variable divider
48  * can no longer be used, as the audio codec requests the exact clock
49  * rates we support through this mechanism. So we now hard code the
50  * variable divider to 1. This means the clock rates will no longer
51  * match the clock names.
52  */
53 #define SUN6I_A31_PLL_AUDIO_REG	0x008
54 
55 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
56 	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
58 };
59 
60 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
61 				       "osc24M", 0x008,
62 				       8, 7,	/* N */
63 				       0, 5,	/* M */
64 				       pll_audio_sdm_table, BIT(24),
65 				       0x284, BIT(31),
66 				       BIT(31),	/* gate */
67 				       BIT(28),	/* lock */
68 				       CLK_SET_RATE_UNGATE);
69 
70 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
71 					"osc24M", 0x010,
72 					8, 7,		/* N */
73 					0, 4,		/* M */
74 					BIT(24),	/* frac enable */
75 					BIT(25),	/* frac select */
76 					270000000,	/* frac rate 0 */
77 					297000000,	/* frac rate 1 */
78 					BIT(31),	/* gate */
79 					BIT(28),	/* lock */
80 					CLK_SET_RATE_UNGATE);
81 
82 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
83 					"osc24M", 0x018,
84 					8, 7,		/* N */
85 					0, 4,		/* M */
86 					BIT(24),	/* frac enable */
87 					BIT(25),	/* frac select */
88 					270000000,	/* frac rate 0 */
89 					297000000,	/* frac rate 1 */
90 					BIT(31),	/* gate */
91 					BIT(28),	/* lock */
92 					CLK_SET_RATE_UNGATE);
93 
94 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
95 				    "osc24M", 0x020,
96 				    8, 5,	/* N */
97 				    4, 2,	/* K */
98 				    0, 2,	/* M */
99 				    BIT(31),	/* gate */
100 				    BIT(28),	/* lock */
101 				    CLK_SET_RATE_UNGATE);
102 
103 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
104 					   "osc24M", 0x028,
105 					   8, 5,	/* N */
106 					   4, 2,	/* K */
107 					   BIT(31),	/* gate */
108 					   BIT(28),	/* lock */
109 					   2,		/* post-div */
110 					   CLK_SET_RATE_UNGATE);
111 
112 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
113 					"osc24M", 0x030,
114 					8, 7,		/* N */
115 					0, 4,		/* M */
116 					BIT(24),	/* frac enable */
117 					BIT(25),	/* frac select */
118 					270000000,	/* frac rate 0 */
119 					297000000,	/* frac rate 1 */
120 					BIT(31),	/* gate */
121 					BIT(28),	/* lock */
122 					CLK_SET_RATE_UNGATE);
123 
124 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
125 					"osc24M", 0x038,
126 					8, 7,		/* N */
127 					0, 4,		/* M */
128 					BIT(24),	/* frac enable */
129 					BIT(25),	/* frac select */
130 					270000000,	/* frac rate 0 */
131 					297000000,	/* frac rate 1 */
132 					BIT(31),	/* gate */
133 					BIT(28),	/* lock */
134 					CLK_SET_RATE_UNGATE);
135 
136 /*
137  * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
138  *
139  * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
140  * integer / fractional clock with switchable multipliers and dividers.
141  * This is not supported here. We hardcode the PLL to MIPI mode.
142  */
143 #define SUN6I_A31_PLL_MIPI_REG	0x040
144 
145 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" };
146 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi",
147 					pll_mipi_parents, 0x040,
148 					8, 4,	/* N */
149 					4, 2,	/* K */
150 					0, 4,	/* M */
151 					21, 0,	/* mux */
152 					BIT(31) | BIT(23) | BIT(22), /* gate */
153 					BIT(28),	/* lock */
154 					CLK_SET_RATE_UNGATE);
155 
156 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9",
157 					"osc24M", 0x044,
158 					8, 7,		/* N */
159 					0, 4,		/* M */
160 					BIT(24),	/* frac enable */
161 					BIT(25),	/* frac select */
162 					270000000,	/* frac rate 0 */
163 					297000000,	/* frac rate 1 */
164 					BIT(31),	/* gate */
165 					BIT(28),	/* lock */
166 					CLK_SET_RATE_UNGATE);
167 
168 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10",
169 					"osc24M", 0x048,
170 					8, 7,		/* N */
171 					0, 4,		/* M */
172 					BIT(24),	/* frac enable */
173 					BIT(25),	/* frac select */
174 					270000000,	/* frac rate 0 */
175 					297000000,	/* frac rate 1 */
176 					BIT(31),	/* gate */
177 					BIT(28),	/* lock */
178 					CLK_SET_RATE_UNGATE);
179 
180 static const char * const cpux_parents[] = { "osc32k", "osc24M",
181 					     "pll-cpu", "pll-cpu" };
182 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents,
183 		     0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
184 
185 static struct clk_div_table axi_div_table[] = {
186 	{ .val = 0, .div = 1 },
187 	{ .val = 1, .div = 2 },
188 	{ .val = 2, .div = 3 },
189 	{ .val = 3, .div = 4 },
190 	{ .val = 4, .div = 4 },
191 	{ .val = 5, .div = 4 },
192 	{ .val = 6, .div = 4 },
193 	{ .val = 7, .div = 4 },
194 	{ /* Sentinel */ },
195 };
196 
197 static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu",
198 			   0x050, 0, 3, axi_div_table, 0);
199 
200 #define SUN6I_A31_AHB1_REG  0x054
201 
202 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
203 					     "axi", "pll-periph" };
204 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
205 	{ .index = 3, .shift = 6, .width = 2 },
206 };
207 
208 static struct ccu_div ahb1_clk = {
209 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
210 
211 	.mux		= {
212 		.shift	= 12,
213 		.width	= 2,
214 
215 		.var_predivs	= ahb1_predivs,
216 		.n_var_predivs	= ARRAY_SIZE(ahb1_predivs),
217 	},
218 
219 	.common		= {
220 		.reg		= 0x054,
221 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
222 		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
223 						      ahb1_parents,
224 						      &ccu_div_ops,
225 						      0),
226 	},
227 };
228 
229 static struct clk_div_table apb1_div_table[] = {
230 	{ .val = 0, .div = 2 },
231 	{ .val = 1, .div = 2 },
232 	{ .val = 2, .div = 4 },
233 	{ .val = 3, .div = 8 },
234 	{ /* Sentinel */ },
235 };
236 
237 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
238 			   0x054, 8, 2, apb1_div_table, 0);
239 
240 static const char * const apb2_parents[] = { "osc32k", "osc24M",
241 					     "pll-periph", "pll-periph" };
242 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
243 			     0, 5,	/* M */
244 			     16, 2,	/* P */
245 			     24, 2,	/* mux */
246 			     0);
247 
248 static SUNXI_CCU_GATE(ahb1_mipidsi_clk,	"ahb1-mipidsi",	"ahb1",
249 		      0x060, BIT(1), 0);
250 static SUNXI_CCU_GATE(ahb1_ss_clk,	"ahb1-ss",	"ahb1",
251 		      0x060, BIT(5), 0);
252 static SUNXI_CCU_GATE(ahb1_dma_clk,	"ahb1-dma",	"ahb1",
253 		      0x060, BIT(6), 0);
254 static SUNXI_CCU_GATE(ahb1_mmc0_clk,	"ahb1-mmc0",	"ahb1",
255 		      0x060, BIT(8), 0);
256 static SUNXI_CCU_GATE(ahb1_mmc1_clk,	"ahb1-mmc1",	"ahb1",
257 		      0x060, BIT(9), 0);
258 static SUNXI_CCU_GATE(ahb1_mmc2_clk,	"ahb1-mmc2",	"ahb1",
259 		      0x060, BIT(10), 0);
260 static SUNXI_CCU_GATE(ahb1_mmc3_clk,	"ahb1-mmc3",	"ahb1",
261 		      0x060, BIT(11), 0);
262 static SUNXI_CCU_GATE(ahb1_nand1_clk,	"ahb1-nand1",	"ahb1",
263 		      0x060, BIT(12), 0);
264 static SUNXI_CCU_GATE(ahb1_nand0_clk,	"ahb1-nand0",	"ahb1",
265 		      0x060, BIT(13), 0);
266 static SUNXI_CCU_GATE(ahb1_sdram_clk,	"ahb1-sdram",	"ahb1",
267 		      0x060, BIT(14), 0);
268 static SUNXI_CCU_GATE(ahb1_emac_clk,	"ahb1-emac",	"ahb1",
269 		      0x060, BIT(17), 0);
270 static SUNXI_CCU_GATE(ahb1_ts_clk,	"ahb1-ts",	"ahb1",
271 		      0x060, BIT(18), 0);
272 static SUNXI_CCU_GATE(ahb1_hstimer_clk,	"ahb1-hstimer",	"ahb1",
273 		      0x060, BIT(19), 0);
274 static SUNXI_CCU_GATE(ahb1_spi0_clk,	"ahb1-spi0",	"ahb1",
275 		      0x060, BIT(20), 0);
276 static SUNXI_CCU_GATE(ahb1_spi1_clk,	"ahb1-spi1",	"ahb1",
277 		      0x060, BIT(21), 0);
278 static SUNXI_CCU_GATE(ahb1_spi2_clk,	"ahb1-spi2",	"ahb1",
279 		      0x060, BIT(22), 0);
280 static SUNXI_CCU_GATE(ahb1_spi3_clk,	"ahb1-spi3",	"ahb1",
281 		      0x060, BIT(23), 0);
282 static SUNXI_CCU_GATE(ahb1_otg_clk,	"ahb1-otg",	"ahb1",
283 		      0x060, BIT(24), 0);
284 static SUNXI_CCU_GATE(ahb1_ehci0_clk,	"ahb1-ehci0",	"ahb1",
285 		      0x060, BIT(26), 0);
286 static SUNXI_CCU_GATE(ahb1_ehci1_clk,	"ahb1-ehci1",	"ahb1",
287 		      0x060, BIT(27), 0);
288 static SUNXI_CCU_GATE(ahb1_ohci0_clk,	"ahb1-ohci0",	"ahb1",
289 		      0x060, BIT(29), 0);
290 static SUNXI_CCU_GATE(ahb1_ohci1_clk,	"ahb1-ohci1",	"ahb1",
291 		      0x060, BIT(30), 0);
292 static SUNXI_CCU_GATE(ahb1_ohci2_clk,	"ahb1-ohci2",	"ahb1",
293 		      0x060, BIT(31), 0);
294 
295 static SUNXI_CCU_GATE(ahb1_ve_clk,	"ahb1-ve",	"ahb1",
296 		      0x064, BIT(0), 0);
297 static SUNXI_CCU_GATE(ahb1_lcd0_clk,	"ahb1-lcd0",	"ahb1",
298 		      0x064, BIT(4), 0);
299 static SUNXI_CCU_GATE(ahb1_lcd1_clk,	"ahb1-lcd1",	"ahb1",
300 		      0x064, BIT(5), 0);
301 static SUNXI_CCU_GATE(ahb1_csi_clk,	"ahb1-csi",	"ahb1",
302 		      0x064, BIT(8), 0);
303 static SUNXI_CCU_GATE(ahb1_hdmi_clk,	"ahb1-hdmi",	"ahb1",
304 		      0x064, BIT(11), 0);
305 static SUNXI_CCU_GATE(ahb1_be0_clk,	"ahb1-be0",	"ahb1",
306 		      0x064, BIT(12), 0);
307 static SUNXI_CCU_GATE(ahb1_be1_clk,	"ahb1-be1",	"ahb1",
308 		      0x064, BIT(13), 0);
309 static SUNXI_CCU_GATE(ahb1_fe0_clk,	"ahb1-fe0",	"ahb1",
310 		      0x064, BIT(14), 0);
311 static SUNXI_CCU_GATE(ahb1_fe1_clk,	"ahb1-fe1",	"ahb1",
312 		      0x064, BIT(15), 0);
313 static SUNXI_CCU_GATE(ahb1_mp_clk,	"ahb1-mp",	"ahb1",
314 		      0x064, BIT(18), 0);
315 static SUNXI_CCU_GATE(ahb1_gpu_clk,	"ahb1-gpu",	"ahb1",
316 		      0x064, BIT(20), 0);
317 static SUNXI_CCU_GATE(ahb1_deu0_clk,	"ahb1-deu0",	"ahb1",
318 		      0x064, BIT(23), 0);
319 static SUNXI_CCU_GATE(ahb1_deu1_clk,	"ahb1-deu1",	"ahb1",
320 		      0x064, BIT(24), 0);
321 static SUNXI_CCU_GATE(ahb1_drc0_clk,	"ahb1-drc0",	"ahb1",
322 		      0x064, BIT(25), 0);
323 static SUNXI_CCU_GATE(ahb1_drc1_clk,	"ahb1-drc1",	"ahb1",
324 		      0x064, BIT(26), 0);
325 
326 static SUNXI_CCU_GATE(apb1_codec_clk,	"apb1-codec",	"apb1",
327 		      0x068, BIT(0), 0);
328 static SUNXI_CCU_GATE(apb1_spdif_clk,	"apb1-spdif",	"apb1",
329 		      0x068, BIT(1), 0);
330 static SUNXI_CCU_GATE(apb1_digital_mic_clk,	"apb1-digital-mic",	"apb1",
331 		      0x068, BIT(4), 0);
332 static SUNXI_CCU_GATE(apb1_pio_clk,	"apb1-pio",	"apb1",
333 		      0x068, BIT(5), 0);
334 static SUNXI_CCU_GATE(apb1_daudio0_clk,	"apb1-daudio0",	"apb1",
335 		      0x068, BIT(12), 0);
336 static SUNXI_CCU_GATE(apb1_daudio1_clk,	"apb1-daudio1",	"apb1",
337 		      0x068, BIT(13), 0);
338 
339 static SUNXI_CCU_GATE(apb2_i2c0_clk,	"apb2-i2c0",	"apb2",
340 		      0x06c, BIT(0), 0);
341 static SUNXI_CCU_GATE(apb2_i2c1_clk,	"apb2-i2c1",	"apb2",
342 		      0x06c, BIT(1), 0);
343 static SUNXI_CCU_GATE(apb2_i2c2_clk,	"apb2-i2c2",	"apb2",
344 		      0x06c, BIT(2), 0);
345 static SUNXI_CCU_GATE(apb2_i2c3_clk,	"apb2-i2c3",	"apb2",
346 		      0x06c, BIT(3), 0);
347 static SUNXI_CCU_GATE(apb2_uart0_clk,	"apb2-uart0",	"apb2",
348 		      0x06c, BIT(16), 0);
349 static SUNXI_CCU_GATE(apb2_uart1_clk,	"apb2-uart1",	"apb2",
350 		      0x06c, BIT(17), 0);
351 static SUNXI_CCU_GATE(apb2_uart2_clk,	"apb2-uart2",	"apb2",
352 		      0x06c, BIT(18), 0);
353 static SUNXI_CCU_GATE(apb2_uart3_clk,	"apb2-uart3",	"apb2",
354 		      0x06c, BIT(19), 0);
355 static SUNXI_CCU_GATE(apb2_uart4_clk,	"apb2-uart4",	"apb2",
356 		      0x06c, BIT(20), 0);
357 static SUNXI_CCU_GATE(apb2_uart5_clk,	"apb2-uart5",	"apb2",
358 		      0x06c, BIT(21), 0);
359 
360 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
361 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents,
362 				  0x080,
363 				  0, 4,		/* M */
364 				  16, 2,	/* P */
365 				  24, 2,	/* mux */
366 				  BIT(31),	/* gate */
367 				  0);
368 
369 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents,
370 				  0x084,
371 				  0, 4,		/* M */
372 				  16, 2,	/* P */
373 				  24, 2,	/* mux */
374 				  BIT(31),	/* gate */
375 				  0);
376 
377 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents,
378 				  0x088,
379 				  0, 4,		/* M */
380 				  16, 2,	/* P */
381 				  24, 2,	/* mux */
382 				  BIT(31),	/* gate */
383 				  0);
384 
385 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
386 		       0x088, 20, 3, 0);
387 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
388 		       0x088, 8, 3, 0);
389 
390 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents,
391 				  0x08c,
392 				  0, 4,		/* M */
393 				  16, 2,	/* P */
394 				  24, 2,	/* mux */
395 				  BIT(31),	/* gate */
396 				  0);
397 
398 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
399 		       0x08c, 20, 3, 0);
400 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
401 		       0x08c, 8, 3, 0);
402 
403 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents,
404 				  0x090,
405 				  0, 4,		/* M */
406 				  16, 2,	/* P */
407 				  24, 2,	/* mux */
408 				  BIT(31),	/* gate */
409 				  0);
410 
411 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
412 		       0x090, 20, 3, 0);
413 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
414 		       0x090, 8, 3, 0);
415 
416 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents,
417 				  0x094,
418 				  0, 4,		/* M */
419 				  16, 2,	/* P */
420 				  24, 2,	/* mux */
421 				  BIT(31),	/* gate */
422 				  0);
423 
424 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
425 		       0x094, 20, 3, 0);
426 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
427 		       0x094, 8, 3, 0);
428 
429 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
430 				  0, 4,		/* M */
431 				  16, 2,	/* P */
432 				  24, 2,	/* mux */
433 				  BIT(31),	/* gate */
434 				  0);
435 
436 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
437 				  0, 4,		/* M */
438 				  16, 2,	/* P */
439 				  24, 2,	/* mux */
440 				  BIT(31),	/* gate */
441 				  0);
442 
443 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
444 				  0, 4,		/* M */
445 				  16, 2,	/* P */
446 				  24, 2,	/* mux */
447 				  BIT(31),	/* gate */
448 				  0);
449 
450 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
451 				  0, 4,		/* M */
452 				  16, 2,	/* P */
453 				  24, 2,	/* mux */
454 				  BIT(31),	/* gate */
455 				  0);
456 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
457 				  0, 4,		/* M */
458 				  16, 2,	/* P */
459 				  24, 2,	/* mux */
460 				  BIT(31),	/* gate */
461 				  0);
462 
463 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac,
464 				  0, 4,		/* M */
465 				  16, 2,	/* P */
466 				  24, 2,	/* mux */
467 				  BIT(31),	/* gate */
468 				  0);
469 
470 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x",
471 					       "pll-audio-2x", "pll-audio" };
472 static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents,
473 			       0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
474 static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents,
475 			       0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
476 
477 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents,
478 			       0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
479 
480 static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
481 		      0x0cc, BIT(8), 0);
482 static SUNXI_CCU_GATE(usb_phy1_clk,	"usb-phy1",	"osc24M",
483 		      0x0cc, BIT(9), 0);
484 static SUNXI_CCU_GATE(usb_phy2_clk,	"usb-phy2",	"osc24M",
485 		      0x0cc, BIT(10), 0);
486 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc24M",
487 		      0x0cc, BIT(16), 0);
488 static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"osc24M",
489 		      0x0cc, BIT(17), 0);
490 static SUNXI_CCU_GATE(usb_ohci2_clk,	"usb-ohci2",	"osc24M",
491 		      0x0cc, BIT(18), 0);
492 
493 /* TODO emac clk not supported yet */
494 
495 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" };
496 static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0,
497 				  0, 4,		/* M */
498 				  16, 2,	/* P */
499 				  24, 2,	/* mux */
500 				  BIT(31),	/* gate */
501 				  CLK_IS_CRITICAL);
502 
503 static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents,
504 			    0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL);
505 static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents,
506 			    0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL);
507 
508 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"mdfs",
509 		      0x100, BIT(0), 0);
510 static SUNXI_CCU_GATE(dram_csi_isp_clk,	"dram-csi-isp",	"mdfs",
511 		      0x100, BIT(1), 0);
512 static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"mdfs",
513 		      0x100, BIT(3), 0);
514 static SUNXI_CCU_GATE(dram_drc0_clk,	"dram-drc0",	"mdfs",
515 		      0x100, BIT(16), 0);
516 static SUNXI_CCU_GATE(dram_drc1_clk,	"dram-drc1",	"mdfs",
517 		      0x100, BIT(17), 0);
518 static SUNXI_CCU_GATE(dram_deu0_clk,	"dram-deu0",	"mdfs",
519 		      0x100, BIT(18), 0);
520 static SUNXI_CCU_GATE(dram_deu1_clk,	"dram-deu1",	"mdfs",
521 		      0x100, BIT(19), 0);
522 static SUNXI_CCU_GATE(dram_fe0_clk,	"dram-fe0",	"mdfs",
523 		      0x100, BIT(24), 0);
524 static SUNXI_CCU_GATE(dram_fe1_clk,	"dram-fe1",	"mdfs",
525 		      0x100, BIT(25), 0);
526 static SUNXI_CCU_GATE(dram_be0_clk,	"dram-be0",	"mdfs",
527 		      0x100, BIT(26), 0);
528 static SUNXI_CCU_GATE(dram_be1_clk,	"dram-be1",	"mdfs",
529 		      0x100, BIT(27), 0);
530 static SUNXI_CCU_GATE(dram_mp_clk,	"dram-mp",	"mdfs",
531 		      0x100, BIT(28), 0);
532 
533 static const char * const de_parents[] = { "pll-video0", "pll-video1",
534 					   "pll-periph-2x", "pll-gpu",
535 					   "pll9", "pll10" };
536 static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents,
537 				 0x104, 0, 4, 24, 3, BIT(31), 0);
538 static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents,
539 				 0x108, 0, 4, 24, 3, BIT(31), 0);
540 static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents,
541 				 0x10c, 0, 4, 24, 3, BIT(31), 0);
542 static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents,
543 				 0x110, 0, 4, 24, 3, BIT(31), 0);
544 
545 static const char * const mp_parents[] = { "pll-video0", "pll-video1",
546 					   "pll9", "pll10" };
547 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents,
548 				 0x114, 0, 4, 24, 3, BIT(31), 0);
549 
550 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1",
551 						"pll-video0-2x",
552 						"pll-video1-2x", "pll-mipi" };
553 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents,
554 			       0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
555 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents,
556 			       0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
557 
558 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1",
559 						"pll-video0-2x",
560 						"pll-video1-2x" };
561 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents,
562 				 0x12c, 0, 4, 24, 3, BIT(31),
563 				 CLK_SET_RATE_PARENT);
564 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
565 				 0x130, 0, 4, 24, 3, BIT(31),
566 				 CLK_SET_RATE_PARENT);
567 
568 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",
569 						 "pll9", "pll10", "pll-mipi",
570 						 "pll-ve" };
571 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents,
572 				 0x134, 16, 4, 24, 3, BIT(31), 0);
573 
574 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1",
575 						 "osc24M" };
576 static const u8 csi_mclk_table[] = { 0, 1, 5 };
577 static struct ccu_div csi0_mclk_clk = {
578 	.enable		= BIT(15),
579 	.div		= _SUNXI_CCU_DIV(0, 4),
580 	.mux		= _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
581 	.common		= {
582 		.reg		= 0x134,
583 		.hw.init	= CLK_HW_INIT_PARENTS("csi0-mclk",
584 						      csi_mclk_parents,
585 						      &ccu_div_ops,
586 						      0),
587 	},
588 };
589 
590 static struct ccu_div csi1_mclk_clk = {
591 	.enable		= BIT(15),
592 	.div		= _SUNXI_CCU_DIV(0, 4),
593 	.mux		= _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table),
594 	.common		= {
595 		.reg		= 0x138,
596 		.hw.init	= CLK_HW_INIT_PARENTS("csi1-mclk",
597 						      csi_mclk_parents,
598 						      &ccu_div_ops,
599 						      0),
600 	},
601 };
602 
603 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
604 			     0x13c, 16, 3, BIT(31), 0);
605 
606 static SUNXI_CCU_GATE(codec_clk,	"codec",	"pll-audio",
607 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
608 static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
609 		      0x144, BIT(31), 0);
610 static SUNXI_CCU_GATE(digital_mic_clk,	"digital-mic",	"pll-audio",
611 		      0x148, BIT(31), CLK_SET_RATE_PARENT);
612 
613 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents,
614 				 0x150, 0, 4, 24, 2, BIT(31),
615 				 CLK_SET_RATE_PARENT);
616 
617 static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);
618 
619 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
620 
621 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
622 					     "pll-ddr" };
623 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c,
624 				  0, 3,		/* M */
625 				  16, 2,	/* P */
626 				  24, 2,	/* mux */
627 				  BIT(31),	/* gate */
628 				  CLK_IS_CRITICAL);
629 
630 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160,
631 				  0, 3,		/* M */
632 				  16, 2,	/* P */
633 				  24, 2,	/* mux */
634 				  BIT(31),	/* gate */
635 				  CLK_IS_CRITICAL);
636 
637 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents,
638 				 0x168, 16, 3, 24, 2, BIT(31),
639 				 CLK_SET_RATE_PARENT);
640 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy",
641 				 lcd_ch1_parents, 0x168, 0, 3, 8, 2,
642 				 BIT(15), CLK_SET_RATE_PARENT);
643 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy",
644 				 lcd_ch1_parents, 0x16c, 0, 3, 8, 2,
645 				 BIT(15), 0);
646 
647 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents,
648 				 0x180, 0, 3, 24, 2, BIT(31), 0);
649 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents,
650 				 0x184, 0, 3, 24, 2, BIT(31), 0);
651 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents,
652 				 0x188, 0, 3, 24, 2, BIT(31), 0);
653 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents,
654 				 0x18c, 0, 3, 24, 2, BIT(31), 0);
655 
656 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x",
657 					    "pll-video0", "pll-video1",
658 					    "pll9", "pll10" };
659 static const struct ccu_mux_fixed_prediv gpu_predivs[] = {
660 	{ .index = 1, .div = 3, },
661 };
662 
663 static struct ccu_div gpu_core_clk = {
664 	.enable		= BIT(31),
665 	.div		= _SUNXI_CCU_DIV(0, 3),
666 	.mux		= {
667 		.shift		= 24,
668 		.width		= 3,
669 		.fixed_predivs	= gpu_predivs,
670 		.n_predivs	= ARRAY_SIZE(gpu_predivs),
671 	},
672 	.common		= {
673 		.reg		= 0x1a0,
674 		.features	= CCU_FEATURE_FIXED_PREDIV,
675 		.hw.init	= CLK_HW_INIT_PARENTS("gpu-core",
676 						      gpu_parents,
677 						      &ccu_div_ops,
678 						      0),
679 	},
680 };
681 
682 static struct ccu_div gpu_memory_clk = {
683 	.enable		= BIT(31),
684 	.div		= _SUNXI_CCU_DIV(0, 3),
685 	.mux		= {
686 		.shift		= 24,
687 		.width		= 3,
688 		.fixed_predivs	= gpu_predivs,
689 		.n_predivs	= ARRAY_SIZE(gpu_predivs),
690 	},
691 	.common		= {
692 		.reg		= 0x1a4,
693 		.features	= CCU_FEATURE_FIXED_PREDIV,
694 		.hw.init	= CLK_HW_INIT_PARENTS("gpu-memory",
695 						      gpu_parents,
696 						      &ccu_div_ops,
697 						      0),
698 	},
699 };
700 
701 static struct ccu_div gpu_hyd_clk = {
702 	.enable		= BIT(31),
703 	.div		= _SUNXI_CCU_DIV(0, 3),
704 	.mux		= {
705 		.shift		= 24,
706 		.width		= 3,
707 		.fixed_predivs	= gpu_predivs,
708 		.n_predivs	= ARRAY_SIZE(gpu_predivs),
709 	},
710 	.common		= {
711 		.reg		= 0x1a8,
712 		.features	= CCU_FEATURE_FIXED_PREDIV,
713 		.hw.init	= CLK_HW_INIT_PARENTS("gpu-hyd",
714 						      gpu_parents,
715 						      &ccu_div_ops,
716 						      0),
717 	},
718 };
719 
720 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0,
721 				 0, 3,		/* M */
722 				 24, 2,		/* mux */
723 				 BIT(31),	/* gate */
724 				 0);
725 
726 static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents,
727 				 0x1b0,
728 				 0, 3,		/* M */
729 				 24, 2,		/* mux */
730 				 BIT(31),	/* gate */
731 				 0);
732 
733 static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M",
734 						"axi", "ahb1" };
735 static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 };
736 
737 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
738 	{ .index = 0, .div = 750, },
739 	{ .index = 3, .div = 4, },
740 	{ .index = 4, .div = 4, },
741 };
742 
743 static struct ccu_mp out_a_clk = {
744 	.enable		= BIT(31),
745 	.m		= _SUNXI_CCU_DIV(8, 5),
746 	.p		= _SUNXI_CCU_DIV(20, 2),
747 	.mux		= {
748 		.shift		= 24,
749 		.width		= 4,
750 		.table		= clk_out_table,
751 		.fixed_predivs	= clk_out_predivs,
752 		.n_predivs	= ARRAY_SIZE(clk_out_predivs),
753 	},
754 	.common		= {
755 		.reg		= 0x300,
756 		.features	= CCU_FEATURE_FIXED_PREDIV,
757 		.hw.init	= CLK_HW_INIT_PARENTS("out-a",
758 						      clk_out_parents,
759 						      &ccu_mp_ops,
760 						      0),
761 	},
762 };
763 
764 static struct ccu_mp out_b_clk = {
765 	.enable		= BIT(31),
766 	.m		= _SUNXI_CCU_DIV(8, 5),
767 	.p		= _SUNXI_CCU_DIV(20, 2),
768 	.mux		= {
769 		.shift		= 24,
770 		.width		= 4,
771 		.table		= clk_out_table,
772 		.fixed_predivs	= clk_out_predivs,
773 		.n_predivs	= ARRAY_SIZE(clk_out_predivs),
774 	},
775 	.common		= {
776 		.reg		= 0x304,
777 		.features	= CCU_FEATURE_FIXED_PREDIV,
778 		.hw.init	= CLK_HW_INIT_PARENTS("out-b",
779 						      clk_out_parents,
780 						      &ccu_mp_ops,
781 						      0),
782 	},
783 };
784 
785 static struct ccu_mp out_c_clk = {
786 	.enable		= BIT(31),
787 	.m		= _SUNXI_CCU_DIV(8, 5),
788 	.p		= _SUNXI_CCU_DIV(20, 2),
789 	.mux		= {
790 		.shift		= 24,
791 		.width		= 4,
792 		.table		= clk_out_table,
793 		.fixed_predivs	= clk_out_predivs,
794 		.n_predivs	= ARRAY_SIZE(clk_out_predivs),
795 	},
796 	.common		= {
797 		.reg		= 0x308,
798 		.features	= CCU_FEATURE_FIXED_PREDIV,
799 		.hw.init	= CLK_HW_INIT_PARENTS("out-c",
800 						      clk_out_parents,
801 						      &ccu_mp_ops,
802 						      0),
803 	},
804 };
805 
806 static struct ccu_common *sun6i_a31_ccu_clks[] = {
807 	&pll_cpu_clk.common,
808 	&pll_audio_base_clk.common,
809 	&pll_video0_clk.common,
810 	&pll_ve_clk.common,
811 	&pll_ddr_clk.common,
812 	&pll_periph_clk.common,
813 	&pll_video1_clk.common,
814 	&pll_gpu_clk.common,
815 	&pll_mipi_clk.common,
816 	&pll9_clk.common,
817 	&pll10_clk.common,
818 	&cpu_clk.common,
819 	&axi_clk.common,
820 	&ahb1_clk.common,
821 	&apb1_clk.common,
822 	&apb2_clk.common,
823 	&ahb1_mipidsi_clk.common,
824 	&ahb1_ss_clk.common,
825 	&ahb1_dma_clk.common,
826 	&ahb1_mmc0_clk.common,
827 	&ahb1_mmc1_clk.common,
828 	&ahb1_mmc2_clk.common,
829 	&ahb1_mmc3_clk.common,
830 	&ahb1_nand1_clk.common,
831 	&ahb1_nand0_clk.common,
832 	&ahb1_sdram_clk.common,
833 	&ahb1_emac_clk.common,
834 	&ahb1_ts_clk.common,
835 	&ahb1_hstimer_clk.common,
836 	&ahb1_spi0_clk.common,
837 	&ahb1_spi1_clk.common,
838 	&ahb1_spi2_clk.common,
839 	&ahb1_spi3_clk.common,
840 	&ahb1_otg_clk.common,
841 	&ahb1_ehci0_clk.common,
842 	&ahb1_ehci1_clk.common,
843 	&ahb1_ohci0_clk.common,
844 	&ahb1_ohci1_clk.common,
845 	&ahb1_ohci2_clk.common,
846 	&ahb1_ve_clk.common,
847 	&ahb1_lcd0_clk.common,
848 	&ahb1_lcd1_clk.common,
849 	&ahb1_csi_clk.common,
850 	&ahb1_hdmi_clk.common,
851 	&ahb1_be0_clk.common,
852 	&ahb1_be1_clk.common,
853 	&ahb1_fe0_clk.common,
854 	&ahb1_fe1_clk.common,
855 	&ahb1_mp_clk.common,
856 	&ahb1_gpu_clk.common,
857 	&ahb1_deu0_clk.common,
858 	&ahb1_deu1_clk.common,
859 	&ahb1_drc0_clk.common,
860 	&ahb1_drc1_clk.common,
861 	&apb1_codec_clk.common,
862 	&apb1_spdif_clk.common,
863 	&apb1_digital_mic_clk.common,
864 	&apb1_pio_clk.common,
865 	&apb1_daudio0_clk.common,
866 	&apb1_daudio1_clk.common,
867 	&apb2_i2c0_clk.common,
868 	&apb2_i2c1_clk.common,
869 	&apb2_i2c2_clk.common,
870 	&apb2_i2c3_clk.common,
871 	&apb2_uart0_clk.common,
872 	&apb2_uart1_clk.common,
873 	&apb2_uart2_clk.common,
874 	&apb2_uart3_clk.common,
875 	&apb2_uart4_clk.common,
876 	&apb2_uart5_clk.common,
877 	&nand0_clk.common,
878 	&nand1_clk.common,
879 	&mmc0_clk.common,
880 	&mmc0_sample_clk.common,
881 	&mmc0_output_clk.common,
882 	&mmc1_clk.common,
883 	&mmc1_sample_clk.common,
884 	&mmc1_output_clk.common,
885 	&mmc2_clk.common,
886 	&mmc2_sample_clk.common,
887 	&mmc2_output_clk.common,
888 	&mmc3_clk.common,
889 	&mmc3_sample_clk.common,
890 	&mmc3_output_clk.common,
891 	&ts_clk.common,
892 	&ss_clk.common,
893 	&spi0_clk.common,
894 	&spi1_clk.common,
895 	&spi2_clk.common,
896 	&spi3_clk.common,
897 	&daudio0_clk.common,
898 	&daudio1_clk.common,
899 	&spdif_clk.common,
900 	&usb_phy0_clk.common,
901 	&usb_phy1_clk.common,
902 	&usb_phy2_clk.common,
903 	&usb_ohci0_clk.common,
904 	&usb_ohci1_clk.common,
905 	&usb_ohci2_clk.common,
906 	&mdfs_clk.common,
907 	&sdram0_clk.common,
908 	&sdram1_clk.common,
909 	&dram_ve_clk.common,
910 	&dram_csi_isp_clk.common,
911 	&dram_ts_clk.common,
912 	&dram_drc0_clk.common,
913 	&dram_drc1_clk.common,
914 	&dram_deu0_clk.common,
915 	&dram_deu1_clk.common,
916 	&dram_fe0_clk.common,
917 	&dram_fe1_clk.common,
918 	&dram_be0_clk.common,
919 	&dram_be1_clk.common,
920 	&dram_mp_clk.common,
921 	&be0_clk.common,
922 	&be1_clk.common,
923 	&fe0_clk.common,
924 	&fe1_clk.common,
925 	&mp_clk.common,
926 	&lcd0_ch0_clk.common,
927 	&lcd1_ch0_clk.common,
928 	&lcd0_ch1_clk.common,
929 	&lcd1_ch1_clk.common,
930 	&csi0_sclk_clk.common,
931 	&csi0_mclk_clk.common,
932 	&csi1_mclk_clk.common,
933 	&ve_clk.common,
934 	&codec_clk.common,
935 	&avs_clk.common,
936 	&digital_mic_clk.common,
937 	&hdmi_clk.common,
938 	&hdmi_ddc_clk.common,
939 	&ps_clk.common,
940 	&mbus0_clk.common,
941 	&mbus1_clk.common,
942 	&mipi_dsi_clk.common,
943 	&mipi_dsi_dphy_clk.common,
944 	&mipi_csi_dphy_clk.common,
945 	&iep_drc0_clk.common,
946 	&iep_drc1_clk.common,
947 	&iep_deu0_clk.common,
948 	&iep_deu1_clk.common,
949 	&gpu_core_clk.common,
950 	&gpu_memory_clk.common,
951 	&gpu_hyd_clk.common,
952 	&ats_clk.common,
953 	&trace_clk.common,
954 	&out_a_clk.common,
955 	&out_b_clk.common,
956 	&out_c_clk.common,
957 };
958 
959 static const struct clk_hw *clk_parent_pll_audio[] = {
960 	&pll_audio_base_clk.common.hw
961 };
962 
963 /* We hardcode the divider to 1 for now */
964 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
965 			    clk_parent_pll_audio,
966 			    1, 1, CLK_SET_RATE_PARENT);
967 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
968 			    clk_parent_pll_audio,
969 			    2, 1, CLK_SET_RATE_PARENT);
970 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
971 			    clk_parent_pll_audio,
972 			    1, 1, CLK_SET_RATE_PARENT);
973 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
974 			    clk_parent_pll_audio,
975 			    1, 2, CLK_SET_RATE_PARENT);
976 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
977 			   &pll_periph_clk.common.hw,
978 			   1, 2, 0);
979 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
980 			   &pll_video0_clk.common.hw,
981 			   1, 2, CLK_SET_RATE_PARENT);
982 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
983 			   &pll_video1_clk.common.hw,
984 			   1, 2, CLK_SET_RATE_PARENT);
985 
986 static struct clk_hw_onecell_data sun6i_a31_hw_clks = {
987 	.hws	= {
988 		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
989 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
990 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
991 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
992 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
993 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
994 		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
995 		[CLK_PLL_VIDEO0_2X]	= &pll_video0_2x_clk.hw,
996 		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
997 		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
998 		[CLK_PLL_PERIPH]	= &pll_periph_clk.common.hw,
999 		[CLK_PLL_PERIPH_2X]	= &pll_periph_2x_clk.hw,
1000 		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
1001 		[CLK_PLL_VIDEO1_2X]	= &pll_video1_2x_clk.hw,
1002 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
1003 		[CLK_PLL_MIPI]		= &pll_mipi_clk.common.hw,
1004 		[CLK_PLL9]		= &pll9_clk.common.hw,
1005 		[CLK_PLL10]		= &pll10_clk.common.hw,
1006 		[CLK_CPU]		= &cpu_clk.common.hw,
1007 		[CLK_AXI]		= &axi_clk.common.hw,
1008 		[CLK_AHB1]		= &ahb1_clk.common.hw,
1009 		[CLK_APB1]		= &apb1_clk.common.hw,
1010 		[CLK_APB2]		= &apb2_clk.common.hw,
1011 		[CLK_AHB1_MIPIDSI]	= &ahb1_mipidsi_clk.common.hw,
1012 		[CLK_AHB1_SS]		= &ahb1_ss_clk.common.hw,
1013 		[CLK_AHB1_DMA]		= &ahb1_dma_clk.common.hw,
1014 		[CLK_AHB1_MMC0]		= &ahb1_mmc0_clk.common.hw,
1015 		[CLK_AHB1_MMC1]		= &ahb1_mmc1_clk.common.hw,
1016 		[CLK_AHB1_MMC2]		= &ahb1_mmc2_clk.common.hw,
1017 		[CLK_AHB1_MMC3]		= &ahb1_mmc3_clk.common.hw,
1018 		[CLK_AHB1_NAND1]	= &ahb1_nand1_clk.common.hw,
1019 		[CLK_AHB1_NAND0]	= &ahb1_nand0_clk.common.hw,
1020 		[CLK_AHB1_SDRAM]	= &ahb1_sdram_clk.common.hw,
1021 		[CLK_AHB1_EMAC]		= &ahb1_emac_clk.common.hw,
1022 		[CLK_AHB1_TS]		= &ahb1_ts_clk.common.hw,
1023 		[CLK_AHB1_HSTIMER]	= &ahb1_hstimer_clk.common.hw,
1024 		[CLK_AHB1_SPI0]		= &ahb1_spi0_clk.common.hw,
1025 		[CLK_AHB1_SPI1]		= &ahb1_spi1_clk.common.hw,
1026 		[CLK_AHB1_SPI2]		= &ahb1_spi2_clk.common.hw,
1027 		[CLK_AHB1_SPI3]		= &ahb1_spi3_clk.common.hw,
1028 		[CLK_AHB1_OTG]		= &ahb1_otg_clk.common.hw,
1029 		[CLK_AHB1_EHCI0]	= &ahb1_ehci0_clk.common.hw,
1030 		[CLK_AHB1_EHCI1]	= &ahb1_ehci1_clk.common.hw,
1031 		[CLK_AHB1_OHCI0]	= &ahb1_ohci0_clk.common.hw,
1032 		[CLK_AHB1_OHCI1]	= &ahb1_ohci1_clk.common.hw,
1033 		[CLK_AHB1_OHCI2]	= &ahb1_ohci2_clk.common.hw,
1034 		[CLK_AHB1_VE]		= &ahb1_ve_clk.common.hw,
1035 		[CLK_AHB1_LCD0]		= &ahb1_lcd0_clk.common.hw,
1036 		[CLK_AHB1_LCD1]		= &ahb1_lcd1_clk.common.hw,
1037 		[CLK_AHB1_CSI]		= &ahb1_csi_clk.common.hw,
1038 		[CLK_AHB1_HDMI]		= &ahb1_hdmi_clk.common.hw,
1039 		[CLK_AHB1_BE0]		= &ahb1_be0_clk.common.hw,
1040 		[CLK_AHB1_BE1]		= &ahb1_be1_clk.common.hw,
1041 		[CLK_AHB1_FE0]		= &ahb1_fe0_clk.common.hw,
1042 		[CLK_AHB1_FE1]		= &ahb1_fe1_clk.common.hw,
1043 		[CLK_AHB1_MP]		= &ahb1_mp_clk.common.hw,
1044 		[CLK_AHB1_GPU]		= &ahb1_gpu_clk.common.hw,
1045 		[CLK_AHB1_DEU0]		= &ahb1_deu0_clk.common.hw,
1046 		[CLK_AHB1_DEU1]		= &ahb1_deu1_clk.common.hw,
1047 		[CLK_AHB1_DRC0]		= &ahb1_drc0_clk.common.hw,
1048 		[CLK_AHB1_DRC1]		= &ahb1_drc1_clk.common.hw,
1049 		[CLK_APB1_CODEC]	= &apb1_codec_clk.common.hw,
1050 		[CLK_APB1_SPDIF]	= &apb1_spdif_clk.common.hw,
1051 		[CLK_APB1_DIGITAL_MIC]	= &apb1_digital_mic_clk.common.hw,
1052 		[CLK_APB1_PIO]		= &apb1_pio_clk.common.hw,
1053 		[CLK_APB1_DAUDIO0]	= &apb1_daudio0_clk.common.hw,
1054 		[CLK_APB1_DAUDIO1]	= &apb1_daudio1_clk.common.hw,
1055 		[CLK_APB2_I2C0]		= &apb2_i2c0_clk.common.hw,
1056 		[CLK_APB2_I2C1]		= &apb2_i2c1_clk.common.hw,
1057 		[CLK_APB2_I2C2]		= &apb2_i2c2_clk.common.hw,
1058 		[CLK_APB2_I2C3]		= &apb2_i2c3_clk.common.hw,
1059 		[CLK_APB2_UART0]	= &apb2_uart0_clk.common.hw,
1060 		[CLK_APB2_UART1]	= &apb2_uart1_clk.common.hw,
1061 		[CLK_APB2_UART2]	= &apb2_uart2_clk.common.hw,
1062 		[CLK_APB2_UART3]	= &apb2_uart3_clk.common.hw,
1063 		[CLK_APB2_UART4]	= &apb2_uart4_clk.common.hw,
1064 		[CLK_APB2_UART5]	= &apb2_uart5_clk.common.hw,
1065 		[CLK_NAND0]		= &nand0_clk.common.hw,
1066 		[CLK_NAND1]		= &nand1_clk.common.hw,
1067 		[CLK_MMC0]		= &mmc0_clk.common.hw,
1068 		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
1069 		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
1070 		[CLK_MMC1]		= &mmc1_clk.common.hw,
1071 		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
1072 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
1073 		[CLK_MMC2]		= &mmc2_clk.common.hw,
1074 		[CLK_MMC2_SAMPLE]	= &mmc2_sample_clk.common.hw,
1075 		[CLK_MMC2_OUTPUT]	= &mmc2_output_clk.common.hw,
1076 		[CLK_MMC3]		= &mmc3_clk.common.hw,
1077 		[CLK_MMC3_SAMPLE]	= &mmc3_sample_clk.common.hw,
1078 		[CLK_MMC3_OUTPUT]	= &mmc3_output_clk.common.hw,
1079 		[CLK_TS]		= &ts_clk.common.hw,
1080 		[CLK_SS]		= &ss_clk.common.hw,
1081 		[CLK_SPI0]		= &spi0_clk.common.hw,
1082 		[CLK_SPI1]		= &spi1_clk.common.hw,
1083 		[CLK_SPI2]		= &spi2_clk.common.hw,
1084 		[CLK_SPI3]		= &spi3_clk.common.hw,
1085 		[CLK_DAUDIO0]		= &daudio0_clk.common.hw,
1086 		[CLK_DAUDIO1]		= &daudio1_clk.common.hw,
1087 		[CLK_SPDIF]		= &spdif_clk.common.hw,
1088 		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
1089 		[CLK_USB_PHY1]		= &usb_phy1_clk.common.hw,
1090 		[CLK_USB_PHY2]		= &usb_phy2_clk.common.hw,
1091 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
1092 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
1093 		[CLK_USB_OHCI2]		= &usb_ohci2_clk.common.hw,
1094 		[CLK_MDFS]		= &mdfs_clk.common.hw,
1095 		[CLK_SDRAM0]		= &sdram0_clk.common.hw,
1096 		[CLK_SDRAM1]		= &sdram1_clk.common.hw,
1097 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
1098 		[CLK_DRAM_CSI_ISP]	= &dram_csi_isp_clk.common.hw,
1099 		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
1100 		[CLK_DRAM_DRC0]		= &dram_drc0_clk.common.hw,
1101 		[CLK_DRAM_DRC1]		= &dram_drc1_clk.common.hw,
1102 		[CLK_DRAM_DEU0]		= &dram_deu0_clk.common.hw,
1103 		[CLK_DRAM_DEU1]		= &dram_deu1_clk.common.hw,
1104 		[CLK_DRAM_FE0]		= &dram_fe0_clk.common.hw,
1105 		[CLK_DRAM_FE1]		= &dram_fe1_clk.common.hw,
1106 		[CLK_DRAM_BE0]		= &dram_be0_clk.common.hw,
1107 		[CLK_DRAM_BE1]		= &dram_be1_clk.common.hw,
1108 		[CLK_DRAM_MP]		= &dram_mp_clk.common.hw,
1109 		[CLK_BE0]		= &be0_clk.common.hw,
1110 		[CLK_BE1]		= &be1_clk.common.hw,
1111 		[CLK_FE0]		= &fe0_clk.common.hw,
1112 		[CLK_FE1]		= &fe1_clk.common.hw,
1113 		[CLK_MP]		= &mp_clk.common.hw,
1114 		[CLK_LCD0_CH0]		= &lcd0_ch0_clk.common.hw,
1115 		[CLK_LCD1_CH0]		= &lcd1_ch0_clk.common.hw,
1116 		[CLK_LCD0_CH1]		= &lcd0_ch1_clk.common.hw,
1117 		[CLK_LCD1_CH1]		= &lcd1_ch1_clk.common.hw,
1118 		[CLK_CSI0_SCLK]		= &csi0_sclk_clk.common.hw,
1119 		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,
1120 		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,
1121 		[CLK_VE]		= &ve_clk.common.hw,
1122 		[CLK_CODEC]		= &codec_clk.common.hw,
1123 		[CLK_AVS]		= &avs_clk.common.hw,
1124 		[CLK_DIGITAL_MIC]	= &digital_mic_clk.common.hw,
1125 		[CLK_HDMI]		= &hdmi_clk.common.hw,
1126 		[CLK_HDMI_DDC]		= &hdmi_ddc_clk.common.hw,
1127 		[CLK_PS]		= &ps_clk.common.hw,
1128 		[CLK_MBUS0]		= &mbus0_clk.common.hw,
1129 		[CLK_MBUS1]		= &mbus1_clk.common.hw,
1130 		[CLK_MIPI_DSI]		= &mipi_dsi_clk.common.hw,
1131 		[CLK_MIPI_DSI_DPHY]	= &mipi_dsi_dphy_clk.common.hw,
1132 		[CLK_MIPI_CSI_DPHY]	= &mipi_csi_dphy_clk.common.hw,
1133 		[CLK_IEP_DRC0]		= &iep_drc0_clk.common.hw,
1134 		[CLK_IEP_DRC1]		= &iep_drc1_clk.common.hw,
1135 		[CLK_IEP_DEU0]		= &iep_deu0_clk.common.hw,
1136 		[CLK_IEP_DEU1]		= &iep_deu1_clk.common.hw,
1137 		[CLK_GPU_CORE]		= &gpu_core_clk.common.hw,
1138 		[CLK_GPU_MEMORY]	= &gpu_memory_clk.common.hw,
1139 		[CLK_GPU_HYD]		= &gpu_hyd_clk.common.hw,
1140 		[CLK_ATS]		= &ats_clk.common.hw,
1141 		[CLK_TRACE]		= &trace_clk.common.hw,
1142 		[CLK_OUT_A]		= &out_a_clk.common.hw,
1143 		[CLK_OUT_B]		= &out_b_clk.common.hw,
1144 		[CLK_OUT_C]		= &out_c_clk.common.hw,
1145 	},
1146 	.num	= CLK_NUMBER,
1147 };
1148 
1149 static struct ccu_reset_map sun6i_a31_ccu_resets[] = {
1150 	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
1151 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
1152 	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
1153 
1154 	[RST_AHB1_MIPI_DSI]	= { 0x2c0, BIT(1) },
1155 	[RST_AHB1_SS]		= { 0x2c0, BIT(5) },
1156 	[RST_AHB1_DMA]		= { 0x2c0, BIT(6) },
1157 	[RST_AHB1_MMC0]		= { 0x2c0, BIT(8) },
1158 	[RST_AHB1_MMC1]		= { 0x2c0, BIT(9) },
1159 	[RST_AHB1_MMC2]		= { 0x2c0, BIT(10) },
1160 	[RST_AHB1_MMC3]		= { 0x2c0, BIT(11) },
1161 	[RST_AHB1_NAND1]	= { 0x2c0, BIT(12) },
1162 	[RST_AHB1_NAND0]	= { 0x2c0, BIT(13) },
1163 	[RST_AHB1_SDRAM]	= { 0x2c0, BIT(14) },
1164 	[RST_AHB1_EMAC]		= { 0x2c0, BIT(17) },
1165 	[RST_AHB1_TS]		= { 0x2c0, BIT(18) },
1166 	[RST_AHB1_HSTIMER]	= { 0x2c0, BIT(19) },
1167 	[RST_AHB1_SPI0]		= { 0x2c0, BIT(20) },
1168 	[RST_AHB1_SPI1]		= { 0x2c0, BIT(21) },
1169 	[RST_AHB1_SPI2]		= { 0x2c0, BIT(22) },
1170 	[RST_AHB1_SPI3]		= { 0x2c0, BIT(23) },
1171 	[RST_AHB1_OTG]		= { 0x2c0, BIT(24) },
1172 	[RST_AHB1_EHCI0]	= { 0x2c0, BIT(26) },
1173 	[RST_AHB1_EHCI1]	= { 0x2c0, BIT(27) },
1174 	[RST_AHB1_OHCI0]	= { 0x2c0, BIT(29) },
1175 	[RST_AHB1_OHCI1]	= { 0x2c0, BIT(30) },
1176 	[RST_AHB1_OHCI2]	= { 0x2c0, BIT(31) },
1177 
1178 	[RST_AHB1_VE]		= { 0x2c4, BIT(0) },
1179 	[RST_AHB1_LCD0]		= { 0x2c4, BIT(4) },
1180 	[RST_AHB1_LCD1]		= { 0x2c4, BIT(5) },
1181 	[RST_AHB1_CSI]		= { 0x2c4, BIT(8) },
1182 	[RST_AHB1_HDMI]		= { 0x2c4, BIT(11) },
1183 	[RST_AHB1_BE0]		= { 0x2c4, BIT(12) },
1184 	[RST_AHB1_BE1]		= { 0x2c4, BIT(13) },
1185 	[RST_AHB1_FE0]		= { 0x2c4, BIT(14) },
1186 	[RST_AHB1_FE1]		= { 0x2c4, BIT(15) },
1187 	[RST_AHB1_MP]		= { 0x2c4, BIT(18) },
1188 	[RST_AHB1_GPU]		= { 0x2c4, BIT(20) },
1189 	[RST_AHB1_DEU0]		= { 0x2c4, BIT(23) },
1190 	[RST_AHB1_DEU1]		= { 0x2c4, BIT(24) },
1191 	[RST_AHB1_DRC0]		= { 0x2c4, BIT(25) },
1192 	[RST_AHB1_DRC1]		= { 0x2c4, BIT(26) },
1193 	[RST_AHB1_LVDS]		= { 0x2c8, BIT(0) },
1194 
1195 	[RST_APB1_CODEC]	= { 0x2d0, BIT(0) },
1196 	[RST_APB1_SPDIF]	= { 0x2d0, BIT(1) },
1197 	[RST_APB1_DIGITAL_MIC]	= { 0x2d0, BIT(4) },
1198 	[RST_APB1_DAUDIO0]	= { 0x2d0, BIT(12) },
1199 	[RST_APB1_DAUDIO1]	= { 0x2d0, BIT(13) },
1200 
1201 	[RST_APB2_I2C0]		= { 0x2d8, BIT(0) },
1202 	[RST_APB2_I2C1]		= { 0x2d8, BIT(1) },
1203 	[RST_APB2_I2C2]		= { 0x2d8, BIT(2) },
1204 	[RST_APB2_I2C3]		= { 0x2d8, BIT(3) },
1205 	[RST_APB2_UART0]	= { 0x2d8, BIT(16) },
1206 	[RST_APB2_UART1]	= { 0x2d8, BIT(17) },
1207 	[RST_APB2_UART2]	= { 0x2d8, BIT(18) },
1208 	[RST_APB2_UART3]	= { 0x2d8, BIT(19) },
1209 	[RST_APB2_UART4]	= { 0x2d8, BIT(20) },
1210 	[RST_APB2_UART5]	= { 0x2d8, BIT(21) },
1211 };
1212 
1213 static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = {
1214 	.ccu_clks	= sun6i_a31_ccu_clks,
1215 	.num_ccu_clks	= ARRAY_SIZE(sun6i_a31_ccu_clks),
1216 
1217 	.hw_clks	= &sun6i_a31_hw_clks,
1218 
1219 	.resets		= sun6i_a31_ccu_resets,
1220 	.num_resets	= ARRAY_SIZE(sun6i_a31_ccu_resets),
1221 };
1222 
1223 static struct ccu_mux_nb sun6i_a31_cpu_nb = {
1224 	.common		= &cpu_clk.common,
1225 	.cm		= &cpu_clk.mux,
1226 	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
1227 	.bypass_index	= 1, /* index of 24 MHz oscillator */
1228 };
1229 
1230 static int sun6i_a31_ccu_probe(struct platform_device *pdev)
1231 {
1232 	void __iomem *reg;
1233 	int ret;
1234 	u32 val;
1235 
1236 	reg = devm_platform_ioremap_resource(pdev, 0);
1237 	if (IS_ERR(reg))
1238 		return PTR_ERR(reg);
1239 
1240 	/* Force the PLL-Audio-1x divider to 1 */
1241 	val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);
1242 	val &= ~GENMASK(19, 16);
1243 	writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);
1244 
1245 	/* Force PLL-MIPI to MIPI mode */
1246 	val = readl(reg + SUN6I_A31_PLL_MIPI_REG);
1247 	val &= BIT(16);
1248 	writel(val, reg + SUN6I_A31_PLL_MIPI_REG);
1249 
1250 	/* Force AHB1 to PLL6 / 3 */
1251 	val = readl(reg + SUN6I_A31_AHB1_REG);
1252 	/* set PLL6 pre-div = 3 */
1253 	val &= ~GENMASK(7, 6);
1254 	val |= 0x2 << 6;
1255 	/* select PLL6 / pre-div */
1256 	val &= ~GENMASK(13, 12);
1257 	val |= 0x3 << 12;
1258 	writel(val, reg + SUN6I_A31_AHB1_REG);
1259 
1260 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun6i_a31_ccu_desc);
1261 	if (ret)
1262 		return ret;
1263 
1264 	ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk,
1265 				  &sun6i_a31_cpu_nb);
1266 
1267 	return 0;
1268 }
1269 
1270 static const struct of_device_id sun6i_a31_ccu_ids[] = {
1271 	{ .compatible = "allwinner,sun6i-a31-ccu" },
1272 	{ }
1273 };
1274 
1275 static struct platform_driver sun6i_a31_ccu_driver = {
1276 	.probe	= sun6i_a31_ccu_probe,
1277 	.driver	= {
1278 		.name			= "sun6i-a31-ccu",
1279 		.suppress_bind_attrs	= true,
1280 		.of_match_table		= sun6i_a31_ccu_ids,
1281 	},
1282 };
1283 module_platform_driver(sun6i_a31_ccu_driver);
1284 
1285 MODULE_IMPORT_NS(SUNXI_CCU);
1286 MODULE_LICENSE("GPL");
1287