1 /* 2 * Copyright (c) 2016 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * Based on ccu-sun8i-h3.c by Maxime Ripard. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/clk-provider.h> 19 #include <linux/io.h> 20 #include <linux/of_address.h> 21 22 #include "ccu_common.h" 23 #include "ccu_reset.h" 24 25 #include "ccu_div.h" 26 #include "ccu_gate.h" 27 #include "ccu_mp.h" 28 #include "ccu_mult.h" 29 #include "ccu_mux.h" 30 #include "ccu_nk.h" 31 #include "ccu_nkm.h" 32 #include "ccu_nkmp.h" 33 #include "ccu_nm.h" 34 #include "ccu_phase.h" 35 #include "ccu_sdm.h" 36 37 #include "ccu-sun6i-a31.h" 38 39 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", 40 "osc24M", 0x000, 41 8, 5, /* N */ 42 4, 2, /* K */ 43 0, 2, /* M */ 44 BIT(31), /* gate */ 45 BIT(28), /* lock */ 46 0); 47 48 /* 49 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 50 * the base (2x, 4x and 8x), and one variable divider (the one true 51 * pll audio). 52 * 53 * With sigma-delta modulation for fractional-N on the audio PLL, 54 * we have to use specific dividers. This means the variable divider 55 * can no longer be used, as the audio codec requests the exact clock 56 * rates we support through this mechanism. So we now hard code the 57 * variable divider to 1. This means the clock rates will no longer 58 * match the clock names. 59 */ 60 #define SUN6I_A31_PLL_AUDIO_REG 0x008 61 62 static struct ccu_sdm_setting pll_audio_sdm_table[] = { 63 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 64 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 65 }; 66 67 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 68 "osc24M", 0x008, 69 8, 7, /* N */ 70 0, 5, /* M */ 71 pll_audio_sdm_table, BIT(24), 72 0x284, BIT(31), 73 BIT(31), /* gate */ 74 BIT(28), /* lock */ 75 CLK_SET_RATE_UNGATE); 76 77 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", 78 "osc24M", 0x010, 79 8, 7, /* N */ 80 0, 4, /* M */ 81 BIT(24), /* frac enable */ 82 BIT(25), /* frac select */ 83 270000000, /* frac rate 0 */ 84 297000000, /* frac rate 1 */ 85 BIT(31), /* gate */ 86 BIT(28), /* lock */ 87 CLK_SET_RATE_UNGATE); 88 89 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 90 "osc24M", 0x018, 91 8, 7, /* N */ 92 0, 4, /* M */ 93 BIT(24), /* frac enable */ 94 BIT(25), /* frac select */ 95 270000000, /* frac rate 0 */ 96 297000000, /* frac rate 1 */ 97 BIT(31), /* gate */ 98 BIT(28), /* lock */ 99 CLK_SET_RATE_UNGATE); 100 101 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr", 102 "osc24M", 0x020, 103 8, 5, /* N */ 104 4, 2, /* K */ 105 0, 2, /* M */ 106 BIT(31), /* gate */ 107 BIT(28), /* lock */ 108 CLK_SET_RATE_UNGATE); 109 110 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph", 111 "osc24M", 0x028, 112 8, 5, /* N */ 113 4, 2, /* K */ 114 BIT(31), /* gate */ 115 BIT(28), /* lock */ 116 2, /* post-div */ 117 CLK_SET_RATE_UNGATE); 118 119 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", 120 "osc24M", 0x030, 121 8, 7, /* N */ 122 0, 4, /* M */ 123 BIT(24), /* frac enable */ 124 BIT(25), /* frac select */ 125 270000000, /* frac rate 0 */ 126 297000000, /* frac rate 1 */ 127 BIT(31), /* gate */ 128 BIT(28), /* lock */ 129 CLK_SET_RATE_UNGATE); 130 131 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 132 "osc24M", 0x038, 133 8, 7, /* N */ 134 0, 4, /* M */ 135 BIT(24), /* frac enable */ 136 BIT(25), /* frac select */ 137 270000000, /* frac rate 0 */ 138 297000000, /* frac rate 1 */ 139 BIT(31), /* gate */ 140 BIT(28), /* lock */ 141 CLK_SET_RATE_UNGATE); 142 143 /* 144 * The MIPI PLL has 2 modes: "MIPI" and "HDMI". 145 * 146 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an 147 * integer / fractional clock with switchable multipliers and dividers. 148 * This is not supported here. We hardcode the PLL to MIPI mode. 149 */ 150 #define SUN6I_A31_PLL_MIPI_REG 0x040 151 152 static const char * const pll_mipi_parents[] = { "pll-video0", "pll-video1" }; 153 static SUNXI_CCU_NKM_WITH_MUX_GATE_LOCK(pll_mipi_clk, "pll-mipi", 154 pll_mipi_parents, 0x040, 155 8, 4, /* N */ 156 4, 2, /* K */ 157 0, 4, /* M */ 158 21, 0, /* mux */ 159 BIT(31) | BIT(23) | BIT(22), /* gate */ 160 BIT(28), /* lock */ 161 CLK_SET_RATE_UNGATE); 162 163 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll9_clk, "pll9", 164 "osc24M", 0x044, 165 8, 7, /* N */ 166 0, 4, /* M */ 167 BIT(24), /* frac enable */ 168 BIT(25), /* frac select */ 169 270000000, /* frac rate 0 */ 170 297000000, /* frac rate 1 */ 171 BIT(31), /* gate */ 172 BIT(28), /* lock */ 173 CLK_SET_RATE_UNGATE); 174 175 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll10_clk, "pll10", 176 "osc24M", 0x048, 177 8, 7, /* N */ 178 0, 4, /* M */ 179 BIT(24), /* frac enable */ 180 BIT(25), /* frac select */ 181 270000000, /* frac rate 0 */ 182 297000000, /* frac rate 1 */ 183 BIT(31), /* gate */ 184 BIT(28), /* lock */ 185 CLK_SET_RATE_UNGATE); 186 187 static const char * const cpux_parents[] = { "osc32k", "osc24M", 188 "pll-cpu", "pll-cpu" }; 189 static SUNXI_CCU_MUX(cpu_clk, "cpu", cpux_parents, 190 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 191 192 static struct clk_div_table axi_div_table[] = { 193 { .val = 0, .div = 1 }, 194 { .val = 1, .div = 2 }, 195 { .val = 2, .div = 3 }, 196 { .val = 3, .div = 4 }, 197 { .val = 4, .div = 4 }, 198 { .val = 5, .div = 4 }, 199 { .val = 6, .div = 4 }, 200 { .val = 7, .div = 4 }, 201 { /* Sentinel */ }, 202 }; 203 204 static SUNXI_CCU_DIV_TABLE(axi_clk, "axi", "cpu", 205 0x050, 0, 3, axi_div_table, 0); 206 207 #define SUN6I_A31_AHB1_REG 0x054 208 209 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 210 "axi", "pll-periph" }; 211 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 212 { .index = 3, .shift = 6, .width = 2 }, 213 }; 214 215 static struct ccu_div ahb1_clk = { 216 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 217 218 .mux = { 219 .shift = 12, 220 .width = 2, 221 222 .var_predivs = ahb1_predivs, 223 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 224 }, 225 226 .common = { 227 .reg = 0x054, 228 .features = CCU_FEATURE_VARIABLE_PREDIV, 229 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 230 ahb1_parents, 231 &ccu_div_ops, 232 0), 233 }, 234 }; 235 236 static struct clk_div_table apb1_div_table[] = { 237 { .val = 0, .div = 2 }, 238 { .val = 1, .div = 2 }, 239 { .val = 2, .div = 4 }, 240 { .val = 3, .div = 8 }, 241 { /* Sentinel */ }, 242 }; 243 244 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 245 0x054, 8, 2, apb1_div_table, 0); 246 247 static const char * const apb2_parents[] = { "osc32k", "osc24M", 248 "pll-periph", "pll-periph" }; 249 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 250 0, 5, /* M */ 251 16, 2, /* P */ 252 24, 2, /* mux */ 253 0); 254 255 static SUNXI_CCU_GATE(ahb1_mipidsi_clk, "ahb1-mipidsi", "ahb1", 256 0x060, BIT(1), 0); 257 static SUNXI_CCU_GATE(ahb1_ss_clk, "ahb1-ss", "ahb1", 258 0x060, BIT(5), 0); 259 static SUNXI_CCU_GATE(ahb1_dma_clk, "ahb1-dma", "ahb1", 260 0x060, BIT(6), 0); 261 static SUNXI_CCU_GATE(ahb1_mmc0_clk, "ahb1-mmc0", "ahb1", 262 0x060, BIT(8), 0); 263 static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1", 264 0x060, BIT(9), 0); 265 static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1", 266 0x060, BIT(10), 0); 267 static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1", 268 0x060, BIT(11), 0); 269 static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1", 270 0x060, BIT(12), 0); 271 static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1", 272 0x060, BIT(13), 0); 273 static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1", 274 0x060, BIT(14), 0); 275 static SUNXI_CCU_GATE(ahb1_emac_clk, "ahb1-emac", "ahb1", 276 0x060, BIT(17), 0); 277 static SUNXI_CCU_GATE(ahb1_ts_clk, "ahb1-ts", "ahb1", 278 0x060, BIT(18), 0); 279 static SUNXI_CCU_GATE(ahb1_hstimer_clk, "ahb1-hstimer", "ahb1", 280 0x060, BIT(19), 0); 281 static SUNXI_CCU_GATE(ahb1_spi0_clk, "ahb1-spi0", "ahb1", 282 0x060, BIT(20), 0); 283 static SUNXI_CCU_GATE(ahb1_spi1_clk, "ahb1-spi1", "ahb1", 284 0x060, BIT(21), 0); 285 static SUNXI_CCU_GATE(ahb1_spi2_clk, "ahb1-spi2", "ahb1", 286 0x060, BIT(22), 0); 287 static SUNXI_CCU_GATE(ahb1_spi3_clk, "ahb1-spi3", "ahb1", 288 0x060, BIT(23), 0); 289 static SUNXI_CCU_GATE(ahb1_otg_clk, "ahb1-otg", "ahb1", 290 0x060, BIT(24), 0); 291 static SUNXI_CCU_GATE(ahb1_ehci0_clk, "ahb1-ehci0", "ahb1", 292 0x060, BIT(26), 0); 293 static SUNXI_CCU_GATE(ahb1_ehci1_clk, "ahb1-ehci1", "ahb1", 294 0x060, BIT(27), 0); 295 static SUNXI_CCU_GATE(ahb1_ohci0_clk, "ahb1-ohci0", "ahb1", 296 0x060, BIT(29), 0); 297 static SUNXI_CCU_GATE(ahb1_ohci1_clk, "ahb1-ohci1", "ahb1", 298 0x060, BIT(30), 0); 299 static SUNXI_CCU_GATE(ahb1_ohci2_clk, "ahb1-ohci2", "ahb1", 300 0x060, BIT(31), 0); 301 302 static SUNXI_CCU_GATE(ahb1_ve_clk, "ahb1-ve", "ahb1", 303 0x064, BIT(0), 0); 304 static SUNXI_CCU_GATE(ahb1_lcd0_clk, "ahb1-lcd0", "ahb1", 305 0x064, BIT(4), 0); 306 static SUNXI_CCU_GATE(ahb1_lcd1_clk, "ahb1-lcd1", "ahb1", 307 0x064, BIT(5), 0); 308 static SUNXI_CCU_GATE(ahb1_csi_clk, "ahb1-csi", "ahb1", 309 0x064, BIT(8), 0); 310 static SUNXI_CCU_GATE(ahb1_hdmi_clk, "ahb1-hdmi", "ahb1", 311 0x064, BIT(11), 0); 312 static SUNXI_CCU_GATE(ahb1_be0_clk, "ahb1-be0", "ahb1", 313 0x064, BIT(12), 0); 314 static SUNXI_CCU_GATE(ahb1_be1_clk, "ahb1-be1", "ahb1", 315 0x064, BIT(13), 0); 316 static SUNXI_CCU_GATE(ahb1_fe0_clk, "ahb1-fe0", "ahb1", 317 0x064, BIT(14), 0); 318 static SUNXI_CCU_GATE(ahb1_fe1_clk, "ahb1-fe1", "ahb1", 319 0x064, BIT(15), 0); 320 static SUNXI_CCU_GATE(ahb1_mp_clk, "ahb1-mp", "ahb1", 321 0x064, BIT(18), 0); 322 static SUNXI_CCU_GATE(ahb1_gpu_clk, "ahb1-gpu", "ahb1", 323 0x064, BIT(20), 0); 324 static SUNXI_CCU_GATE(ahb1_deu0_clk, "ahb1-deu0", "ahb1", 325 0x064, BIT(23), 0); 326 static SUNXI_CCU_GATE(ahb1_deu1_clk, "ahb1-deu1", "ahb1", 327 0x064, BIT(24), 0); 328 static SUNXI_CCU_GATE(ahb1_drc0_clk, "ahb1-drc0", "ahb1", 329 0x064, BIT(25), 0); 330 static SUNXI_CCU_GATE(ahb1_drc1_clk, "ahb1-drc1", "ahb1", 331 0x064, BIT(26), 0); 332 333 static SUNXI_CCU_GATE(apb1_codec_clk, "apb1-codec", "apb1", 334 0x068, BIT(0), 0); 335 static SUNXI_CCU_GATE(apb1_spdif_clk, "apb1-spdif", "apb1", 336 0x068, BIT(1), 0); 337 static SUNXI_CCU_GATE(apb1_digital_mic_clk, "apb1-digital-mic", "apb1", 338 0x068, BIT(4), 0); 339 static SUNXI_CCU_GATE(apb1_pio_clk, "apb1-pio", "apb1", 340 0x068, BIT(5), 0); 341 static SUNXI_CCU_GATE(apb1_daudio0_clk, "apb1-daudio0", "apb1", 342 0x068, BIT(12), 0); 343 static SUNXI_CCU_GATE(apb1_daudio1_clk, "apb1-daudio1", "apb1", 344 0x068, BIT(13), 0); 345 346 static SUNXI_CCU_GATE(apb2_i2c0_clk, "apb2-i2c0", "apb2", 347 0x06c, BIT(0), 0); 348 static SUNXI_CCU_GATE(apb2_i2c1_clk, "apb2-i2c1", "apb2", 349 0x06c, BIT(1), 0); 350 static SUNXI_CCU_GATE(apb2_i2c2_clk, "apb2-i2c2", "apb2", 351 0x06c, BIT(2), 0); 352 static SUNXI_CCU_GATE(apb2_i2c3_clk, "apb2-i2c3", "apb2", 353 0x06c, BIT(3), 0); 354 static SUNXI_CCU_GATE(apb2_uart0_clk, "apb2-uart0", "apb2", 355 0x06c, BIT(16), 0); 356 static SUNXI_CCU_GATE(apb2_uart1_clk, "apb2-uart1", "apb2", 357 0x06c, BIT(17), 0); 358 static SUNXI_CCU_GATE(apb2_uart2_clk, "apb2-uart2", "apb2", 359 0x06c, BIT(18), 0); 360 static SUNXI_CCU_GATE(apb2_uart3_clk, "apb2-uart3", "apb2", 361 0x06c, BIT(19), 0); 362 static SUNXI_CCU_GATE(apb2_uart4_clk, "apb2-uart4", "apb2", 363 0x06c, BIT(20), 0); 364 static SUNXI_CCU_GATE(apb2_uart5_clk, "apb2-uart5", "apb2", 365 0x06c, BIT(21), 0); 366 367 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" }; 368 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", mod0_default_parents, 369 0x080, 370 0, 4, /* M */ 371 16, 2, /* P */ 372 24, 2, /* mux */ 373 BIT(31), /* gate */ 374 0); 375 376 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", mod0_default_parents, 377 0x084, 378 0, 4, /* M */ 379 16, 2, /* P */ 380 24, 2, /* mux */ 381 BIT(31), /* gate */ 382 0); 383 384 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 385 0x088, 386 0, 4, /* M */ 387 16, 2, /* P */ 388 24, 2, /* mux */ 389 BIT(31), /* gate */ 390 0); 391 392 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0", 393 0x088, 20, 3, 0); 394 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0", 395 0x088, 8, 3, 0); 396 397 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 398 0x08c, 399 0, 4, /* M */ 400 16, 2, /* P */ 401 24, 2, /* mux */ 402 BIT(31), /* gate */ 403 0); 404 405 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1", 406 0x08c, 20, 3, 0); 407 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1", 408 0x08c, 8, 3, 0); 409 410 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 411 0x090, 412 0, 4, /* M */ 413 16, 2, /* P */ 414 24, 2, /* mux */ 415 BIT(31), /* gate */ 416 0); 417 418 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2", 419 0x090, 20, 3, 0); 420 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2", 421 0x090, 8, 3, 0); 422 423 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 424 0x094, 425 0, 4, /* M */ 426 16, 2, /* P */ 427 24, 2, /* mux */ 428 BIT(31), /* gate */ 429 0); 430 431 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3", 432 0x094, 20, 3, 0); 433 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3", 434 0x094, 8, 3, 0); 435 436 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098, 437 0, 4, /* M */ 438 16, 2, /* P */ 439 24, 2, /* mux */ 440 BIT(31), /* gate */ 441 0); 442 443 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c, 444 0, 4, /* M */ 445 16, 2, /* P */ 446 24, 2, /* mux */ 447 BIT(31), /* gate */ 448 0); 449 450 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 451 0, 4, /* M */ 452 16, 2, /* P */ 453 24, 2, /* mux */ 454 BIT(31), /* gate */ 455 0); 456 457 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 458 0, 4, /* M */ 459 16, 2, /* P */ 460 24, 2, /* mux */ 461 BIT(31), /* gate */ 462 0); 463 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8, 464 0, 4, /* M */ 465 16, 2, /* P */ 466 24, 2, /* mux */ 467 BIT(31), /* gate */ 468 0); 469 470 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0ac, 471 0, 4, /* M */ 472 16, 2, /* P */ 473 24, 2, /* mux */ 474 BIT(31), /* gate */ 475 0); 476 477 static const char * const daudio_parents[] = { "pll-audio-8x", "pll-audio-4x", 478 "pll-audio-2x", "pll-audio" }; 479 static SUNXI_CCU_MUX_WITH_GATE(daudio0_clk, "daudio0", daudio_parents, 480 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 481 static SUNXI_CCU_MUX_WITH_GATE(daudio1_clk, "daudio1", daudio_parents, 482 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 483 484 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", daudio_parents, 485 0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 486 487 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 488 0x0cc, BIT(8), 0); 489 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 490 0x0cc, BIT(9), 0); 491 static SUNXI_CCU_GATE(usb_phy2_clk, "usb-phy2", "osc24M", 492 0x0cc, BIT(10), 0); 493 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M", 494 0x0cc, BIT(16), 0); 495 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "osc24M", 496 0x0cc, BIT(17), 0); 497 static SUNXI_CCU_GATE(usb_ohci2_clk, "usb-ohci2", "osc24M", 498 0x0cc, BIT(18), 0); 499 500 /* TODO emac clk not supported yet */ 501 502 static const char * const dram_parents[] = { "pll-ddr", "pll-periph" }; 503 static SUNXI_CCU_MP_WITH_MUX_GATE(mdfs_clk, "mdfs", dram_parents, 0x0f0, 504 0, 4, /* M */ 505 16, 2, /* P */ 506 24, 2, /* mux */ 507 BIT(31), /* gate */ 508 CLK_IS_CRITICAL); 509 510 static SUNXI_CCU_M_WITH_MUX(sdram0_clk, "sdram0", dram_parents, 511 0x0f4, 0, 4, 4, 1, CLK_IS_CRITICAL); 512 static SUNXI_CCU_M_WITH_MUX(sdram1_clk, "sdram1", dram_parents, 513 0x0f4, 8, 4, 12, 1, CLK_IS_CRITICAL); 514 515 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "mdfs", 516 0x100, BIT(0), 0); 517 static SUNXI_CCU_GATE(dram_csi_isp_clk, "dram-csi-isp", "mdfs", 518 0x100, BIT(1), 0); 519 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "mdfs", 520 0x100, BIT(3), 0); 521 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "mdfs", 522 0x100, BIT(16), 0); 523 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "mdfs", 524 0x100, BIT(17), 0); 525 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "mdfs", 526 0x100, BIT(18), 0); 527 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "mdfs", 528 0x100, BIT(19), 0); 529 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "mdfs", 530 0x100, BIT(24), 0); 531 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "mdfs", 532 0x100, BIT(25), 0); 533 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "mdfs", 534 0x100, BIT(26), 0); 535 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "mdfs", 536 0x100, BIT(27), 0); 537 static SUNXI_CCU_GATE(dram_mp_clk, "dram-mp", "mdfs", 538 0x100, BIT(28), 0); 539 540 static const char * const de_parents[] = { "pll-video0", "pll-video1", 541 "pll-periph-2x", "pll-gpu", 542 "pll9", "pll10" }; 543 static SUNXI_CCU_M_WITH_MUX_GATE(be0_clk, "be0", de_parents, 544 0x104, 0, 4, 24, 3, BIT(31), 0); 545 static SUNXI_CCU_M_WITH_MUX_GATE(be1_clk, "be1", de_parents, 546 0x108, 0, 4, 24, 3, BIT(31), 0); 547 static SUNXI_CCU_M_WITH_MUX_GATE(fe0_clk, "fe0", de_parents, 548 0x10c, 0, 4, 24, 3, BIT(31), 0); 549 static SUNXI_CCU_M_WITH_MUX_GATE(fe1_clk, "fe1", de_parents, 550 0x110, 0, 4, 24, 3, BIT(31), 0); 551 552 static const char * const mp_parents[] = { "pll-video0", "pll-video1", 553 "pll9", "pll10" }; 554 static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", mp_parents, 555 0x114, 0, 4, 24, 3, BIT(31), 0); 556 557 static const char * const lcd_ch0_parents[] = { "pll-video0", "pll-video1", 558 "pll-video0-2x", 559 "pll-video1-2x", "pll-mipi" }; 560 static SUNXI_CCU_MUX_WITH_GATE(lcd0_ch0_clk, "lcd0-ch0", lcd_ch0_parents, 561 0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT); 562 static SUNXI_CCU_MUX_WITH_GATE(lcd1_ch0_clk, "lcd1-ch0", lcd_ch0_parents, 563 0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT); 564 565 static const char * const lcd_ch1_parents[] = { "pll-video0", "pll-video1", 566 "pll-video0-2x", 567 "pll-video1-2x" }; 568 static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch1_clk, "lcd0-ch1", lcd_ch1_parents, 569 0x12c, 0, 4, 24, 3, BIT(31), 570 CLK_SET_RATE_PARENT); 571 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents, 572 0x130, 0, 4, 24, 3, BIT(31), 573 CLK_SET_RATE_PARENT); 574 575 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1", 576 "pll9", "pll10", "pll-mipi", 577 "pll-ve" }; 578 static SUNXI_CCU_M_WITH_MUX_GATE(csi0_sclk_clk, "csi0-sclk", csi_sclk_parents, 579 0x134, 16, 4, 24, 3, BIT(31), 0); 580 581 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-video1", 582 "osc24M" }; 583 static const u8 csi_mclk_table[] = { 0, 1, 5 }; 584 static struct ccu_div csi0_mclk_clk = { 585 .enable = BIT(15), 586 .div = _SUNXI_CCU_DIV(0, 4), 587 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table), 588 .common = { 589 .reg = 0x134, 590 .hw.init = CLK_HW_INIT_PARENTS("csi0-mclk", 591 csi_mclk_parents, 592 &ccu_div_ops, 593 0), 594 }, 595 }; 596 597 static struct ccu_div csi1_mclk_clk = { 598 .enable = BIT(15), 599 .div = _SUNXI_CCU_DIV(0, 4), 600 .mux = _SUNXI_CCU_MUX_TABLE(8, 3, csi_mclk_table), 601 .common = { 602 .reg = 0x138, 603 .hw.init = CLK_HW_INIT_PARENTS("csi1-mclk", 604 csi_mclk_parents, 605 &ccu_div_ops, 606 0), 607 }, 608 }; 609 610 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 611 0x13c, 16, 3, BIT(31), 0); 612 613 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 614 0x140, BIT(31), CLK_SET_RATE_PARENT); 615 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 616 0x144, BIT(31), 0); 617 static SUNXI_CCU_GATE(digital_mic_clk, "digital-mic", "pll-audio", 618 0x148, BIT(31), CLK_SET_RATE_PARENT); 619 620 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents, 621 0x150, 0, 4, 24, 2, BIT(31), 622 CLK_SET_RATE_PARENT); 623 624 static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0); 625 626 static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0); 627 628 static const char * const mbus_parents[] = { "osc24M", "pll-periph", 629 "pll-ddr" }; 630 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus0_clk, "mbus0", mbus_parents, 0x15c, 631 0, 3, /* M */ 632 16, 2, /* P */ 633 24, 2, /* mux */ 634 BIT(31), /* gate */ 635 CLK_IS_CRITICAL); 636 637 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus1_clk, "mbus1", mbus_parents, 0x160, 638 0, 3, /* M */ 639 16, 2, /* P */ 640 24, 2, /* mux */ 641 BIT(31), /* gate */ 642 CLK_IS_CRITICAL); 643 644 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_clk, "mipi-dsi", lcd_ch1_parents, 645 0x168, 16, 3, 24, 2, BIT(31), 646 CLK_SET_RATE_PARENT); 647 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_dsi_dphy_clk, "mipi-dsi-dphy", 648 lcd_ch1_parents, 0x168, 0, 3, 8, 2, 649 BIT(15), CLK_SET_RATE_PARENT); 650 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_dphy_clk, "mipi-csi-dphy", 651 lcd_ch1_parents, 0x16c, 0, 3, 8, 2, 652 BIT(15), 0); 653 654 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc0_clk, "iep-drc0", de_parents, 655 0x180, 0, 3, 24, 2, BIT(31), 0); 656 static SUNXI_CCU_M_WITH_MUX_GATE(iep_drc1_clk, "iep-drc1", de_parents, 657 0x184, 0, 3, 24, 2, BIT(31), 0); 658 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu0_clk, "iep-deu0", de_parents, 659 0x188, 0, 3, 24, 2, BIT(31), 0); 660 static SUNXI_CCU_M_WITH_MUX_GATE(iep_deu1_clk, "iep-deu1", de_parents, 661 0x18c, 0, 3, 24, 2, BIT(31), 0); 662 663 static const char * const gpu_parents[] = { "pll-gpu", "pll-periph-2x", 664 "pll-video0", "pll-video1", 665 "pll9", "pll10" }; 666 static const struct ccu_mux_fixed_prediv gpu_predivs[] = { 667 { .index = 1, .div = 3, }, 668 }; 669 670 static struct ccu_div gpu_core_clk = { 671 .enable = BIT(31), 672 .div = _SUNXI_CCU_DIV(0, 3), 673 .mux = { 674 .shift = 24, 675 .width = 3, 676 .fixed_predivs = gpu_predivs, 677 .n_predivs = ARRAY_SIZE(gpu_predivs), 678 }, 679 .common = { 680 .reg = 0x1a0, 681 .features = CCU_FEATURE_FIXED_PREDIV, 682 .hw.init = CLK_HW_INIT_PARENTS("gpu-core", 683 gpu_parents, 684 &ccu_div_ops, 685 0), 686 }, 687 }; 688 689 static struct ccu_div gpu_memory_clk = { 690 .enable = BIT(31), 691 .div = _SUNXI_CCU_DIV(0, 3), 692 .mux = { 693 .shift = 24, 694 .width = 3, 695 .fixed_predivs = gpu_predivs, 696 .n_predivs = ARRAY_SIZE(gpu_predivs), 697 }, 698 .common = { 699 .reg = 0x1a4, 700 .features = CCU_FEATURE_FIXED_PREDIV, 701 .hw.init = CLK_HW_INIT_PARENTS("gpu-memory", 702 gpu_parents, 703 &ccu_div_ops, 704 0), 705 }, 706 }; 707 708 static struct ccu_div gpu_hyd_clk = { 709 .enable = BIT(31), 710 .div = _SUNXI_CCU_DIV(0, 3), 711 .mux = { 712 .shift = 24, 713 .width = 3, 714 .fixed_predivs = gpu_predivs, 715 .n_predivs = ARRAY_SIZE(gpu_predivs), 716 }, 717 .common = { 718 .reg = 0x1a8, 719 .features = CCU_FEATURE_FIXED_PREDIV, 720 .hw.init = CLK_HW_INIT_PARENTS("gpu-hyd", 721 gpu_parents, 722 &ccu_div_ops, 723 0), 724 }, 725 }; 726 727 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", mod0_default_parents, 0x1b0, 728 0, 3, /* M */ 729 24, 2, /* mux */ 730 BIT(31), /* gate */ 731 0); 732 733 static SUNXI_CCU_M_WITH_MUX_GATE(trace_clk, "trace", mod0_default_parents, 734 0x1b0, 735 0, 3, /* M */ 736 24, 2, /* mux */ 737 BIT(31), /* gate */ 738 0); 739 740 static const char * const clk_out_parents[] = { "osc24M", "osc32k", "osc24M", 741 "axi", "ahb1" }; 742 static const u8 clk_out_table[] = { 0, 1, 2, 11, 13 }; 743 744 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = { 745 { .index = 0, .div = 750, }, 746 { .index = 3, .div = 4, }, 747 { .index = 4, .div = 4, }, 748 }; 749 750 static struct ccu_mp out_a_clk = { 751 .enable = BIT(31), 752 .m = _SUNXI_CCU_DIV(8, 5), 753 .p = _SUNXI_CCU_DIV(20, 2), 754 .mux = { 755 .shift = 24, 756 .width = 4, 757 .table = clk_out_table, 758 .fixed_predivs = clk_out_predivs, 759 .n_predivs = ARRAY_SIZE(clk_out_predivs), 760 }, 761 .common = { 762 .reg = 0x300, 763 .features = CCU_FEATURE_FIXED_PREDIV, 764 .hw.init = CLK_HW_INIT_PARENTS("out-a", 765 clk_out_parents, 766 &ccu_mp_ops, 767 0), 768 }, 769 }; 770 771 static struct ccu_mp out_b_clk = { 772 .enable = BIT(31), 773 .m = _SUNXI_CCU_DIV(8, 5), 774 .p = _SUNXI_CCU_DIV(20, 2), 775 .mux = { 776 .shift = 24, 777 .width = 4, 778 .table = clk_out_table, 779 .fixed_predivs = clk_out_predivs, 780 .n_predivs = ARRAY_SIZE(clk_out_predivs), 781 }, 782 .common = { 783 .reg = 0x304, 784 .features = CCU_FEATURE_FIXED_PREDIV, 785 .hw.init = CLK_HW_INIT_PARENTS("out-b", 786 clk_out_parents, 787 &ccu_mp_ops, 788 0), 789 }, 790 }; 791 792 static struct ccu_mp out_c_clk = { 793 .enable = BIT(31), 794 .m = _SUNXI_CCU_DIV(8, 5), 795 .p = _SUNXI_CCU_DIV(20, 2), 796 .mux = { 797 .shift = 24, 798 .width = 4, 799 .table = clk_out_table, 800 .fixed_predivs = clk_out_predivs, 801 .n_predivs = ARRAY_SIZE(clk_out_predivs), 802 }, 803 .common = { 804 .reg = 0x308, 805 .features = CCU_FEATURE_FIXED_PREDIV, 806 .hw.init = CLK_HW_INIT_PARENTS("out-c", 807 clk_out_parents, 808 &ccu_mp_ops, 809 0), 810 }, 811 }; 812 813 static struct ccu_common *sun6i_a31_ccu_clks[] = { 814 &pll_cpu_clk.common, 815 &pll_audio_base_clk.common, 816 &pll_video0_clk.common, 817 &pll_ve_clk.common, 818 &pll_ddr_clk.common, 819 &pll_periph_clk.common, 820 &pll_video1_clk.common, 821 &pll_gpu_clk.common, 822 &pll_mipi_clk.common, 823 &pll9_clk.common, 824 &pll10_clk.common, 825 &cpu_clk.common, 826 &axi_clk.common, 827 &ahb1_clk.common, 828 &apb1_clk.common, 829 &apb2_clk.common, 830 &ahb1_mipidsi_clk.common, 831 &ahb1_ss_clk.common, 832 &ahb1_dma_clk.common, 833 &ahb1_mmc0_clk.common, 834 &ahb1_mmc1_clk.common, 835 &ahb1_mmc2_clk.common, 836 &ahb1_mmc3_clk.common, 837 &ahb1_nand1_clk.common, 838 &ahb1_nand0_clk.common, 839 &ahb1_sdram_clk.common, 840 &ahb1_emac_clk.common, 841 &ahb1_ts_clk.common, 842 &ahb1_hstimer_clk.common, 843 &ahb1_spi0_clk.common, 844 &ahb1_spi1_clk.common, 845 &ahb1_spi2_clk.common, 846 &ahb1_spi3_clk.common, 847 &ahb1_otg_clk.common, 848 &ahb1_ehci0_clk.common, 849 &ahb1_ehci1_clk.common, 850 &ahb1_ohci0_clk.common, 851 &ahb1_ohci1_clk.common, 852 &ahb1_ohci2_clk.common, 853 &ahb1_ve_clk.common, 854 &ahb1_lcd0_clk.common, 855 &ahb1_lcd1_clk.common, 856 &ahb1_csi_clk.common, 857 &ahb1_hdmi_clk.common, 858 &ahb1_be0_clk.common, 859 &ahb1_be1_clk.common, 860 &ahb1_fe0_clk.common, 861 &ahb1_fe1_clk.common, 862 &ahb1_mp_clk.common, 863 &ahb1_gpu_clk.common, 864 &ahb1_deu0_clk.common, 865 &ahb1_deu1_clk.common, 866 &ahb1_drc0_clk.common, 867 &ahb1_drc1_clk.common, 868 &apb1_codec_clk.common, 869 &apb1_spdif_clk.common, 870 &apb1_digital_mic_clk.common, 871 &apb1_pio_clk.common, 872 &apb1_daudio0_clk.common, 873 &apb1_daudio1_clk.common, 874 &apb2_i2c0_clk.common, 875 &apb2_i2c1_clk.common, 876 &apb2_i2c2_clk.common, 877 &apb2_i2c3_clk.common, 878 &apb2_uart0_clk.common, 879 &apb2_uart1_clk.common, 880 &apb2_uart2_clk.common, 881 &apb2_uart3_clk.common, 882 &apb2_uart4_clk.common, 883 &apb2_uart5_clk.common, 884 &nand0_clk.common, 885 &nand1_clk.common, 886 &mmc0_clk.common, 887 &mmc0_sample_clk.common, 888 &mmc0_output_clk.common, 889 &mmc1_clk.common, 890 &mmc1_sample_clk.common, 891 &mmc1_output_clk.common, 892 &mmc2_clk.common, 893 &mmc2_sample_clk.common, 894 &mmc2_output_clk.common, 895 &mmc3_clk.common, 896 &mmc3_sample_clk.common, 897 &mmc3_output_clk.common, 898 &ts_clk.common, 899 &ss_clk.common, 900 &spi0_clk.common, 901 &spi1_clk.common, 902 &spi2_clk.common, 903 &spi3_clk.common, 904 &daudio0_clk.common, 905 &daudio1_clk.common, 906 &spdif_clk.common, 907 &usb_phy0_clk.common, 908 &usb_phy1_clk.common, 909 &usb_phy2_clk.common, 910 &usb_ohci0_clk.common, 911 &usb_ohci1_clk.common, 912 &usb_ohci2_clk.common, 913 &mdfs_clk.common, 914 &sdram0_clk.common, 915 &sdram1_clk.common, 916 &dram_ve_clk.common, 917 &dram_csi_isp_clk.common, 918 &dram_ts_clk.common, 919 &dram_drc0_clk.common, 920 &dram_drc1_clk.common, 921 &dram_deu0_clk.common, 922 &dram_deu1_clk.common, 923 &dram_fe0_clk.common, 924 &dram_fe1_clk.common, 925 &dram_be0_clk.common, 926 &dram_be1_clk.common, 927 &dram_mp_clk.common, 928 &be0_clk.common, 929 &be1_clk.common, 930 &fe0_clk.common, 931 &fe1_clk.common, 932 &mp_clk.common, 933 &lcd0_ch0_clk.common, 934 &lcd1_ch0_clk.common, 935 &lcd0_ch1_clk.common, 936 &lcd1_ch1_clk.common, 937 &csi0_sclk_clk.common, 938 &csi0_mclk_clk.common, 939 &csi1_mclk_clk.common, 940 &ve_clk.common, 941 &codec_clk.common, 942 &avs_clk.common, 943 &digital_mic_clk.common, 944 &hdmi_clk.common, 945 &hdmi_ddc_clk.common, 946 &ps_clk.common, 947 &mbus0_clk.common, 948 &mbus1_clk.common, 949 &mipi_dsi_clk.common, 950 &mipi_dsi_dphy_clk.common, 951 &mipi_csi_dphy_clk.common, 952 &iep_drc0_clk.common, 953 &iep_drc1_clk.common, 954 &iep_deu0_clk.common, 955 &iep_deu1_clk.common, 956 &gpu_core_clk.common, 957 &gpu_memory_clk.common, 958 &gpu_hyd_clk.common, 959 &ats_clk.common, 960 &trace_clk.common, 961 &out_a_clk.common, 962 &out_b_clk.common, 963 &out_c_clk.common, 964 }; 965 966 /* We hardcode the divider to 1 for now */ 967 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 968 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 969 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 970 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 971 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 972 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 973 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 974 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 975 static CLK_FIXED_FACTOR(pll_periph_2x_clk, "pll-periph-2x", 976 "pll-periph", 1, 2, 0); 977 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", 978 "pll-video0", 1, 2, CLK_SET_RATE_PARENT); 979 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x", 980 "pll-video1", 1, 2, CLK_SET_RATE_PARENT); 981 982 static struct clk_hw_onecell_data sun6i_a31_hw_clks = { 983 .hws = { 984 [CLK_PLL_CPU] = &pll_cpu_clk.common.hw, 985 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 986 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 987 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 988 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 989 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 990 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 991 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, 992 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 993 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw, 994 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw, 995 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw, 996 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 997 [CLK_PLL_VIDEO1_2X] = &pll_video1_2x_clk.hw, 998 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 999 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 1000 [CLK_PLL9] = &pll9_clk.common.hw, 1001 [CLK_PLL10] = &pll10_clk.common.hw, 1002 [CLK_CPU] = &cpu_clk.common.hw, 1003 [CLK_AXI] = &axi_clk.common.hw, 1004 [CLK_AHB1] = &ahb1_clk.common.hw, 1005 [CLK_APB1] = &apb1_clk.common.hw, 1006 [CLK_APB2] = &apb2_clk.common.hw, 1007 [CLK_AHB1_MIPIDSI] = &ahb1_mipidsi_clk.common.hw, 1008 [CLK_AHB1_SS] = &ahb1_ss_clk.common.hw, 1009 [CLK_AHB1_DMA] = &ahb1_dma_clk.common.hw, 1010 [CLK_AHB1_MMC0] = &ahb1_mmc0_clk.common.hw, 1011 [CLK_AHB1_MMC1] = &ahb1_mmc1_clk.common.hw, 1012 [CLK_AHB1_MMC2] = &ahb1_mmc2_clk.common.hw, 1013 [CLK_AHB1_MMC3] = &ahb1_mmc3_clk.common.hw, 1014 [CLK_AHB1_NAND1] = &ahb1_nand1_clk.common.hw, 1015 [CLK_AHB1_NAND0] = &ahb1_nand0_clk.common.hw, 1016 [CLK_AHB1_SDRAM] = &ahb1_sdram_clk.common.hw, 1017 [CLK_AHB1_EMAC] = &ahb1_emac_clk.common.hw, 1018 [CLK_AHB1_TS] = &ahb1_ts_clk.common.hw, 1019 [CLK_AHB1_HSTIMER] = &ahb1_hstimer_clk.common.hw, 1020 [CLK_AHB1_SPI0] = &ahb1_spi0_clk.common.hw, 1021 [CLK_AHB1_SPI1] = &ahb1_spi1_clk.common.hw, 1022 [CLK_AHB1_SPI2] = &ahb1_spi2_clk.common.hw, 1023 [CLK_AHB1_SPI3] = &ahb1_spi3_clk.common.hw, 1024 [CLK_AHB1_OTG] = &ahb1_otg_clk.common.hw, 1025 [CLK_AHB1_EHCI0] = &ahb1_ehci0_clk.common.hw, 1026 [CLK_AHB1_EHCI1] = &ahb1_ehci1_clk.common.hw, 1027 [CLK_AHB1_OHCI0] = &ahb1_ohci0_clk.common.hw, 1028 [CLK_AHB1_OHCI1] = &ahb1_ohci1_clk.common.hw, 1029 [CLK_AHB1_OHCI2] = &ahb1_ohci2_clk.common.hw, 1030 [CLK_AHB1_VE] = &ahb1_ve_clk.common.hw, 1031 [CLK_AHB1_LCD0] = &ahb1_lcd0_clk.common.hw, 1032 [CLK_AHB1_LCD1] = &ahb1_lcd1_clk.common.hw, 1033 [CLK_AHB1_CSI] = &ahb1_csi_clk.common.hw, 1034 [CLK_AHB1_HDMI] = &ahb1_hdmi_clk.common.hw, 1035 [CLK_AHB1_BE0] = &ahb1_be0_clk.common.hw, 1036 [CLK_AHB1_BE1] = &ahb1_be1_clk.common.hw, 1037 [CLK_AHB1_FE0] = &ahb1_fe0_clk.common.hw, 1038 [CLK_AHB1_FE1] = &ahb1_fe1_clk.common.hw, 1039 [CLK_AHB1_MP] = &ahb1_mp_clk.common.hw, 1040 [CLK_AHB1_GPU] = &ahb1_gpu_clk.common.hw, 1041 [CLK_AHB1_DEU0] = &ahb1_deu0_clk.common.hw, 1042 [CLK_AHB1_DEU1] = &ahb1_deu1_clk.common.hw, 1043 [CLK_AHB1_DRC0] = &ahb1_drc0_clk.common.hw, 1044 [CLK_AHB1_DRC1] = &ahb1_drc1_clk.common.hw, 1045 [CLK_APB1_CODEC] = &apb1_codec_clk.common.hw, 1046 [CLK_APB1_SPDIF] = &apb1_spdif_clk.common.hw, 1047 [CLK_APB1_DIGITAL_MIC] = &apb1_digital_mic_clk.common.hw, 1048 [CLK_APB1_PIO] = &apb1_pio_clk.common.hw, 1049 [CLK_APB1_DAUDIO0] = &apb1_daudio0_clk.common.hw, 1050 [CLK_APB1_DAUDIO1] = &apb1_daudio1_clk.common.hw, 1051 [CLK_APB2_I2C0] = &apb2_i2c0_clk.common.hw, 1052 [CLK_APB2_I2C1] = &apb2_i2c1_clk.common.hw, 1053 [CLK_APB2_I2C2] = &apb2_i2c2_clk.common.hw, 1054 [CLK_APB2_I2C3] = &apb2_i2c3_clk.common.hw, 1055 [CLK_APB2_UART0] = &apb2_uart0_clk.common.hw, 1056 [CLK_APB2_UART1] = &apb2_uart1_clk.common.hw, 1057 [CLK_APB2_UART2] = &apb2_uart2_clk.common.hw, 1058 [CLK_APB2_UART3] = &apb2_uart3_clk.common.hw, 1059 [CLK_APB2_UART4] = &apb2_uart4_clk.common.hw, 1060 [CLK_APB2_UART5] = &apb2_uart5_clk.common.hw, 1061 [CLK_NAND0] = &nand0_clk.common.hw, 1062 [CLK_NAND1] = &nand1_clk.common.hw, 1063 [CLK_MMC0] = &mmc0_clk.common.hw, 1064 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw, 1065 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw, 1066 [CLK_MMC1] = &mmc1_clk.common.hw, 1067 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw, 1068 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw, 1069 [CLK_MMC2] = &mmc2_clk.common.hw, 1070 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw, 1071 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw, 1072 [CLK_MMC3] = &mmc3_clk.common.hw, 1073 [CLK_MMC3_SAMPLE] = &mmc3_sample_clk.common.hw, 1074 [CLK_MMC3_OUTPUT] = &mmc3_output_clk.common.hw, 1075 [CLK_TS] = &ts_clk.common.hw, 1076 [CLK_SS] = &ss_clk.common.hw, 1077 [CLK_SPI0] = &spi0_clk.common.hw, 1078 [CLK_SPI1] = &spi1_clk.common.hw, 1079 [CLK_SPI2] = &spi2_clk.common.hw, 1080 [CLK_SPI3] = &spi3_clk.common.hw, 1081 [CLK_DAUDIO0] = &daudio0_clk.common.hw, 1082 [CLK_DAUDIO1] = &daudio1_clk.common.hw, 1083 [CLK_SPDIF] = &spdif_clk.common.hw, 1084 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 1085 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 1086 [CLK_USB_PHY2] = &usb_phy2_clk.common.hw, 1087 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 1088 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 1089 [CLK_USB_OHCI2] = &usb_ohci2_clk.common.hw, 1090 [CLK_MDFS] = &mdfs_clk.common.hw, 1091 [CLK_SDRAM0] = &sdram0_clk.common.hw, 1092 [CLK_SDRAM1] = &sdram1_clk.common.hw, 1093 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 1094 [CLK_DRAM_CSI_ISP] = &dram_csi_isp_clk.common.hw, 1095 [CLK_DRAM_TS] = &dram_ts_clk.common.hw, 1096 [CLK_DRAM_DRC0] = &dram_drc0_clk.common.hw, 1097 [CLK_DRAM_DRC1] = &dram_drc1_clk.common.hw, 1098 [CLK_DRAM_DEU0] = &dram_deu0_clk.common.hw, 1099 [CLK_DRAM_DEU1] = &dram_deu1_clk.common.hw, 1100 [CLK_DRAM_FE0] = &dram_fe0_clk.common.hw, 1101 [CLK_DRAM_FE1] = &dram_fe1_clk.common.hw, 1102 [CLK_DRAM_BE0] = &dram_be0_clk.common.hw, 1103 [CLK_DRAM_BE1] = &dram_be1_clk.common.hw, 1104 [CLK_DRAM_MP] = &dram_mp_clk.common.hw, 1105 [CLK_BE0] = &be0_clk.common.hw, 1106 [CLK_BE1] = &be1_clk.common.hw, 1107 [CLK_FE0] = &fe0_clk.common.hw, 1108 [CLK_FE1] = &fe1_clk.common.hw, 1109 [CLK_MP] = &mp_clk.common.hw, 1110 [CLK_LCD0_CH0] = &lcd0_ch0_clk.common.hw, 1111 [CLK_LCD1_CH0] = &lcd1_ch0_clk.common.hw, 1112 [CLK_LCD0_CH1] = &lcd0_ch1_clk.common.hw, 1113 [CLK_LCD1_CH1] = &lcd1_ch1_clk.common.hw, 1114 [CLK_CSI0_SCLK] = &csi0_sclk_clk.common.hw, 1115 [CLK_CSI0_MCLK] = &csi0_mclk_clk.common.hw, 1116 [CLK_CSI1_MCLK] = &csi1_mclk_clk.common.hw, 1117 [CLK_VE] = &ve_clk.common.hw, 1118 [CLK_CODEC] = &codec_clk.common.hw, 1119 [CLK_AVS] = &avs_clk.common.hw, 1120 [CLK_DIGITAL_MIC] = &digital_mic_clk.common.hw, 1121 [CLK_HDMI] = &hdmi_clk.common.hw, 1122 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, 1123 [CLK_PS] = &ps_clk.common.hw, 1124 [CLK_MBUS0] = &mbus0_clk.common.hw, 1125 [CLK_MBUS1] = &mbus1_clk.common.hw, 1126 [CLK_MIPI_DSI] = &mipi_dsi_clk.common.hw, 1127 [CLK_MIPI_DSI_DPHY] = &mipi_dsi_dphy_clk.common.hw, 1128 [CLK_MIPI_CSI_DPHY] = &mipi_csi_dphy_clk.common.hw, 1129 [CLK_IEP_DRC0] = &iep_drc0_clk.common.hw, 1130 [CLK_IEP_DRC1] = &iep_drc1_clk.common.hw, 1131 [CLK_IEP_DEU0] = &iep_deu0_clk.common.hw, 1132 [CLK_IEP_DEU1] = &iep_deu1_clk.common.hw, 1133 [CLK_GPU_CORE] = &gpu_core_clk.common.hw, 1134 [CLK_GPU_MEMORY] = &gpu_memory_clk.common.hw, 1135 [CLK_GPU_HYD] = &gpu_hyd_clk.common.hw, 1136 [CLK_ATS] = &ats_clk.common.hw, 1137 [CLK_TRACE] = &trace_clk.common.hw, 1138 [CLK_OUT_A] = &out_a_clk.common.hw, 1139 [CLK_OUT_B] = &out_b_clk.common.hw, 1140 [CLK_OUT_C] = &out_c_clk.common.hw, 1141 }, 1142 .num = CLK_NUMBER, 1143 }; 1144 1145 static struct ccu_reset_map sun6i_a31_ccu_resets[] = { 1146 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 1147 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 1148 [RST_USB_PHY2] = { 0x0cc, BIT(2) }, 1149 1150 [RST_AHB1_MIPI_DSI] = { 0x2c0, BIT(1) }, 1151 [RST_AHB1_SS] = { 0x2c0, BIT(5) }, 1152 [RST_AHB1_DMA] = { 0x2c0, BIT(6) }, 1153 [RST_AHB1_MMC0] = { 0x2c0, BIT(8) }, 1154 [RST_AHB1_MMC1] = { 0x2c0, BIT(9) }, 1155 [RST_AHB1_MMC2] = { 0x2c0, BIT(10) }, 1156 [RST_AHB1_MMC3] = { 0x2c0, BIT(11) }, 1157 [RST_AHB1_NAND1] = { 0x2c0, BIT(12) }, 1158 [RST_AHB1_NAND0] = { 0x2c0, BIT(13) }, 1159 [RST_AHB1_SDRAM] = { 0x2c0, BIT(14) }, 1160 [RST_AHB1_EMAC] = { 0x2c0, BIT(17) }, 1161 [RST_AHB1_TS] = { 0x2c0, BIT(18) }, 1162 [RST_AHB1_HSTIMER] = { 0x2c0, BIT(19) }, 1163 [RST_AHB1_SPI0] = { 0x2c0, BIT(20) }, 1164 [RST_AHB1_SPI1] = { 0x2c0, BIT(21) }, 1165 [RST_AHB1_SPI2] = { 0x2c0, BIT(22) }, 1166 [RST_AHB1_SPI3] = { 0x2c0, BIT(23) }, 1167 [RST_AHB1_OTG] = { 0x2c0, BIT(24) }, 1168 [RST_AHB1_EHCI0] = { 0x2c0, BIT(26) }, 1169 [RST_AHB1_EHCI1] = { 0x2c0, BIT(27) }, 1170 [RST_AHB1_OHCI0] = { 0x2c0, BIT(29) }, 1171 [RST_AHB1_OHCI1] = { 0x2c0, BIT(30) }, 1172 [RST_AHB1_OHCI2] = { 0x2c0, BIT(31) }, 1173 1174 [RST_AHB1_VE] = { 0x2c4, BIT(0) }, 1175 [RST_AHB1_LCD0] = { 0x2c4, BIT(4) }, 1176 [RST_AHB1_LCD1] = { 0x2c4, BIT(5) }, 1177 [RST_AHB1_CSI] = { 0x2c4, BIT(8) }, 1178 [RST_AHB1_HDMI] = { 0x2c4, BIT(11) }, 1179 [RST_AHB1_BE0] = { 0x2c4, BIT(12) }, 1180 [RST_AHB1_BE1] = { 0x2c4, BIT(13) }, 1181 [RST_AHB1_FE0] = { 0x2c4, BIT(14) }, 1182 [RST_AHB1_FE1] = { 0x2c4, BIT(15) }, 1183 [RST_AHB1_MP] = { 0x2c4, BIT(18) }, 1184 [RST_AHB1_GPU] = { 0x2c4, BIT(20) }, 1185 [RST_AHB1_DEU0] = { 0x2c4, BIT(23) }, 1186 [RST_AHB1_DEU1] = { 0x2c4, BIT(24) }, 1187 [RST_AHB1_DRC0] = { 0x2c4, BIT(25) }, 1188 [RST_AHB1_DRC1] = { 0x2c4, BIT(26) }, 1189 [RST_AHB1_LVDS] = { 0x2c8, BIT(0) }, 1190 1191 [RST_APB1_CODEC] = { 0x2d0, BIT(0) }, 1192 [RST_APB1_SPDIF] = { 0x2d0, BIT(1) }, 1193 [RST_APB1_DIGITAL_MIC] = { 0x2d0, BIT(4) }, 1194 [RST_APB1_DAUDIO0] = { 0x2d0, BIT(12) }, 1195 [RST_APB1_DAUDIO1] = { 0x2d0, BIT(13) }, 1196 1197 [RST_APB2_I2C0] = { 0x2d8, BIT(0) }, 1198 [RST_APB2_I2C1] = { 0x2d8, BIT(1) }, 1199 [RST_APB2_I2C2] = { 0x2d8, BIT(2) }, 1200 [RST_APB2_I2C3] = { 0x2d8, BIT(3) }, 1201 [RST_APB2_UART0] = { 0x2d8, BIT(16) }, 1202 [RST_APB2_UART1] = { 0x2d8, BIT(17) }, 1203 [RST_APB2_UART2] = { 0x2d8, BIT(18) }, 1204 [RST_APB2_UART3] = { 0x2d8, BIT(19) }, 1205 [RST_APB2_UART4] = { 0x2d8, BIT(20) }, 1206 [RST_APB2_UART5] = { 0x2d8, BIT(21) }, 1207 }; 1208 1209 static const struct sunxi_ccu_desc sun6i_a31_ccu_desc = { 1210 .ccu_clks = sun6i_a31_ccu_clks, 1211 .num_ccu_clks = ARRAY_SIZE(sun6i_a31_ccu_clks), 1212 1213 .hw_clks = &sun6i_a31_hw_clks, 1214 1215 .resets = sun6i_a31_ccu_resets, 1216 .num_resets = ARRAY_SIZE(sun6i_a31_ccu_resets), 1217 }; 1218 1219 static struct ccu_mux_nb sun6i_a31_cpu_nb = { 1220 .common = &cpu_clk.common, 1221 .cm = &cpu_clk.mux, 1222 .delay_us = 1, /* > 8 clock cycles at 24 MHz */ 1223 .bypass_index = 1, /* index of 24 MHz oscillator */ 1224 }; 1225 1226 static void __init sun6i_a31_ccu_setup(struct device_node *node) 1227 { 1228 void __iomem *reg; 1229 u32 val; 1230 1231 reg = of_io_request_and_map(node, 0, of_node_full_name(node)); 1232 if (IS_ERR(reg)) { 1233 pr_err("%pOF: Could not map the clock registers\n", node); 1234 return; 1235 } 1236 1237 /* Force the PLL-Audio-1x divider to 1 */ 1238 val = readl(reg + SUN6I_A31_PLL_AUDIO_REG); 1239 val &= ~GENMASK(19, 16); 1240 writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG); 1241 1242 /* Force PLL-MIPI to MIPI mode */ 1243 val = readl(reg + SUN6I_A31_PLL_MIPI_REG); 1244 val &= BIT(16); 1245 writel(val, reg + SUN6I_A31_PLL_MIPI_REG); 1246 1247 /* Force AHB1 to PLL6 / 3 */ 1248 val = readl(reg + SUN6I_A31_AHB1_REG); 1249 /* set PLL6 pre-div = 3 */ 1250 val &= ~GENMASK(7, 6); 1251 val |= 0x2 << 6; 1252 /* select PLL6 / pre-div */ 1253 val &= ~GENMASK(13, 12); 1254 val |= 0x3 << 12; 1255 writel(val, reg + SUN6I_A31_AHB1_REG); 1256 1257 sunxi_ccu_probe(node, reg, &sun6i_a31_ccu_desc); 1258 1259 ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, 1260 &sun6i_a31_cpu_nb); 1261 } 1262 CLK_OF_DECLARE(sun6i_a31_ccu, "allwinner,sun6i-a31-ccu", 1263 sun6i_a31_ccu_setup); 1264