1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #ifndef _CCU_SUN5I_H_ 9 #define _CCU_SUN5I_H_ 10 11 #include <dt-bindings/clock/sun5i-ccu.h> 12 #include <dt-bindings/reset/sun5i-ccu.h> 13 14 /* The HOSC is exported */ 15 #define CLK_PLL_CORE 2 16 #define CLK_PLL_AUDIO_BASE 3 17 #define CLK_PLL_AUDIO 4 18 #define CLK_PLL_AUDIO_2X 5 19 #define CLK_PLL_AUDIO_4X 6 20 #define CLK_PLL_AUDIO_8X 7 21 #define CLK_PLL_VIDEO0 8 22 23 /* The PLL_VIDEO0_2X is exported for HDMI */ 24 25 #define CLK_PLL_VE 10 26 #define CLK_PLL_DDR_BASE 11 27 #define CLK_PLL_DDR 12 28 #define CLK_PLL_DDR_OTHER 13 29 #define CLK_PLL_PERIPH 14 30 #define CLK_PLL_VIDEO1 15 31 32 /* The PLL_VIDEO1_2X is exported for HDMI */ 33 /* The CPU clock is exported */ 34 35 #define CLK_AXI 18 36 #define CLK_AHB 19 37 #define CLK_APB0 20 38 #define CLK_APB1 21 39 #define CLK_DRAM_AXI 22 40 41 /* AHB gates are exported */ 42 /* APB0 gates are exported */ 43 /* APB1 gates are exported */ 44 /* Modules clocks are exported */ 45 /* USB clocks are exported */ 46 /* GPS clock is exported */ 47 /* DRAM gates are exported */ 48 /* More display modules clocks are exported */ 49 50 #define CLK_TCON_CH1_SCLK 91 51 52 /* The rest of the module clocks are exported */ 53 54 #define CLK_NUMBER (CLK_IEP + 1) 55 56 #endif /* _CCU_SUN5I_H_ */ 57