1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6 #include <linux/clk-provider.h> 7 #include <linux/of_address.h> 8 #include <linux/platform_device.h> 9 10 #include "ccu_common.h" 11 #include "ccu_reset.h" 12 13 #include "ccu_div.h" 14 #include "ccu_gate.h" 15 #include "ccu_mp.h" 16 #include "ccu_mult.h" 17 #include "ccu_nk.h" 18 #include "ccu_nkm.h" 19 #include "ccu_nkmp.h" 20 #include "ccu_nm.h" 21 22 #include "ccu-sun50i-h6.h" 23 24 /* 25 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However 26 * P should only be used for output frequencies lower than 288 MHz. 27 * 28 * For now we can just model it as a multiplier clock, and force P to /1. 29 * 30 * The M factor is present in the register's description, but not in the 31 * frequency formula, and it's documented as "M is only used for backdoor 32 * testing", so it's not modelled and then force to 0. 33 */ 34 #define SUN50I_H6_PLL_CPUX_REG 0x000 35 static struct ccu_mult pll_cpux_clk = { 36 .enable = BIT(31), 37 .lock = BIT(28), 38 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12), 39 .common = { 40 .reg = 0x000, 41 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", 42 &ccu_mult_ops, 43 CLK_SET_RATE_UNGATE), 44 }, 45 }; 46 47 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ 48 #define SUN50I_H6_PLL_DDR0_REG 0x010 49 static struct ccu_nkmp pll_ddr0_clk = { 50 .enable = BIT(31), 51 .lock = BIT(28), 52 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 53 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 54 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 55 .common = { 56 .reg = 0x010, 57 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M", 58 &ccu_nkmp_ops, 59 CLK_SET_RATE_UNGATE), 60 }, 61 }; 62 63 #define SUN50I_H6_PLL_PERIPH0_REG 0x020 64 static struct ccu_nkmp pll_periph0_clk = { 65 .enable = BIT(31), 66 .lock = BIT(28), 67 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 68 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 69 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 70 .fixed_post_div = 4, 71 .common = { 72 .reg = 0x020, 73 .features = CCU_FEATURE_FIXED_POSTDIV, 74 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 75 &ccu_nkmp_ops, 76 CLK_SET_RATE_UNGATE), 77 }, 78 }; 79 80 #define SUN50I_H6_PLL_PERIPH1_REG 0x028 81 static struct ccu_nkmp pll_periph1_clk = { 82 .enable = BIT(31), 83 .lock = BIT(28), 84 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 85 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 86 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 87 .fixed_post_div = 4, 88 .common = { 89 .reg = 0x028, 90 .features = CCU_FEATURE_FIXED_POSTDIV, 91 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 92 &ccu_nkmp_ops, 93 CLK_SET_RATE_UNGATE), 94 }, 95 }; 96 97 #define SUN50I_H6_PLL_GPU_REG 0x030 98 static struct ccu_nkmp pll_gpu_clk = { 99 .enable = BIT(31), 100 .lock = BIT(28), 101 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 102 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 103 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 104 .common = { 105 .reg = 0x030, 106 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", 107 &ccu_nkmp_ops, 108 CLK_SET_RATE_UNGATE), 109 }, 110 }; 111 112 /* 113 * For Video PLLs, the output divider is described as "used for testing" 114 * in the user manual. So it's not modelled and forced to 0. 115 */ 116 #define SUN50I_H6_PLL_VIDEO0_REG 0x040 117 static struct ccu_nm pll_video0_clk = { 118 .enable = BIT(31), 119 .lock = BIT(28), 120 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 121 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 122 .fixed_post_div = 4, 123 .min_rate = 288000000, 124 .max_rate = 2400000000UL, 125 .common = { 126 .reg = 0x040, 127 .features = CCU_FEATURE_FIXED_POSTDIV, 128 .hw.init = CLK_HW_INIT("pll-video0", "osc24M", 129 &ccu_nm_ops, 130 CLK_SET_RATE_UNGATE), 131 }, 132 }; 133 134 #define SUN50I_H6_PLL_VIDEO1_REG 0x048 135 static struct ccu_nm pll_video1_clk = { 136 .enable = BIT(31), 137 .lock = BIT(28), 138 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 139 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 140 .fixed_post_div = 4, 141 .min_rate = 288000000, 142 .max_rate = 2400000000UL, 143 .common = { 144 .reg = 0x048, 145 .features = CCU_FEATURE_FIXED_POSTDIV, 146 .hw.init = CLK_HW_INIT("pll-video1", "osc24M", 147 &ccu_nm_ops, 148 CLK_SET_RATE_UNGATE), 149 }, 150 }; 151 152 #define SUN50I_H6_PLL_VE_REG 0x058 153 static struct ccu_nkmp pll_ve_clk = { 154 .enable = BIT(31), 155 .lock = BIT(28), 156 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 157 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 158 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 159 .common = { 160 .reg = 0x058, 161 .hw.init = CLK_HW_INIT("pll-ve", "osc24M", 162 &ccu_nkmp_ops, 163 CLK_SET_RATE_UNGATE), 164 }, 165 }; 166 167 #define SUN50I_H6_PLL_DE_REG 0x060 168 static struct ccu_nkmp pll_de_clk = { 169 .enable = BIT(31), 170 .lock = BIT(28), 171 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 172 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 173 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 174 .common = { 175 .reg = 0x060, 176 .hw.init = CLK_HW_INIT("pll-de", "osc24M", 177 &ccu_nkmp_ops, 178 CLK_SET_RATE_UNGATE), 179 }, 180 }; 181 182 #define SUN50I_H6_PLL_HSIC_REG 0x070 183 static struct ccu_nkmp pll_hsic_clk = { 184 .enable = BIT(31), 185 .lock = BIT(28), 186 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 187 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 188 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 189 .common = { 190 .reg = 0x070, 191 .hw.init = CLK_HW_INIT("pll-hsic", "osc24M", 192 &ccu_nkmp_ops, 193 CLK_SET_RATE_UNGATE), 194 }, 195 }; 196 197 /* 198 * The Audio PLL is supposed to have 3 outputs: 2 fixed factors from 199 * the base (2x and 4x), and one variable divider (the one true pll audio). 200 * 201 * We don't have any need for the variable divider for now, so we just 202 * hardcode it to match with the clock names. 203 */ 204 #define SUN50I_H6_PLL_AUDIO_REG 0x078 205 static struct ccu_nm pll_audio_base_clk = { 206 .enable = BIT(31), 207 .lock = BIT(28), 208 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 209 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 210 .common = { 211 .reg = 0x078, 212 .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M", 213 &ccu_nm_ops, 214 CLK_SET_RATE_UNGATE), 215 }, 216 }; 217 218 static const char * const cpux_parents[] = { "osc24M", "osc32k", 219 "iosc", "pll-cpux" }; 220 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 221 0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 222 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0); 223 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0); 224 225 static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k", 226 "iosc", "pll-periph0" }; 227 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", 228 psi_ahb1_ahb2_parents, 229 0x510, 230 0, 5, /* M */ 231 8, 2, /* P */ 232 24, 2, /* mux */ 233 0); 234 235 static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k", 236 "psi-ahb1-ahb2", 237 "pll-periph0" }; 238 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, 239 0, 5, /* M */ 240 8, 2, /* P */ 241 24, 2, /* mux */ 242 0); 243 244 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, 245 0, 5, /* M */ 246 8, 2, /* P */ 247 24, 2, /* mux */ 248 0); 249 250 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, 251 0, 5, /* M */ 252 8, 2, /* P */ 253 24, 2, /* mux */ 254 0); 255 256 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 257 "pll-ddr0", "pll-periph0-4x" }; 258 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540, 259 0, 3, /* M */ 260 24, 2, /* mux */ 261 BIT(31), /* gate */ 262 CLK_IS_CRITICAL); 263 264 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" }; 265 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, 266 0, 4, /* M */ 267 24, 1, /* mux */ 268 BIT(31), /* gate */ 269 0); 270 271 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2", 272 0x60c, BIT(0), 0); 273 274 static const char * const deinterlace_parents[] = { "pll-periph0", 275 "pll-periph1" }; 276 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", 277 deinterlace_parents, 278 0x620, 279 0, 4, /* M */ 280 24, 1, /* mux */ 281 BIT(31), /* gate */ 282 0); 283 284 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2", 285 0x62c, BIT(0), 0); 286 287 static const char * const gpu_parents[] = { "pll-gpu" }; 288 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, 289 0, 3, /* M */ 290 24, 1, /* mux */ 291 BIT(31), /* gate */ 292 0); 293 294 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", 295 0x67c, BIT(0), 0); 296 297 /* Also applies to EMCE */ 298 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" }; 299 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, 300 0, 4, /* M */ 301 8, 2, /* N */ 302 24, 1, /* mux */ 303 BIT(31),/* gate */ 304 0); 305 306 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2", 307 0x68c, BIT(0), 0); 308 309 static const char * const ve_parents[] = { "pll-ve" }; 310 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 311 0, 3, /* M */ 312 24, 1, /* mux */ 313 BIT(31), /* gate */ 314 0); 315 316 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", 317 0x69c, BIT(0), 0); 318 319 static SUNXI_CCU_MP_WITH_MUX_GATE(emce_clk, "emce", ce_parents, 0x6b0, 320 0, 4, /* M */ 321 8, 2, /* N */ 322 24, 1, /* mux */ 323 BIT(31),/* gate */ 324 0); 325 326 static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2", 327 0x6bc, BIT(0), 0); 328 329 static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" }; 330 static SUNXI_CCU_M_WITH_MUX_GATE(vp9_clk, "vp9", vp9_parents, 0x6c0, 331 0, 3, /* M */ 332 24, 1, /* mux */ 333 BIT(31), /* gate */ 334 0); 335 336 static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2", 337 0x6cc, BIT(0), 0); 338 339 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2", 340 0x70c, BIT(0), 0); 341 342 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2", 343 0x71c, BIT(0), 0); 344 345 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2", 346 0x72c, BIT(0), 0); 347 348 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2", 349 0x73c, BIT(0), 0); 350 351 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0); 352 353 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2", 354 0x78c, BIT(0), 0); 355 356 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 357 0x79c, BIT(0), 0); 358 359 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); 360 361 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); 362 363 static const char * const dram_parents[] = { "pll-ddr0" }; 364 static struct ccu_div dram_clk = { 365 .div = _SUNXI_CCU_DIV(0, 2), 366 .mux = _SUNXI_CCU_MUX(24, 2), 367 .common = { 368 .reg = 0x800, 369 .hw.init = CLK_HW_INIT_PARENTS("dram", 370 dram_parents, 371 &ccu_div_ops, 372 CLK_IS_CRITICAL), 373 }, 374 }; 375 376 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus", 377 0x804, BIT(0), 0); 378 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus", 379 0x804, BIT(1), 0); 380 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus", 381 0x804, BIT(2), 0); 382 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus", 383 0x804, BIT(3), 0); 384 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus", 385 0x804, BIT(5), 0); 386 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus", 387 0x804, BIT(8), 0); 388 static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus", 389 0x804, BIT(11), 0); 390 391 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2", 392 0x80c, BIT(0), CLK_IS_CRITICAL); 393 394 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0", 395 "pll-periph1", "pll-periph0-2x", 396 "pll-periph1-2x" }; 397 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810, 398 0, 4, /* M */ 399 8, 2, /* N */ 400 24, 3, /* mux */ 401 BIT(31),/* gate */ 402 0); 403 404 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814, 405 0, 4, /* M */ 406 8, 2, /* N */ 407 24, 3, /* mux */ 408 BIT(31),/* gate */ 409 0); 410 411 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); 412 413 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", 414 "pll-periph1-2x" }; 415 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 416 0, 4, /* M */ 417 8, 2, /* N */ 418 24, 2, /* mux */ 419 BIT(31), /* gate */ 420 2, /* post-div */ 421 0); 422 423 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 424 0, 4, /* M */ 425 8, 2, /* N */ 426 24, 2, /* mux */ 427 BIT(31), /* gate */ 428 2, /* post-div */ 429 0); 430 431 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 432 0, 4, /* M */ 433 8, 2, /* N */ 434 24, 2, /* mux */ 435 BIT(31), /* gate */ 436 2, /* post-div */ 437 0); 438 439 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); 440 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); 441 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0); 442 443 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0); 444 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0); 445 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0); 446 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0); 447 448 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0); 449 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0); 450 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0); 451 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0); 452 453 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0); 454 static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0); 455 456 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940, 457 0, 4, /* M */ 458 8, 2, /* N */ 459 24, 3, /* mux */ 460 BIT(31),/* gate */ 461 0); 462 463 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944, 464 0, 4, /* M */ 465 8, 2, /* N */ 466 24, 3, /* mux */ 467 BIT(31),/* gate */ 468 0); 469 470 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0); 471 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0); 472 473 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0); 474 475 static const char * const ts_parents[] = { "osc24M", "pll-periph0" }; 476 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0, 477 0, 4, /* M */ 478 8, 2, /* N */ 479 24, 1, /* mux */ 480 BIT(31),/* gate */ 481 0); 482 483 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0); 484 485 static const char * const ir_tx_parents[] = { "osc32k", "osc24M" }; 486 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0, 487 0, 4, /* M */ 488 8, 2, /* N */ 489 24, 1, /* mux */ 490 BIT(31),/* gate */ 491 0); 492 493 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0); 494 495 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0); 496 497 static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" }; 498 static struct ccu_div i2s3_clk = { 499 .enable = BIT(31), 500 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 501 .mux = _SUNXI_CCU_MUX(24, 2), 502 .common = { 503 .reg = 0xa0c, 504 .hw.init = CLK_HW_INIT_PARENTS("i2s3", 505 audio_parents, 506 &ccu_div_ops, 507 0), 508 }, 509 }; 510 511 static struct ccu_div i2s0_clk = { 512 .enable = BIT(31), 513 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 514 .mux = _SUNXI_CCU_MUX(24, 2), 515 .common = { 516 .reg = 0xa10, 517 .hw.init = CLK_HW_INIT_PARENTS("i2s0", 518 audio_parents, 519 &ccu_div_ops, 520 0), 521 }, 522 }; 523 524 static struct ccu_div i2s1_clk = { 525 .enable = BIT(31), 526 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 527 .mux = _SUNXI_CCU_MUX(24, 2), 528 .common = { 529 .reg = 0xa14, 530 .hw.init = CLK_HW_INIT_PARENTS("i2s1", 531 audio_parents, 532 &ccu_div_ops, 533 0), 534 }, 535 }; 536 537 static struct ccu_div i2s2_clk = { 538 .enable = BIT(31), 539 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 540 .mux = _SUNXI_CCU_MUX(24, 2), 541 .common = { 542 .reg = 0xa18, 543 .hw.init = CLK_HW_INIT_PARENTS("i2s2", 544 audio_parents, 545 &ccu_div_ops, 546 0), 547 }, 548 }; 549 550 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0); 551 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0); 552 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0); 553 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0); 554 555 static struct ccu_div spdif_clk = { 556 .enable = BIT(31), 557 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 558 .mux = _SUNXI_CCU_MUX(24, 2), 559 .common = { 560 .reg = 0xa20, 561 .hw.init = CLK_HW_INIT_PARENTS("spdif", 562 audio_parents, 563 &ccu_div_ops, 564 0), 565 }, 566 }; 567 568 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0); 569 570 static struct ccu_div dmic_clk = { 571 .enable = BIT(31), 572 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 573 .mux = _SUNXI_CCU_MUX(24, 2), 574 .common = { 575 .reg = 0xa40, 576 .hw.init = CLK_HW_INIT_PARENTS("dmic", 577 audio_parents, 578 &ccu_div_ops, 579 0), 580 }, 581 }; 582 583 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0); 584 585 static struct ccu_div audio_hub_clk = { 586 .enable = BIT(31), 587 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 588 .mux = _SUNXI_CCU_MUX(24, 2), 589 .common = { 590 .reg = 0xa60, 591 .hw.init = CLK_HW_INIT_PARENTS("audio-hub", 592 audio_parents, 593 &ccu_div_ops, 594 0), 595 }, 596 }; 597 598 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0); 599 600 /* 601 * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports. 602 * We will force them to 0 (12M divided from 48M). 603 */ 604 #define SUN50I_H6_USB0_CLK_REG 0xa70 605 #define SUN50I_H6_USB3_CLK_REG 0xa7c 606 607 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0); 608 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0); 609 610 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0); 611 612 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0); 613 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0); 614 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0); 615 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0); 616 617 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0); 618 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0); 619 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0); 620 static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0); 621 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0); 622 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0); 623 624 static CLK_FIXED_FACTOR(pcie_ref_100m_clk, "pcie-ref-100M", 625 "pll-periph0-4x", 24, 1, 0); 626 static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M", 627 0xab0, BIT(31), 0); 628 static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref", 629 0xab0, BIT(30), 0); 630 631 static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi", 632 "pll-periph0", 0xab4, 633 0, 4, /* M */ 634 BIT(31), /* gate */ 635 0); 636 637 static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8, 638 0, 5, /* M */ 639 BIT(31), /* gate */ 640 0); 641 642 static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2", 643 0xabc, BIT(0), 0); 644 645 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1", 646 "pll-video1-4x" }; 647 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00, 648 0, 4, /* M */ 649 24, 2, /* mux */ 650 BIT(31), /* gate */ 651 0); 652 653 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0); 654 655 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; 656 static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { 657 { .index = 1, .div = 36621 }, 658 }; 659 static struct ccu_mux hdmi_cec_clk = { 660 .enable = BIT(31), 661 662 .mux = { 663 .shift = 24, 664 .width = 2, 665 666 .fixed_predivs = hdmi_cec_predivs, 667 .n_predivs = ARRAY_SIZE(hdmi_cec_predivs), 668 }, 669 670 .common = { 671 .reg = 0xb10, 672 .features = CCU_FEATURE_VARIABLE_PREDIV, 673 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec", 674 hdmi_cec_parents, 675 &ccu_mux_ops, 676 0), 677 }, 678 }; 679 680 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0); 681 682 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3", 683 0xb5c, BIT(0), 0); 684 685 static const char * const tcon_lcd0_parents[] = { "pll-video0", 686 "pll-video0-4x", 687 "pll-video1" }; 688 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", 689 tcon_lcd0_parents, 0xb60, 690 24, 3, /* mux */ 691 BIT(31), /* gate */ 692 0); 693 694 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", 695 0xb7c, BIT(0), 0); 696 697 static const char * const tcon_tv0_parents[] = { "pll-video0", 698 "pll-video0-4x", 699 "pll-video1", 700 "pll-video1-4x" }; 701 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", 702 tcon_tv0_parents, 0xb80, 703 0, 4, /* M */ 704 8, 2, /* P */ 705 24, 3, /* mux */ 706 BIT(31), /* gate */ 707 0); 708 709 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", 710 0xb9c, BIT(0), 0); 711 712 static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0); 713 714 static const char * const csi_top_parents[] = { "pll-video0", "pll-ve", 715 "pll-periph0" }; 716 static const u8 csi_top_table[] = { 0, 2, 3 }; 717 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top", 718 csi_top_parents, csi_top_table, 0xc04, 719 0, 4, /* M */ 720 24, 3, /* mux */ 721 BIT(31), /* gate */ 722 0); 723 724 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0", 725 "pll-periph0", "pll-periph1" }; 726 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", 727 csi_mclk_parents, 0xc08, 728 0, 5, /* M */ 729 24, 3, /* mux */ 730 BIT(31), /* gate */ 731 0); 732 733 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0); 734 735 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" }; 736 static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40, 737 0, 4, /* M */ 738 24, 2, /* mux */ 739 BIT(31), /* gate */ 740 0); 741 742 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0); 743 744 /* Fixed factor clocks */ 745 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0); 746 747 /* 748 * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a 749 * fixed post-divider 2. 750 */ 751 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 752 "pll-audio-base", 8, 1, CLK_SET_RATE_PARENT); 753 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 754 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 755 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 756 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 757 758 static CLK_FIXED_FACTOR(pll_periph0_4x_clk, "pll-periph0-4x", 759 "pll-periph0", 1, 4, 0); 760 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", 761 "pll-periph0", 1, 2, 0); 762 763 static CLK_FIXED_FACTOR(pll_periph1_4x_clk, "pll-periph1-4x", 764 "pll-periph1", 1, 4, 0); 765 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", 766 "pll-periph1", 1, 2, 0); 767 768 static CLK_FIXED_FACTOR(pll_video0_4x_clk, "pll-video0-4x", 769 "pll-video0", 1, 4, CLK_SET_RATE_PARENT); 770 771 static CLK_FIXED_FACTOR(pll_video1_4x_clk, "pll-video1-4x", 772 "pll-video1", 1, 4, CLK_SET_RATE_PARENT); 773 774 static struct ccu_common *sun50i_h6_ccu_clks[] = { 775 &pll_cpux_clk.common, 776 &pll_ddr0_clk.common, 777 &pll_periph0_clk.common, 778 &pll_periph1_clk.common, 779 &pll_gpu_clk.common, 780 &pll_video0_clk.common, 781 &pll_video1_clk.common, 782 &pll_ve_clk.common, 783 &pll_de_clk.common, 784 &pll_hsic_clk.common, 785 &pll_audio_base_clk.common, 786 &cpux_clk.common, 787 &axi_clk.common, 788 &cpux_apb_clk.common, 789 &psi_ahb1_ahb2_clk.common, 790 &ahb3_clk.common, 791 &apb1_clk.common, 792 &apb2_clk.common, 793 &mbus_clk.common, 794 &de_clk.common, 795 &bus_de_clk.common, 796 &deinterlace_clk.common, 797 &bus_deinterlace_clk.common, 798 &gpu_clk.common, 799 &bus_gpu_clk.common, 800 &ce_clk.common, 801 &bus_ce_clk.common, 802 &ve_clk.common, 803 &bus_ve_clk.common, 804 &emce_clk.common, 805 &bus_emce_clk.common, 806 &vp9_clk.common, 807 &bus_vp9_clk.common, 808 &bus_dma_clk.common, 809 &bus_msgbox_clk.common, 810 &bus_spinlock_clk.common, 811 &bus_hstimer_clk.common, 812 &avs_clk.common, 813 &bus_dbg_clk.common, 814 &bus_psi_clk.common, 815 &bus_pwm_clk.common, 816 &bus_iommu_clk.common, 817 &dram_clk.common, 818 &mbus_dma_clk.common, 819 &mbus_ve_clk.common, 820 &mbus_ce_clk.common, 821 &mbus_ts_clk.common, 822 &mbus_nand_clk.common, 823 &mbus_csi_clk.common, 824 &mbus_deinterlace_clk.common, 825 &bus_dram_clk.common, 826 &nand0_clk.common, 827 &nand1_clk.common, 828 &bus_nand_clk.common, 829 &mmc0_clk.common, 830 &mmc1_clk.common, 831 &mmc2_clk.common, 832 &bus_mmc0_clk.common, 833 &bus_mmc1_clk.common, 834 &bus_mmc2_clk.common, 835 &bus_uart0_clk.common, 836 &bus_uart1_clk.common, 837 &bus_uart2_clk.common, 838 &bus_uart3_clk.common, 839 &bus_i2c0_clk.common, 840 &bus_i2c1_clk.common, 841 &bus_i2c2_clk.common, 842 &bus_i2c3_clk.common, 843 &bus_scr0_clk.common, 844 &bus_scr1_clk.common, 845 &spi0_clk.common, 846 &spi1_clk.common, 847 &bus_spi0_clk.common, 848 &bus_spi1_clk.common, 849 &bus_emac_clk.common, 850 &ts_clk.common, 851 &bus_ts_clk.common, 852 &ir_tx_clk.common, 853 &bus_ir_tx_clk.common, 854 &bus_ths_clk.common, 855 &i2s3_clk.common, 856 &i2s0_clk.common, 857 &i2s1_clk.common, 858 &i2s2_clk.common, 859 &bus_i2s0_clk.common, 860 &bus_i2s1_clk.common, 861 &bus_i2s2_clk.common, 862 &bus_i2s3_clk.common, 863 &spdif_clk.common, 864 &bus_spdif_clk.common, 865 &dmic_clk.common, 866 &bus_dmic_clk.common, 867 &audio_hub_clk.common, 868 &bus_audio_hub_clk.common, 869 &usb_ohci0_clk.common, 870 &usb_phy0_clk.common, 871 &usb_phy1_clk.common, 872 &usb_ohci3_clk.common, 873 &usb_phy3_clk.common, 874 &usb_hsic_12m_clk.common, 875 &usb_hsic_clk.common, 876 &bus_ohci0_clk.common, 877 &bus_ohci3_clk.common, 878 &bus_ehci0_clk.common, 879 &bus_xhci_clk.common, 880 &bus_ehci3_clk.common, 881 &bus_otg_clk.common, 882 &pcie_ref_clk.common, 883 &pcie_ref_out_clk.common, 884 &pcie_maxi_clk.common, 885 &pcie_aux_clk.common, 886 &bus_pcie_clk.common, 887 &hdmi_clk.common, 888 &hdmi_slow_clk.common, 889 &hdmi_cec_clk.common, 890 &bus_hdmi_clk.common, 891 &bus_tcon_top_clk.common, 892 &tcon_lcd0_clk.common, 893 &bus_tcon_lcd0_clk.common, 894 &tcon_tv0_clk.common, 895 &bus_tcon_tv0_clk.common, 896 &csi_cci_clk.common, 897 &csi_top_clk.common, 898 &csi_mclk_clk.common, 899 &bus_csi_clk.common, 900 &hdcp_clk.common, 901 &bus_hdcp_clk.common, 902 }; 903 904 static struct clk_hw_onecell_data sun50i_h6_hw_clks = { 905 .hws = { 906 [CLK_OSC12M] = &osc12M_clk.hw, 907 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 908 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 909 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 910 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 911 [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.hw, 912 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 913 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 914 [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.hw, 915 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 916 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 917 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw, 918 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 919 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw, 920 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 921 [CLK_PLL_DE] = &pll_de_clk.common.hw, 922 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 923 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 924 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 925 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 926 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 927 [CLK_CPUX] = &cpux_clk.common.hw, 928 [CLK_AXI] = &axi_clk.common.hw, 929 [CLK_CPUX_APB] = &cpux_apb_clk.common.hw, 930 [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw, 931 [CLK_AHB3] = &ahb3_clk.common.hw, 932 [CLK_APB1] = &apb1_clk.common.hw, 933 [CLK_APB2] = &apb2_clk.common.hw, 934 [CLK_MBUS] = &mbus_clk.common.hw, 935 [CLK_DE] = &de_clk.common.hw, 936 [CLK_BUS_DE] = &bus_de_clk.common.hw, 937 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 938 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 939 [CLK_GPU] = &gpu_clk.common.hw, 940 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 941 [CLK_CE] = &ce_clk.common.hw, 942 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 943 [CLK_VE] = &ve_clk.common.hw, 944 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 945 [CLK_EMCE] = &emce_clk.common.hw, 946 [CLK_BUS_EMCE] = &bus_emce_clk.common.hw, 947 [CLK_VP9] = &vp9_clk.common.hw, 948 [CLK_BUS_VP9] = &bus_vp9_clk.common.hw, 949 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 950 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 951 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 952 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 953 [CLK_AVS] = &avs_clk.common.hw, 954 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 955 [CLK_BUS_PSI] = &bus_psi_clk.common.hw, 956 [CLK_BUS_PWM] = &bus_pwm_clk.common.hw, 957 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw, 958 [CLK_DRAM] = &dram_clk.common.hw, 959 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw, 960 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw, 961 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw, 962 [CLK_MBUS_TS] = &mbus_ts_clk.common.hw, 963 [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw, 964 [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw, 965 [CLK_MBUS_DEINTERLACE] = &mbus_deinterlace_clk.common.hw, 966 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 967 [CLK_NAND0] = &nand0_clk.common.hw, 968 [CLK_NAND1] = &nand1_clk.common.hw, 969 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 970 [CLK_MMC0] = &mmc0_clk.common.hw, 971 [CLK_MMC1] = &mmc1_clk.common.hw, 972 [CLK_MMC2] = &mmc2_clk.common.hw, 973 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 974 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 975 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 976 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 977 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 978 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 979 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 980 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 981 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 982 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 983 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 984 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw, 985 [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw, 986 [CLK_SPI0] = &spi0_clk.common.hw, 987 [CLK_SPI1] = &spi1_clk.common.hw, 988 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 989 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 990 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 991 [CLK_TS] = &ts_clk.common.hw, 992 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 993 [CLK_IR_TX] = &ir_tx_clk.common.hw, 994 [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw, 995 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 996 [CLK_I2S3] = &i2s3_clk.common.hw, 997 [CLK_I2S0] = &i2s0_clk.common.hw, 998 [CLK_I2S1] = &i2s1_clk.common.hw, 999 [CLK_I2S2] = &i2s2_clk.common.hw, 1000 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 1001 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 1002 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 1003 [CLK_BUS_I2S3] = &bus_i2s3_clk.common.hw, 1004 [CLK_SPDIF] = &spdif_clk.common.hw, 1005 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 1006 [CLK_DMIC] = &dmic_clk.common.hw, 1007 [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw, 1008 [CLK_AUDIO_HUB] = &audio_hub_clk.common.hw, 1009 [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw, 1010 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 1011 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 1012 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 1013 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw, 1014 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw, 1015 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, 1016 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 1017 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 1018 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw, 1019 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 1020 [CLK_BUS_XHCI] = &bus_xhci_clk.common.hw, 1021 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw, 1022 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 1023 [CLK_PCIE_REF_100M] = &pcie_ref_100m_clk.hw, 1024 [CLK_PCIE_REF] = &pcie_ref_clk.common.hw, 1025 [CLK_PCIE_REF_OUT] = &pcie_ref_out_clk.common.hw, 1026 [CLK_PCIE_MAXI] = &pcie_maxi_clk.common.hw, 1027 [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw, 1028 [CLK_BUS_PCIE] = &bus_pcie_clk.common.hw, 1029 [CLK_HDMI] = &hdmi_clk.common.hw, 1030 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 1031 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, 1032 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 1033 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw, 1034 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, 1035 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, 1036 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw, 1037 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, 1038 [CLK_CSI_CCI] = &csi_cci_clk.common.hw, 1039 [CLK_CSI_TOP] = &csi_top_clk.common.hw, 1040 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 1041 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 1042 [CLK_HDCP] = &hdcp_clk.common.hw, 1043 [CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw, 1044 }, 1045 .num = CLK_NUMBER, 1046 }; 1047 1048 static struct ccu_reset_map sun50i_h6_ccu_resets[] = { 1049 [RST_MBUS] = { 0x540, BIT(30) }, 1050 1051 [RST_BUS_DE] = { 0x60c, BIT(16) }, 1052 [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) }, 1053 [RST_BUS_GPU] = { 0x67c, BIT(16) }, 1054 [RST_BUS_CE] = { 0x68c, BIT(16) }, 1055 [RST_BUS_VE] = { 0x69c, BIT(16) }, 1056 [RST_BUS_EMCE] = { 0x6bc, BIT(16) }, 1057 [RST_BUS_VP9] = { 0x6cc, BIT(16) }, 1058 [RST_BUS_DMA] = { 0x70c, BIT(16) }, 1059 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) }, 1060 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) }, 1061 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) }, 1062 [RST_BUS_DBG] = { 0x78c, BIT(16) }, 1063 [RST_BUS_PSI] = { 0x79c, BIT(16) }, 1064 [RST_BUS_PWM] = { 0x7ac, BIT(16) }, 1065 [RST_BUS_IOMMU] = { 0x7bc, BIT(16) }, 1066 [RST_BUS_DRAM] = { 0x80c, BIT(16) }, 1067 [RST_BUS_NAND] = { 0x82c, BIT(16) }, 1068 [RST_BUS_MMC0] = { 0x84c, BIT(16) }, 1069 [RST_BUS_MMC1] = { 0x84c, BIT(17) }, 1070 [RST_BUS_MMC2] = { 0x84c, BIT(18) }, 1071 [RST_BUS_UART0] = { 0x90c, BIT(16) }, 1072 [RST_BUS_UART1] = { 0x90c, BIT(17) }, 1073 [RST_BUS_UART2] = { 0x90c, BIT(18) }, 1074 [RST_BUS_UART3] = { 0x90c, BIT(19) }, 1075 [RST_BUS_I2C0] = { 0x91c, BIT(16) }, 1076 [RST_BUS_I2C1] = { 0x91c, BIT(17) }, 1077 [RST_BUS_I2C2] = { 0x91c, BIT(18) }, 1078 [RST_BUS_I2C3] = { 0x91c, BIT(19) }, 1079 [RST_BUS_SCR0] = { 0x93c, BIT(16) }, 1080 [RST_BUS_SCR1] = { 0x93c, BIT(17) }, 1081 [RST_BUS_SPI0] = { 0x96c, BIT(16) }, 1082 [RST_BUS_SPI1] = { 0x96c, BIT(17) }, 1083 [RST_BUS_EMAC] = { 0x97c, BIT(16) }, 1084 [RST_BUS_TS] = { 0x9bc, BIT(16) }, 1085 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) }, 1086 [RST_BUS_THS] = { 0x9fc, BIT(16) }, 1087 [RST_BUS_I2S0] = { 0xa1c, BIT(16) }, 1088 [RST_BUS_I2S1] = { 0xa1c, BIT(17) }, 1089 [RST_BUS_I2S2] = { 0xa1c, BIT(18) }, 1090 [RST_BUS_I2S3] = { 0xa1c, BIT(19) }, 1091 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) }, 1092 [RST_BUS_DMIC] = { 0xa4c, BIT(16) }, 1093 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) }, 1094 1095 [RST_USB_PHY0] = { 0xa70, BIT(30) }, 1096 [RST_USB_PHY1] = { 0xa74, BIT(30) }, 1097 [RST_USB_PHY3] = { 0xa7c, BIT(30) }, 1098 [RST_USB_HSIC] = { 0xa7c, BIT(28) }, 1099 1100 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) }, 1101 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) }, 1102 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) }, 1103 [RST_BUS_XHCI] = { 0xa8c, BIT(21) }, 1104 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) }, 1105 [RST_BUS_OTG] = { 0xa8c, BIT(24) }, 1106 [RST_BUS_PCIE] = { 0xabc, BIT(16) }, 1107 1108 [RST_PCIE_POWERUP] = { 0xabc, BIT(17) }, 1109 1110 [RST_BUS_HDMI] = { 0xb1c, BIT(16) }, 1111 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) }, 1112 [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) }, 1113 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) }, 1114 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) }, 1115 [RST_BUS_CSI] = { 0xc2c, BIT(16) }, 1116 [RST_BUS_HDCP] = { 0xc4c, BIT(16) }, 1117 }; 1118 1119 static const struct sunxi_ccu_desc sun50i_h6_ccu_desc = { 1120 .ccu_clks = sun50i_h6_ccu_clks, 1121 .num_ccu_clks = ARRAY_SIZE(sun50i_h6_ccu_clks), 1122 1123 .hw_clks = &sun50i_h6_hw_clks, 1124 1125 .resets = sun50i_h6_ccu_resets, 1126 .num_resets = ARRAY_SIZE(sun50i_h6_ccu_resets), 1127 }; 1128 1129 static const u32 pll_regs[] = { 1130 SUN50I_H6_PLL_CPUX_REG, 1131 SUN50I_H6_PLL_DDR0_REG, 1132 SUN50I_H6_PLL_PERIPH0_REG, 1133 SUN50I_H6_PLL_PERIPH1_REG, 1134 SUN50I_H6_PLL_GPU_REG, 1135 SUN50I_H6_PLL_VIDEO0_REG, 1136 SUN50I_H6_PLL_VIDEO1_REG, 1137 SUN50I_H6_PLL_VE_REG, 1138 SUN50I_H6_PLL_DE_REG, 1139 SUN50I_H6_PLL_HSIC_REG, 1140 SUN50I_H6_PLL_AUDIO_REG, 1141 }; 1142 1143 static const u32 pll_video_regs[] = { 1144 SUN50I_H6_PLL_VIDEO0_REG, 1145 SUN50I_H6_PLL_VIDEO1_REG, 1146 }; 1147 1148 static const u32 usb2_clk_regs[] = { 1149 SUN50I_H6_USB0_CLK_REG, 1150 SUN50I_H6_USB3_CLK_REG, 1151 }; 1152 1153 static int sun50i_h6_ccu_probe(struct platform_device *pdev) 1154 { 1155 struct resource *res; 1156 void __iomem *reg; 1157 u32 val; 1158 int i; 1159 1160 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1161 reg = devm_ioremap_resource(&pdev->dev, res); 1162 if (IS_ERR(reg)) 1163 return PTR_ERR(reg); 1164 1165 /* Enable the lock bits on all PLLs */ 1166 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { 1167 val = readl(reg + pll_regs[i]); 1168 val |= BIT(29); 1169 writel(val, reg + pll_regs[i]); 1170 } 1171 1172 /* 1173 * Force the output divider of video PLLs to 0. 1174 * 1175 * See the comment before pll-video0 definition for the reason. 1176 */ 1177 for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) { 1178 val = readl(reg + pll_video_regs[i]); 1179 val &= ~BIT(0); 1180 writel(val, reg + pll_video_regs[i]); 1181 } 1182 1183 /* 1184 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) 1185 * 1186 * This clock mux is still mysterious, and the code just enforces 1187 * it to have a valid clock parent. 1188 */ 1189 for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) { 1190 val = readl(reg + usb2_clk_regs[i]); 1191 val &= ~GENMASK(25, 24); 1192 writel (val, reg + usb2_clk_regs[i]); 1193 } 1194 1195 /* 1196 * Force the post-divider of pll-audio to 8 and the output divider 1197 * of it to 1, to make the clock name represents the real frequency. 1198 */ 1199 val = readl(reg + SUN50I_H6_PLL_AUDIO_REG); 1200 val &= ~(GENMASK(21, 16) | BIT(0)); 1201 writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG); 1202 1203 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc); 1204 } 1205 1206 static const struct of_device_id sun50i_h6_ccu_ids[] = { 1207 { .compatible = "allwinner,sun50i-h6-ccu" }, 1208 { } 1209 }; 1210 1211 static struct platform_driver sun50i_h6_ccu_driver = { 1212 .probe = sun50i_h6_ccu_probe, 1213 .driver = { 1214 .name = "sun50i-h6-ccu", 1215 .of_match_table = sun50i_h6_ccu_ids, 1216 }, 1217 }; 1218 builtin_platform_driver(sun50i_h6_ccu_driver); 1219