1524353eaSIcenowy Zheng // SPDX-License-Identifier: GPL-2.0 2524353eaSIcenowy Zheng /* 3524353eaSIcenowy Zheng * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io> 4524353eaSIcenowy Zheng */ 5524353eaSIcenowy Zheng 6524353eaSIcenowy Zheng #include <linux/clk-provider.h> 762e59c4eSStephen Boyd #include <linux/io.h> 8524353eaSIcenowy Zheng #include <linux/of_address.h> 9524353eaSIcenowy Zheng #include <linux/platform_device.h> 10524353eaSIcenowy Zheng 11524353eaSIcenowy Zheng #include "ccu_common.h" 12524353eaSIcenowy Zheng #include "ccu_reset.h" 13524353eaSIcenowy Zheng 14524353eaSIcenowy Zheng #include "ccu_div.h" 15524353eaSIcenowy Zheng #include "ccu_gate.h" 16524353eaSIcenowy Zheng #include "ccu_mp.h" 17524353eaSIcenowy Zheng #include "ccu_mult.h" 18524353eaSIcenowy Zheng #include "ccu_nk.h" 19524353eaSIcenowy Zheng #include "ccu_nkm.h" 20524353eaSIcenowy Zheng #include "ccu_nkmp.h" 21524353eaSIcenowy Zheng #include "ccu_nm.h" 22524353eaSIcenowy Zheng 23524353eaSIcenowy Zheng #include "ccu-sun50i-h6.h" 24524353eaSIcenowy Zheng 25524353eaSIcenowy Zheng /* 26524353eaSIcenowy Zheng * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However 27524353eaSIcenowy Zheng * P should only be used for output frequencies lower than 288 MHz. 28524353eaSIcenowy Zheng * 29524353eaSIcenowy Zheng * For now we can just model it as a multiplier clock, and force P to /1. 30524353eaSIcenowy Zheng * 31524353eaSIcenowy Zheng * The M factor is present in the register's description, but not in the 32524353eaSIcenowy Zheng * frequency formula, and it's documented as "M is only used for backdoor 33524353eaSIcenowy Zheng * testing", so it's not modelled and then force to 0. 34524353eaSIcenowy Zheng */ 35524353eaSIcenowy Zheng #define SUN50I_H6_PLL_CPUX_REG 0x000 36524353eaSIcenowy Zheng static struct ccu_mult pll_cpux_clk = { 37524353eaSIcenowy Zheng .enable = BIT(31), 38524353eaSIcenowy Zheng .lock = BIT(28), 39524353eaSIcenowy Zheng .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12), 40524353eaSIcenowy Zheng .common = { 41524353eaSIcenowy Zheng .reg = 0x000, 42524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-cpux", "osc24M", 43524353eaSIcenowy Zheng &ccu_mult_ops, 44524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 45524353eaSIcenowy Zheng }, 46524353eaSIcenowy Zheng }; 47524353eaSIcenowy Zheng 48524353eaSIcenowy Zheng /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */ 49524353eaSIcenowy Zheng #define SUN50I_H6_PLL_DDR0_REG 0x010 50524353eaSIcenowy Zheng static struct ccu_nkmp pll_ddr0_clk = { 51524353eaSIcenowy Zheng .enable = BIT(31), 52524353eaSIcenowy Zheng .lock = BIT(28), 53524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 54524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 55524353eaSIcenowy Zheng .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 56524353eaSIcenowy Zheng .common = { 57524353eaSIcenowy Zheng .reg = 0x010, 58524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M", 59524353eaSIcenowy Zheng &ccu_nkmp_ops, 60524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 61524353eaSIcenowy Zheng }, 62524353eaSIcenowy Zheng }; 63524353eaSIcenowy Zheng 64524353eaSIcenowy Zheng #define SUN50I_H6_PLL_PERIPH0_REG 0x020 65524353eaSIcenowy Zheng static struct ccu_nkmp pll_periph0_clk = { 66524353eaSIcenowy Zheng .enable = BIT(31), 67524353eaSIcenowy Zheng .lock = BIT(28), 68524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 69524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 70524353eaSIcenowy Zheng .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 71524353eaSIcenowy Zheng .fixed_post_div = 4, 72524353eaSIcenowy Zheng .common = { 73524353eaSIcenowy Zheng .reg = 0x020, 74524353eaSIcenowy Zheng .features = CCU_FEATURE_FIXED_POSTDIV, 75524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 76524353eaSIcenowy Zheng &ccu_nkmp_ops, 77524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 78524353eaSIcenowy Zheng }, 79524353eaSIcenowy Zheng }; 80524353eaSIcenowy Zheng 81524353eaSIcenowy Zheng #define SUN50I_H6_PLL_PERIPH1_REG 0x028 82524353eaSIcenowy Zheng static struct ccu_nkmp pll_periph1_clk = { 83524353eaSIcenowy Zheng .enable = BIT(31), 84524353eaSIcenowy Zheng .lock = BIT(28), 85524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 86524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 87524353eaSIcenowy Zheng .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 88524353eaSIcenowy Zheng .fixed_post_div = 4, 89524353eaSIcenowy Zheng .common = { 90524353eaSIcenowy Zheng .reg = 0x028, 91524353eaSIcenowy Zheng .features = CCU_FEATURE_FIXED_POSTDIV, 92524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 93524353eaSIcenowy Zheng &ccu_nkmp_ops, 94524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 95524353eaSIcenowy Zheng }, 96524353eaSIcenowy Zheng }; 97524353eaSIcenowy Zheng 98524353eaSIcenowy Zheng #define SUN50I_H6_PLL_GPU_REG 0x030 99524353eaSIcenowy Zheng static struct ccu_nkmp pll_gpu_clk = { 100524353eaSIcenowy Zheng .enable = BIT(31), 101524353eaSIcenowy Zheng .lock = BIT(28), 102524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 103524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 104524353eaSIcenowy Zheng .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 105524353eaSIcenowy Zheng .common = { 106524353eaSIcenowy Zheng .reg = 0x030, 107524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-gpu", "osc24M", 108524353eaSIcenowy Zheng &ccu_nkmp_ops, 109524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 110524353eaSIcenowy Zheng }, 111524353eaSIcenowy Zheng }; 112524353eaSIcenowy Zheng 113524353eaSIcenowy Zheng /* 114524353eaSIcenowy Zheng * For Video PLLs, the output divider is described as "used for testing" 115524353eaSIcenowy Zheng * in the user manual. So it's not modelled and forced to 0. 116524353eaSIcenowy Zheng */ 117524353eaSIcenowy Zheng #define SUN50I_H6_PLL_VIDEO0_REG 0x040 118524353eaSIcenowy Zheng static struct ccu_nm pll_video0_clk = { 119524353eaSIcenowy Zheng .enable = BIT(31), 120524353eaSIcenowy Zheng .lock = BIT(28), 121524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 122524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 123524353eaSIcenowy Zheng .fixed_post_div = 4, 124ed443341SJernej Skrabec .min_rate = 288000000, 125ed443341SJernej Skrabec .max_rate = 2400000000UL, 126524353eaSIcenowy Zheng .common = { 127524353eaSIcenowy Zheng .reg = 0x040, 128524353eaSIcenowy Zheng .features = CCU_FEATURE_FIXED_POSTDIV, 129524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-video0", "osc24M", 130524353eaSIcenowy Zheng &ccu_nm_ops, 131524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 132524353eaSIcenowy Zheng }, 133524353eaSIcenowy Zheng }; 134524353eaSIcenowy Zheng 135524353eaSIcenowy Zheng #define SUN50I_H6_PLL_VIDEO1_REG 0x048 136524353eaSIcenowy Zheng static struct ccu_nm pll_video1_clk = { 137524353eaSIcenowy Zheng .enable = BIT(31), 138524353eaSIcenowy Zheng .lock = BIT(28), 139524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 140524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 141524353eaSIcenowy Zheng .fixed_post_div = 4, 142ed443341SJernej Skrabec .min_rate = 288000000, 143ed443341SJernej Skrabec .max_rate = 2400000000UL, 144524353eaSIcenowy Zheng .common = { 145524353eaSIcenowy Zheng .reg = 0x048, 146524353eaSIcenowy Zheng .features = CCU_FEATURE_FIXED_POSTDIV, 147524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-video1", "osc24M", 148524353eaSIcenowy Zheng &ccu_nm_ops, 149524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 150524353eaSIcenowy Zheng }, 151524353eaSIcenowy Zheng }; 152524353eaSIcenowy Zheng 153524353eaSIcenowy Zheng #define SUN50I_H6_PLL_VE_REG 0x058 154524353eaSIcenowy Zheng static struct ccu_nkmp pll_ve_clk = { 155524353eaSIcenowy Zheng .enable = BIT(31), 156524353eaSIcenowy Zheng .lock = BIT(28), 157524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 158524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 159524353eaSIcenowy Zheng .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 160524353eaSIcenowy Zheng .common = { 161524353eaSIcenowy Zheng .reg = 0x058, 162524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-ve", "osc24M", 163524353eaSIcenowy Zheng &ccu_nkmp_ops, 164524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 165524353eaSIcenowy Zheng }, 166524353eaSIcenowy Zheng }; 167524353eaSIcenowy Zheng 168524353eaSIcenowy Zheng #define SUN50I_H6_PLL_DE_REG 0x060 169524353eaSIcenowy Zheng static struct ccu_nkmp pll_de_clk = { 170524353eaSIcenowy Zheng .enable = BIT(31), 171524353eaSIcenowy Zheng .lock = BIT(28), 172524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 173524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 174524353eaSIcenowy Zheng .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 175524353eaSIcenowy Zheng .common = { 176524353eaSIcenowy Zheng .reg = 0x060, 177524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-de", "osc24M", 178524353eaSIcenowy Zheng &ccu_nkmp_ops, 179524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 180524353eaSIcenowy Zheng }, 181524353eaSIcenowy Zheng }; 182524353eaSIcenowy Zheng 183524353eaSIcenowy Zheng #define SUN50I_H6_PLL_HSIC_REG 0x070 184524353eaSIcenowy Zheng static struct ccu_nkmp pll_hsic_clk = { 185524353eaSIcenowy Zheng .enable = BIT(31), 186524353eaSIcenowy Zheng .lock = BIT(28), 187524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 188524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 189524353eaSIcenowy Zheng .p = _SUNXI_CCU_DIV(0, 1), /* output divider */ 190524353eaSIcenowy Zheng .common = { 191524353eaSIcenowy Zheng .reg = 0x070, 192524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-hsic", "osc24M", 193524353eaSIcenowy Zheng &ccu_nkmp_ops, 194524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 195524353eaSIcenowy Zheng }, 196524353eaSIcenowy Zheng }; 197524353eaSIcenowy Zheng 198524353eaSIcenowy Zheng /* 199524353eaSIcenowy Zheng * The Audio PLL is supposed to have 3 outputs: 2 fixed factors from 200524353eaSIcenowy Zheng * the base (2x and 4x), and one variable divider (the one true pll audio). 201524353eaSIcenowy Zheng * 202524353eaSIcenowy Zheng * We don't have any need for the variable divider for now, so we just 203524353eaSIcenowy Zheng * hardcode it to match with the clock names. 204524353eaSIcenowy Zheng */ 205524353eaSIcenowy Zheng #define SUN50I_H6_PLL_AUDIO_REG 0x078 2063ee5f8abSJernej Skrabec 2073ee5f8abSJernej Skrabec static struct ccu_sdm_setting pll_audio_sdm_table[] = { 2083ee5f8abSJernej Skrabec { .rate = 541900800, .pattern = 0xc001288d, .m = 1, .n = 22 }, 2093ee5f8abSJernej Skrabec { .rate = 589824000, .pattern = 0xc00126e9, .m = 1, .n = 24 }, 2103ee5f8abSJernej Skrabec }; 2113ee5f8abSJernej Skrabec 212524353eaSIcenowy Zheng static struct ccu_nm pll_audio_base_clk = { 213524353eaSIcenowy Zheng .enable = BIT(31), 214524353eaSIcenowy Zheng .lock = BIT(28), 215524353eaSIcenowy Zheng .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), 216524353eaSIcenowy Zheng .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ 2173ee5f8abSJernej Skrabec .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 2183ee5f8abSJernej Skrabec BIT(24), 0x178, BIT(31)), 219524353eaSIcenowy Zheng .common = { 2203ee5f8abSJernej Skrabec .features = CCU_FEATURE_SIGMA_DELTA_MOD, 221524353eaSIcenowy Zheng .reg = 0x078, 222524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M", 223524353eaSIcenowy Zheng &ccu_nm_ops, 224524353eaSIcenowy Zheng CLK_SET_RATE_UNGATE), 225524353eaSIcenowy Zheng }, 226524353eaSIcenowy Zheng }; 227524353eaSIcenowy Zheng 228524353eaSIcenowy Zheng static const char * const cpux_parents[] = { "osc24M", "osc32k", 229524353eaSIcenowy Zheng "iosc", "pll-cpux" }; 230524353eaSIcenowy Zheng static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 231524353eaSIcenowy Zheng 0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 232524353eaSIcenowy Zheng static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0); 233524353eaSIcenowy Zheng static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0); 234524353eaSIcenowy Zheng 235524353eaSIcenowy Zheng static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k", 236524353eaSIcenowy Zheng "iosc", "pll-periph0" }; 237524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2", 238524353eaSIcenowy Zheng psi_ahb1_ahb2_parents, 239524353eaSIcenowy Zheng 0x510, 24004ef6795SAndre Przywara 0, 2, /* M */ 2412852bfbfSIcenowy Zheng 8, 2, /* P */ 242524353eaSIcenowy Zheng 24, 2, /* mux */ 243524353eaSIcenowy Zheng 0); 244524353eaSIcenowy Zheng 245524353eaSIcenowy Zheng static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k", 246524353eaSIcenowy Zheng "psi-ahb1-ahb2", 247524353eaSIcenowy Zheng "pll-periph0" }; 248524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c, 24904ef6795SAndre Przywara 0, 2, /* M */ 2502852bfbfSIcenowy Zheng 8, 2, /* P */ 251524353eaSIcenowy Zheng 24, 2, /* mux */ 252524353eaSIcenowy Zheng 0); 253524353eaSIcenowy Zheng 254524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520, 25504ef6795SAndre Przywara 0, 2, /* M */ 2562852bfbfSIcenowy Zheng 8, 2, /* P */ 257524353eaSIcenowy Zheng 24, 2, /* mux */ 258524353eaSIcenowy Zheng 0); 259524353eaSIcenowy Zheng 260524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524, 26104ef6795SAndre Przywara 0, 2, /* M */ 2622852bfbfSIcenowy Zheng 8, 2, /* P */ 263524353eaSIcenowy Zheng 24, 2, /* mux */ 264524353eaSIcenowy Zheng 0); 265524353eaSIcenowy Zheng 266524353eaSIcenowy Zheng static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 267524353eaSIcenowy Zheng "pll-ddr0", "pll-periph0-4x" }; 268524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540, 269524353eaSIcenowy Zheng 0, 3, /* M */ 270524353eaSIcenowy Zheng 24, 2, /* mux */ 271524353eaSIcenowy Zheng BIT(31), /* gate */ 272524353eaSIcenowy Zheng CLK_IS_CRITICAL); 273524353eaSIcenowy Zheng 274524353eaSIcenowy Zheng static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" }; 275524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600, 276524353eaSIcenowy Zheng 0, 4, /* M */ 277524353eaSIcenowy Zheng 24, 1, /* mux */ 278524353eaSIcenowy Zheng BIT(31), /* gate */ 279ab65e04dSJernej Skrabec CLK_SET_RATE_PARENT); 280524353eaSIcenowy Zheng 281524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2", 282524353eaSIcenowy Zheng 0x60c, BIT(0), 0); 283524353eaSIcenowy Zheng 284524353eaSIcenowy Zheng static const char * const deinterlace_parents[] = { "pll-periph0", 285524353eaSIcenowy Zheng "pll-periph1" }; 286524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", 287524353eaSIcenowy Zheng deinterlace_parents, 288524353eaSIcenowy Zheng 0x620, 289524353eaSIcenowy Zheng 0, 4, /* M */ 290524353eaSIcenowy Zheng 24, 1, /* mux */ 291524353eaSIcenowy Zheng BIT(31), /* gate */ 292524353eaSIcenowy Zheng 0); 293524353eaSIcenowy Zheng 294524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2", 295524353eaSIcenowy Zheng 0x62c, BIT(0), 0); 296524353eaSIcenowy Zheng 297524353eaSIcenowy Zheng static const char * const gpu_parents[] = { "pll-gpu" }; 298524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670, 299524353eaSIcenowy Zheng 0, 3, /* M */ 300524353eaSIcenowy Zheng 24, 1, /* mux */ 301524353eaSIcenowy Zheng BIT(31), /* gate */ 302834f65e1SJernej Skrabec CLK_SET_RATE_PARENT); 303524353eaSIcenowy Zheng 304524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2", 305524353eaSIcenowy Zheng 0x67c, BIT(0), 0); 306524353eaSIcenowy Zheng 307524353eaSIcenowy Zheng /* Also applies to EMCE */ 308524353eaSIcenowy Zheng static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" }; 309524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680, 310524353eaSIcenowy Zheng 0, 4, /* M */ 311524353eaSIcenowy Zheng 8, 2, /* N */ 312524353eaSIcenowy Zheng 24, 1, /* mux */ 313524353eaSIcenowy Zheng BIT(31),/* gate */ 314524353eaSIcenowy Zheng 0); 315524353eaSIcenowy Zheng 316524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2", 317524353eaSIcenowy Zheng 0x68c, BIT(0), 0); 318524353eaSIcenowy Zheng 319524353eaSIcenowy Zheng static const char * const ve_parents[] = { "pll-ve" }; 320524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690, 321524353eaSIcenowy Zheng 0, 3, /* M */ 322524353eaSIcenowy Zheng 24, 1, /* mux */ 323524353eaSIcenowy Zheng BIT(31), /* gate */ 3246597ce3dSJernej Skrabec CLK_SET_RATE_PARENT); 325524353eaSIcenowy Zheng 326524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2", 327524353eaSIcenowy Zheng 0x69c, BIT(0), 0); 328524353eaSIcenowy Zheng 329524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(emce_clk, "emce", ce_parents, 0x6b0, 330524353eaSIcenowy Zheng 0, 4, /* M */ 331524353eaSIcenowy Zheng 8, 2, /* N */ 332524353eaSIcenowy Zheng 24, 1, /* mux */ 333524353eaSIcenowy Zheng BIT(31),/* gate */ 334524353eaSIcenowy Zheng 0); 335524353eaSIcenowy Zheng 336524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2", 337524353eaSIcenowy Zheng 0x6bc, BIT(0), 0); 338524353eaSIcenowy Zheng 339524353eaSIcenowy Zheng static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" }; 340524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(vp9_clk, "vp9", vp9_parents, 0x6c0, 341524353eaSIcenowy Zheng 0, 3, /* M */ 342524353eaSIcenowy Zheng 24, 1, /* mux */ 343524353eaSIcenowy Zheng BIT(31), /* gate */ 344524353eaSIcenowy Zheng 0); 345524353eaSIcenowy Zheng 346524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2", 347524353eaSIcenowy Zheng 0x6cc, BIT(0), 0); 348524353eaSIcenowy Zheng 349524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2", 350524353eaSIcenowy Zheng 0x70c, BIT(0), 0); 351524353eaSIcenowy Zheng 352524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2", 353524353eaSIcenowy Zheng 0x71c, BIT(0), 0); 354524353eaSIcenowy Zheng 355524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2", 356524353eaSIcenowy Zheng 0x72c, BIT(0), 0); 357524353eaSIcenowy Zheng 358524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2", 359524353eaSIcenowy Zheng 0x73c, BIT(0), 0); 360524353eaSIcenowy Zheng 361524353eaSIcenowy Zheng static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0); 362524353eaSIcenowy Zheng 363524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2", 364524353eaSIcenowy Zheng 0x78c, BIT(0), 0); 365524353eaSIcenowy Zheng 366524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2", 367524353eaSIcenowy Zheng 0x79c, BIT(0), 0); 368524353eaSIcenowy Zheng 36958c0f798SRongyi Chen static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0); 370524353eaSIcenowy Zheng 371524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0); 372524353eaSIcenowy Zheng 373524353eaSIcenowy Zheng static const char * const dram_parents[] = { "pll-ddr0" }; 374524353eaSIcenowy Zheng static struct ccu_div dram_clk = { 375524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV(0, 2), 376524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 377524353eaSIcenowy Zheng .common = { 378524353eaSIcenowy Zheng .reg = 0x800, 379524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("dram", 380524353eaSIcenowy Zheng dram_parents, 381524353eaSIcenowy Zheng &ccu_div_ops, 382524353eaSIcenowy Zheng CLK_IS_CRITICAL), 383524353eaSIcenowy Zheng }, 384524353eaSIcenowy Zheng }; 385524353eaSIcenowy Zheng 386524353eaSIcenowy Zheng static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus", 387524353eaSIcenowy Zheng 0x804, BIT(0), 0); 388524353eaSIcenowy Zheng static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus", 389524353eaSIcenowy Zheng 0x804, BIT(1), 0); 390524353eaSIcenowy Zheng static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus", 391524353eaSIcenowy Zheng 0x804, BIT(2), 0); 392524353eaSIcenowy Zheng static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus", 393524353eaSIcenowy Zheng 0x804, BIT(3), 0); 394524353eaSIcenowy Zheng static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus", 395524353eaSIcenowy Zheng 0x804, BIT(5), 0); 396524353eaSIcenowy Zheng static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus", 397524353eaSIcenowy Zheng 0x804, BIT(8), 0); 398524353eaSIcenowy Zheng static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus", 399524353eaSIcenowy Zheng 0x804, BIT(11), 0); 400524353eaSIcenowy Zheng 401524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2", 402524353eaSIcenowy Zheng 0x80c, BIT(0), CLK_IS_CRITICAL); 403524353eaSIcenowy Zheng 404524353eaSIcenowy Zheng static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0", 405524353eaSIcenowy Zheng "pll-periph1", "pll-periph0-2x", 406524353eaSIcenowy Zheng "pll-periph1-2x" }; 407524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810, 408524353eaSIcenowy Zheng 0, 4, /* M */ 409524353eaSIcenowy Zheng 8, 2, /* N */ 410524353eaSIcenowy Zheng 24, 3, /* mux */ 411524353eaSIcenowy Zheng BIT(31),/* gate */ 412524353eaSIcenowy Zheng 0); 413524353eaSIcenowy Zheng 414524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814, 415524353eaSIcenowy Zheng 0, 4, /* M */ 416524353eaSIcenowy Zheng 8, 2, /* N */ 417524353eaSIcenowy Zheng 24, 3, /* mux */ 418524353eaSIcenowy Zheng BIT(31),/* gate */ 419524353eaSIcenowy Zheng 0); 420524353eaSIcenowy Zheng 421524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); 422524353eaSIcenowy Zheng 423524353eaSIcenowy Zheng static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", 424524353eaSIcenowy Zheng "pll-periph1-2x" }; 425c2ff8383SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, 426524353eaSIcenowy Zheng 0, 4, /* M */ 427524353eaSIcenowy Zheng 8, 2, /* N */ 428db754893SJagan Teki 24, 2, /* mux */ 429524353eaSIcenowy Zheng BIT(31), /* gate */ 430c2ff8383SIcenowy Zheng 2, /* post-div */ 431524353eaSIcenowy Zheng 0); 432524353eaSIcenowy Zheng 433c2ff8383SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, 434524353eaSIcenowy Zheng 0, 4, /* M */ 435524353eaSIcenowy Zheng 8, 2, /* N */ 436db754893SJagan Teki 24, 2, /* mux */ 437524353eaSIcenowy Zheng BIT(31), /* gate */ 438c2ff8383SIcenowy Zheng 2, /* post-div */ 439524353eaSIcenowy Zheng 0); 440524353eaSIcenowy Zheng 441c2ff8383SIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, 442524353eaSIcenowy Zheng 0, 4, /* M */ 443524353eaSIcenowy Zheng 8, 2, /* N */ 444db754893SJagan Teki 24, 2, /* mux */ 445524353eaSIcenowy Zheng BIT(31), /* gate */ 446c2ff8383SIcenowy Zheng 2, /* post-div */ 447524353eaSIcenowy Zheng 0); 448524353eaSIcenowy Zheng 449524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); 450524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0); 451524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0); 452524353eaSIcenowy Zheng 453524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0); 454524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0); 455524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0); 456524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0); 457524353eaSIcenowy Zheng 458524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0); 459524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0); 460524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0); 461524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0); 462524353eaSIcenowy Zheng 463524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0); 464524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0); 465524353eaSIcenowy Zheng 466524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940, 467524353eaSIcenowy Zheng 0, 4, /* M */ 468524353eaSIcenowy Zheng 8, 2, /* N */ 469524353eaSIcenowy Zheng 24, 3, /* mux */ 470524353eaSIcenowy Zheng BIT(31),/* gate */ 471524353eaSIcenowy Zheng 0); 472524353eaSIcenowy Zheng 473524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944, 474524353eaSIcenowy Zheng 0, 4, /* M */ 475524353eaSIcenowy Zheng 8, 2, /* N */ 476524353eaSIcenowy Zheng 24, 3, /* mux */ 477524353eaSIcenowy Zheng BIT(31),/* gate */ 478524353eaSIcenowy Zheng 0); 479524353eaSIcenowy Zheng 480524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0); 481524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0); 482524353eaSIcenowy Zheng 483524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0); 484524353eaSIcenowy Zheng 485524353eaSIcenowy Zheng static const char * const ts_parents[] = { "osc24M", "pll-periph0" }; 486524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0, 487524353eaSIcenowy Zheng 0, 4, /* M */ 488524353eaSIcenowy Zheng 8, 2, /* N */ 489524353eaSIcenowy Zheng 24, 1, /* mux */ 490524353eaSIcenowy Zheng BIT(31),/* gate */ 491524353eaSIcenowy Zheng 0); 492524353eaSIcenowy Zheng 493524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0); 494524353eaSIcenowy Zheng 495524353eaSIcenowy Zheng static const char * const ir_tx_parents[] = { "osc32k", "osc24M" }; 496524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0, 497524353eaSIcenowy Zheng 0, 4, /* M */ 498524353eaSIcenowy Zheng 8, 2, /* N */ 499524353eaSIcenowy Zheng 24, 1, /* mux */ 500524353eaSIcenowy Zheng BIT(31),/* gate */ 501524353eaSIcenowy Zheng 0); 502524353eaSIcenowy Zheng 503524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0); 504524353eaSIcenowy Zheng 505524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0); 506524353eaSIcenowy Zheng 507524353eaSIcenowy Zheng static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" }; 508524353eaSIcenowy Zheng static struct ccu_div i2s3_clk = { 509524353eaSIcenowy Zheng .enable = BIT(31), 510524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 511524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 512524353eaSIcenowy Zheng .common = { 513524353eaSIcenowy Zheng .reg = 0xa0c, 514524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("i2s3", 515524353eaSIcenowy Zheng audio_parents, 516524353eaSIcenowy Zheng &ccu_div_ops, 51765818ad0SJernej Skrabec CLK_SET_RATE_PARENT), 518524353eaSIcenowy Zheng }, 519524353eaSIcenowy Zheng }; 520524353eaSIcenowy Zheng 521524353eaSIcenowy Zheng static struct ccu_div i2s0_clk = { 522524353eaSIcenowy Zheng .enable = BIT(31), 523524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 524524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 525524353eaSIcenowy Zheng .common = { 526524353eaSIcenowy Zheng .reg = 0xa10, 527524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("i2s0", 528524353eaSIcenowy Zheng audio_parents, 529524353eaSIcenowy Zheng &ccu_div_ops, 53065818ad0SJernej Skrabec CLK_SET_RATE_PARENT), 531524353eaSIcenowy Zheng }, 532524353eaSIcenowy Zheng }; 533524353eaSIcenowy Zheng 534524353eaSIcenowy Zheng static struct ccu_div i2s1_clk = { 535524353eaSIcenowy Zheng .enable = BIT(31), 536524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 537524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 538524353eaSIcenowy Zheng .common = { 539524353eaSIcenowy Zheng .reg = 0xa14, 540524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("i2s1", 541524353eaSIcenowy Zheng audio_parents, 542524353eaSIcenowy Zheng &ccu_div_ops, 54365818ad0SJernej Skrabec CLK_SET_RATE_PARENT), 544524353eaSIcenowy Zheng }, 545524353eaSIcenowy Zheng }; 546524353eaSIcenowy Zheng 547524353eaSIcenowy Zheng static struct ccu_div i2s2_clk = { 548524353eaSIcenowy Zheng .enable = BIT(31), 549524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 550524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 551524353eaSIcenowy Zheng .common = { 552524353eaSIcenowy Zheng .reg = 0xa18, 553524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("i2s2", 554524353eaSIcenowy Zheng audio_parents, 555524353eaSIcenowy Zheng &ccu_div_ops, 55665818ad0SJernej Skrabec CLK_SET_RATE_PARENT), 557524353eaSIcenowy Zheng }, 558524353eaSIcenowy Zheng }; 559524353eaSIcenowy Zheng 560524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0); 561524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0); 562524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0); 563524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0); 564524353eaSIcenowy Zheng 565524353eaSIcenowy Zheng static struct ccu_div spdif_clk = { 566524353eaSIcenowy Zheng .enable = BIT(31), 567524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 568524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 569524353eaSIcenowy Zheng .common = { 570524353eaSIcenowy Zheng .reg = 0xa20, 571524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("spdif", 572524353eaSIcenowy Zheng audio_parents, 573524353eaSIcenowy Zheng &ccu_div_ops, 574524353eaSIcenowy Zheng 0), 575524353eaSIcenowy Zheng }, 576524353eaSIcenowy Zheng }; 577524353eaSIcenowy Zheng 578524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0); 579524353eaSIcenowy Zheng 580524353eaSIcenowy Zheng static struct ccu_div dmic_clk = { 581524353eaSIcenowy Zheng .enable = BIT(31), 582524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 583524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 584524353eaSIcenowy Zheng .common = { 585524353eaSIcenowy Zheng .reg = 0xa40, 586524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("dmic", 587524353eaSIcenowy Zheng audio_parents, 588524353eaSIcenowy Zheng &ccu_div_ops, 589524353eaSIcenowy Zheng 0), 590524353eaSIcenowy Zheng }, 591524353eaSIcenowy Zheng }; 592524353eaSIcenowy Zheng 593524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0); 594524353eaSIcenowy Zheng 595524353eaSIcenowy Zheng static struct ccu_div audio_hub_clk = { 596524353eaSIcenowy Zheng .enable = BIT(31), 597524353eaSIcenowy Zheng .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO), 598524353eaSIcenowy Zheng .mux = _SUNXI_CCU_MUX(24, 2), 599524353eaSIcenowy Zheng .common = { 600524353eaSIcenowy Zheng .reg = 0xa60, 601524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("audio-hub", 602524353eaSIcenowy Zheng audio_parents, 603524353eaSIcenowy Zheng &ccu_div_ops, 604524353eaSIcenowy Zheng 0), 605524353eaSIcenowy Zheng }, 606524353eaSIcenowy Zheng }; 607524353eaSIcenowy Zheng 608524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0); 609524353eaSIcenowy Zheng 610524353eaSIcenowy Zheng /* 611524353eaSIcenowy Zheng * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports. 612524353eaSIcenowy Zheng * We will force them to 0 (12M divided from 48M). 613524353eaSIcenowy Zheng */ 614524353eaSIcenowy Zheng #define SUN50I_H6_USB0_CLK_REG 0xa70 615524353eaSIcenowy Zheng #define SUN50I_H6_USB3_CLK_REG 0xa7c 616524353eaSIcenowy Zheng 617524353eaSIcenowy Zheng static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0); 618524353eaSIcenowy Zheng static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0); 619524353eaSIcenowy Zheng 620524353eaSIcenowy Zheng static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0); 621524353eaSIcenowy Zheng 622524353eaSIcenowy Zheng static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0); 623524353eaSIcenowy Zheng static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0); 624524353eaSIcenowy Zheng static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0); 625524353eaSIcenowy Zheng static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0); 626524353eaSIcenowy Zheng 627524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0); 628524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0); 629524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0); 630524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0); 631524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0); 632524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0); 633524353eaSIcenowy Zheng 6348916d3fcSChen-Yu Tsai static struct clk_fixed_factor pll_periph0_4x_clk; 6358916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M", 6368916d3fcSChen-Yu Tsai &pll_periph0_4x_clk.hw, 24, 1, 0); 637524353eaSIcenowy Zheng static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M", 638524353eaSIcenowy Zheng 0xab0, BIT(31), 0); 639524353eaSIcenowy Zheng static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref", 640524353eaSIcenowy Zheng 0xab0, BIT(30), 0); 641524353eaSIcenowy Zheng 642524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi", 643524353eaSIcenowy Zheng "pll-periph0", 0xab4, 644524353eaSIcenowy Zheng 0, 4, /* M */ 645524353eaSIcenowy Zheng BIT(31), /* gate */ 646524353eaSIcenowy Zheng 0); 647524353eaSIcenowy Zheng 648524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8, 649524353eaSIcenowy Zheng 0, 5, /* M */ 650524353eaSIcenowy Zheng BIT(31), /* gate */ 651524353eaSIcenowy Zheng 0); 652524353eaSIcenowy Zheng 653524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2", 654524353eaSIcenowy Zheng 0xabc, BIT(0), 0); 655524353eaSIcenowy Zheng 656524353eaSIcenowy Zheng static const char * const hdmi_parents[] = { "pll-video0", "pll-video1", 657524353eaSIcenowy Zheng "pll-video1-4x" }; 658524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00, 659524353eaSIcenowy Zheng 0, 4, /* M */ 660524353eaSIcenowy Zheng 24, 2, /* mux */ 661524353eaSIcenowy Zheng BIT(31), /* gate */ 662524353eaSIcenowy Zheng 0); 663524353eaSIcenowy Zheng 664f422fa55SIcenowy Zheng static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0); 665f422fa55SIcenowy Zheng 666524353eaSIcenowy Zheng static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" }; 667524353eaSIcenowy Zheng static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = { 668524353eaSIcenowy Zheng { .index = 1, .div = 36621 }, 669524353eaSIcenowy Zheng }; 67026fae7a4SJernej Skrabec 67126fae7a4SJernej Skrabec #define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10 672524353eaSIcenowy Zheng static struct ccu_mux hdmi_cec_clk = { 673524353eaSIcenowy Zheng .enable = BIT(31), 674524353eaSIcenowy Zheng 675524353eaSIcenowy Zheng .mux = { 676524353eaSIcenowy Zheng .shift = 24, 677524353eaSIcenowy Zheng .width = 2, 678524353eaSIcenowy Zheng 679524353eaSIcenowy Zheng .fixed_predivs = hdmi_cec_predivs, 680524353eaSIcenowy Zheng .n_predivs = ARRAY_SIZE(hdmi_cec_predivs), 681524353eaSIcenowy Zheng }, 682524353eaSIcenowy Zheng 683524353eaSIcenowy Zheng .common = { 684524353eaSIcenowy Zheng .reg = 0xb10, 68575665082SAndre Przywara .features = CCU_FEATURE_FIXED_PREDIV, 686524353eaSIcenowy Zheng .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec", 687524353eaSIcenowy Zheng hdmi_cec_parents, 688524353eaSIcenowy Zheng &ccu_mux_ops, 689524353eaSIcenowy Zheng 0), 690524353eaSIcenowy Zheng }, 691524353eaSIcenowy Zheng }; 692524353eaSIcenowy Zheng 693524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0); 694524353eaSIcenowy Zheng 695524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3", 696524353eaSIcenowy Zheng 0xb5c, BIT(0), 0); 697524353eaSIcenowy Zheng 698524353eaSIcenowy Zheng static const char * const tcon_lcd0_parents[] = { "pll-video0", 699524353eaSIcenowy Zheng "pll-video0-4x", 700524353eaSIcenowy Zheng "pll-video1" }; 701524353eaSIcenowy Zheng static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", 702524353eaSIcenowy Zheng tcon_lcd0_parents, 0xb60, 703524353eaSIcenowy Zheng 24, 3, /* mux */ 704524353eaSIcenowy Zheng BIT(31), /* gate */ 7056597ce3dSJernej Skrabec CLK_SET_RATE_PARENT); 706524353eaSIcenowy Zheng 707524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3", 708524353eaSIcenowy Zheng 0xb7c, BIT(0), 0); 709524353eaSIcenowy Zheng 710524353eaSIcenowy Zheng static const char * const tcon_tv0_parents[] = { "pll-video0", 711524353eaSIcenowy Zheng "pll-video0-4x", 712524353eaSIcenowy Zheng "pll-video1", 713524353eaSIcenowy Zheng "pll-video1-4x" }; 714524353eaSIcenowy Zheng static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", 715524353eaSIcenowy Zheng tcon_tv0_parents, 0xb80, 716524353eaSIcenowy Zheng 0, 4, /* M */ 717524353eaSIcenowy Zheng 8, 2, /* P */ 718524353eaSIcenowy Zheng 24, 3, /* mux */ 719524353eaSIcenowy Zheng BIT(31), /* gate */ 7206597ce3dSJernej Skrabec CLK_SET_RATE_PARENT); 721524353eaSIcenowy Zheng 722524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3", 723524353eaSIcenowy Zheng 0xb9c, BIT(0), 0); 724524353eaSIcenowy Zheng 725524353eaSIcenowy Zheng static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0); 726524353eaSIcenowy Zheng 727524353eaSIcenowy Zheng static const char * const csi_top_parents[] = { "pll-video0", "pll-ve", 728524353eaSIcenowy Zheng "pll-periph0" }; 729524353eaSIcenowy Zheng static const u8 csi_top_table[] = { 0, 2, 3 }; 730524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top", 731524353eaSIcenowy Zheng csi_top_parents, csi_top_table, 0xc04, 732524353eaSIcenowy Zheng 0, 4, /* M */ 733524353eaSIcenowy Zheng 24, 3, /* mux */ 734524353eaSIcenowy Zheng BIT(31), /* gate */ 735524353eaSIcenowy Zheng 0); 736524353eaSIcenowy Zheng 737524353eaSIcenowy Zheng static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0", 738524353eaSIcenowy Zheng "pll-periph0", "pll-periph1" }; 739524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", 740524353eaSIcenowy Zheng csi_mclk_parents, 0xc08, 741524353eaSIcenowy Zheng 0, 5, /* M */ 742524353eaSIcenowy Zheng 24, 3, /* mux */ 743524353eaSIcenowy Zheng BIT(31), /* gate */ 744524353eaSIcenowy Zheng 0); 745524353eaSIcenowy Zheng 746524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0); 747524353eaSIcenowy Zheng 748524353eaSIcenowy Zheng static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" }; 749524353eaSIcenowy Zheng static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40, 750524353eaSIcenowy Zheng 0, 4, /* M */ 751524353eaSIcenowy Zheng 24, 2, /* mux */ 752524353eaSIcenowy Zheng BIT(31), /* gate */ 753524353eaSIcenowy Zheng 0); 754524353eaSIcenowy Zheng 755524353eaSIcenowy Zheng static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0); 756524353eaSIcenowy Zheng 757524353eaSIcenowy Zheng /* Fixed factor clocks */ 7588916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0); 7598916d3fcSChen-Yu Tsai 7608916d3fcSChen-Yu Tsai static const struct clk_hw *clk_parent_pll_audio[] = { 7618916d3fcSChen-Yu Tsai &pll_audio_base_clk.common.hw 7628916d3fcSChen-Yu Tsai }; 763524353eaSIcenowy Zheng 764524353eaSIcenowy Zheng /* 7653ee5f8abSJernej Skrabec * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200 7663ee5f8abSJernej Skrabec * rates can be set exactly in conjunction with sigma-delta modulation. 767524353eaSIcenowy Zheng */ 7688916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio", 7698916d3fcSChen-Yu Tsai clk_parent_pll_audio, 7703ee5f8abSJernej Skrabec 24, 1, CLK_SET_RATE_PARENT); 7718916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", 7728916d3fcSChen-Yu Tsai clk_parent_pll_audio, 7738916d3fcSChen-Yu Tsai 4, 1, CLK_SET_RATE_PARENT); 7748916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", 7758916d3fcSChen-Yu Tsai clk_parent_pll_audio, 7768916d3fcSChen-Yu Tsai 2, 1, CLK_SET_RATE_PARENT); 777524353eaSIcenowy Zheng 7788916d3fcSChen-Yu Tsai static const struct clk_hw *pll_periph0_parents[] = { 7798916d3fcSChen-Yu Tsai &pll_periph0_clk.common.hw 7808916d3fcSChen-Yu Tsai }; 7818916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_periph0_4x_clk, "pll-periph0-4x", 7828916d3fcSChen-Yu Tsai pll_periph0_parents, 7838916d3fcSChen-Yu Tsai 1, 4, 0); 7848916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x", 7858916d3fcSChen-Yu Tsai pll_periph0_parents, 7868916d3fcSChen-Yu Tsai 1, 2, 0); 787524353eaSIcenowy Zheng 7888916d3fcSChen-Yu Tsai static const struct clk_hw *pll_periph1_parents[] = { 7898916d3fcSChen-Yu Tsai &pll_periph1_clk.common.hw 7908916d3fcSChen-Yu Tsai }; 7918916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_periph1_4x_clk, "pll-periph1-4x", 7928916d3fcSChen-Yu Tsai pll_periph1_parents, 7938916d3fcSChen-Yu Tsai 1, 4, 0); 7948916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x", 7958916d3fcSChen-Yu Tsai pll_periph1_parents, 7968916d3fcSChen-Yu Tsai 1, 2, 0); 797524353eaSIcenowy Zheng 7988916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x", 7998916d3fcSChen-Yu Tsai &pll_video0_clk.common.hw, 8008916d3fcSChen-Yu Tsai 1, 4, CLK_SET_RATE_PARENT); 8018916d3fcSChen-Yu Tsai static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x", 8028916d3fcSChen-Yu Tsai &pll_video1_clk.common.hw, 8038916d3fcSChen-Yu Tsai 1, 4, CLK_SET_RATE_PARENT); 804524353eaSIcenowy Zheng 805524353eaSIcenowy Zheng static struct ccu_common *sun50i_h6_ccu_clks[] = { 806524353eaSIcenowy Zheng &pll_cpux_clk.common, 807524353eaSIcenowy Zheng &pll_ddr0_clk.common, 808524353eaSIcenowy Zheng &pll_periph0_clk.common, 809524353eaSIcenowy Zheng &pll_periph1_clk.common, 810524353eaSIcenowy Zheng &pll_gpu_clk.common, 811524353eaSIcenowy Zheng &pll_video0_clk.common, 812524353eaSIcenowy Zheng &pll_video1_clk.common, 813524353eaSIcenowy Zheng &pll_ve_clk.common, 814524353eaSIcenowy Zheng &pll_de_clk.common, 815524353eaSIcenowy Zheng &pll_hsic_clk.common, 816524353eaSIcenowy Zheng &pll_audio_base_clk.common, 817524353eaSIcenowy Zheng &cpux_clk.common, 818524353eaSIcenowy Zheng &axi_clk.common, 819524353eaSIcenowy Zheng &cpux_apb_clk.common, 820524353eaSIcenowy Zheng &psi_ahb1_ahb2_clk.common, 821524353eaSIcenowy Zheng &ahb3_clk.common, 822524353eaSIcenowy Zheng &apb1_clk.common, 823524353eaSIcenowy Zheng &apb2_clk.common, 824524353eaSIcenowy Zheng &mbus_clk.common, 825524353eaSIcenowy Zheng &de_clk.common, 826524353eaSIcenowy Zheng &bus_de_clk.common, 827524353eaSIcenowy Zheng &deinterlace_clk.common, 828524353eaSIcenowy Zheng &bus_deinterlace_clk.common, 829524353eaSIcenowy Zheng &gpu_clk.common, 830524353eaSIcenowy Zheng &bus_gpu_clk.common, 831524353eaSIcenowy Zheng &ce_clk.common, 832524353eaSIcenowy Zheng &bus_ce_clk.common, 833524353eaSIcenowy Zheng &ve_clk.common, 834524353eaSIcenowy Zheng &bus_ve_clk.common, 835524353eaSIcenowy Zheng &emce_clk.common, 836524353eaSIcenowy Zheng &bus_emce_clk.common, 837524353eaSIcenowy Zheng &vp9_clk.common, 838524353eaSIcenowy Zheng &bus_vp9_clk.common, 839524353eaSIcenowy Zheng &bus_dma_clk.common, 840524353eaSIcenowy Zheng &bus_msgbox_clk.common, 841524353eaSIcenowy Zheng &bus_spinlock_clk.common, 842524353eaSIcenowy Zheng &bus_hstimer_clk.common, 843524353eaSIcenowy Zheng &avs_clk.common, 844524353eaSIcenowy Zheng &bus_dbg_clk.common, 845524353eaSIcenowy Zheng &bus_psi_clk.common, 846524353eaSIcenowy Zheng &bus_pwm_clk.common, 847524353eaSIcenowy Zheng &bus_iommu_clk.common, 848524353eaSIcenowy Zheng &dram_clk.common, 849524353eaSIcenowy Zheng &mbus_dma_clk.common, 850524353eaSIcenowy Zheng &mbus_ve_clk.common, 851524353eaSIcenowy Zheng &mbus_ce_clk.common, 852524353eaSIcenowy Zheng &mbus_ts_clk.common, 853524353eaSIcenowy Zheng &mbus_nand_clk.common, 854524353eaSIcenowy Zheng &mbus_csi_clk.common, 855524353eaSIcenowy Zheng &mbus_deinterlace_clk.common, 856524353eaSIcenowy Zheng &bus_dram_clk.common, 857524353eaSIcenowy Zheng &nand0_clk.common, 858524353eaSIcenowy Zheng &nand1_clk.common, 859524353eaSIcenowy Zheng &bus_nand_clk.common, 860524353eaSIcenowy Zheng &mmc0_clk.common, 861524353eaSIcenowy Zheng &mmc1_clk.common, 862524353eaSIcenowy Zheng &mmc2_clk.common, 863524353eaSIcenowy Zheng &bus_mmc0_clk.common, 864524353eaSIcenowy Zheng &bus_mmc1_clk.common, 865524353eaSIcenowy Zheng &bus_mmc2_clk.common, 866524353eaSIcenowy Zheng &bus_uart0_clk.common, 867524353eaSIcenowy Zheng &bus_uart1_clk.common, 868524353eaSIcenowy Zheng &bus_uart2_clk.common, 869524353eaSIcenowy Zheng &bus_uart3_clk.common, 870524353eaSIcenowy Zheng &bus_i2c0_clk.common, 871524353eaSIcenowy Zheng &bus_i2c1_clk.common, 872524353eaSIcenowy Zheng &bus_i2c2_clk.common, 873524353eaSIcenowy Zheng &bus_i2c3_clk.common, 874524353eaSIcenowy Zheng &bus_scr0_clk.common, 875524353eaSIcenowy Zheng &bus_scr1_clk.common, 876524353eaSIcenowy Zheng &spi0_clk.common, 877524353eaSIcenowy Zheng &spi1_clk.common, 878524353eaSIcenowy Zheng &bus_spi0_clk.common, 879524353eaSIcenowy Zheng &bus_spi1_clk.common, 880524353eaSIcenowy Zheng &bus_emac_clk.common, 881524353eaSIcenowy Zheng &ts_clk.common, 882524353eaSIcenowy Zheng &bus_ts_clk.common, 883524353eaSIcenowy Zheng &ir_tx_clk.common, 884524353eaSIcenowy Zheng &bus_ir_tx_clk.common, 885524353eaSIcenowy Zheng &bus_ths_clk.common, 886524353eaSIcenowy Zheng &i2s3_clk.common, 887524353eaSIcenowy Zheng &i2s0_clk.common, 888524353eaSIcenowy Zheng &i2s1_clk.common, 889524353eaSIcenowy Zheng &i2s2_clk.common, 890524353eaSIcenowy Zheng &bus_i2s0_clk.common, 891524353eaSIcenowy Zheng &bus_i2s1_clk.common, 892524353eaSIcenowy Zheng &bus_i2s2_clk.common, 893524353eaSIcenowy Zheng &bus_i2s3_clk.common, 894524353eaSIcenowy Zheng &spdif_clk.common, 895524353eaSIcenowy Zheng &bus_spdif_clk.common, 896524353eaSIcenowy Zheng &dmic_clk.common, 897524353eaSIcenowy Zheng &bus_dmic_clk.common, 898524353eaSIcenowy Zheng &audio_hub_clk.common, 899524353eaSIcenowy Zheng &bus_audio_hub_clk.common, 900524353eaSIcenowy Zheng &usb_ohci0_clk.common, 901524353eaSIcenowy Zheng &usb_phy0_clk.common, 902524353eaSIcenowy Zheng &usb_phy1_clk.common, 903524353eaSIcenowy Zheng &usb_ohci3_clk.common, 904524353eaSIcenowy Zheng &usb_phy3_clk.common, 905524353eaSIcenowy Zheng &usb_hsic_12m_clk.common, 906524353eaSIcenowy Zheng &usb_hsic_clk.common, 907524353eaSIcenowy Zheng &bus_ohci0_clk.common, 908524353eaSIcenowy Zheng &bus_ohci3_clk.common, 909524353eaSIcenowy Zheng &bus_ehci0_clk.common, 910524353eaSIcenowy Zheng &bus_xhci_clk.common, 911524353eaSIcenowy Zheng &bus_ehci3_clk.common, 912524353eaSIcenowy Zheng &bus_otg_clk.common, 913524353eaSIcenowy Zheng &pcie_ref_clk.common, 914524353eaSIcenowy Zheng &pcie_ref_out_clk.common, 915524353eaSIcenowy Zheng &pcie_maxi_clk.common, 916524353eaSIcenowy Zheng &pcie_aux_clk.common, 917524353eaSIcenowy Zheng &bus_pcie_clk.common, 918524353eaSIcenowy Zheng &hdmi_clk.common, 919f422fa55SIcenowy Zheng &hdmi_slow_clk.common, 920524353eaSIcenowy Zheng &hdmi_cec_clk.common, 921524353eaSIcenowy Zheng &bus_hdmi_clk.common, 922524353eaSIcenowy Zheng &bus_tcon_top_clk.common, 923524353eaSIcenowy Zheng &tcon_lcd0_clk.common, 924524353eaSIcenowy Zheng &bus_tcon_lcd0_clk.common, 925524353eaSIcenowy Zheng &tcon_tv0_clk.common, 926524353eaSIcenowy Zheng &bus_tcon_tv0_clk.common, 927524353eaSIcenowy Zheng &csi_cci_clk.common, 928524353eaSIcenowy Zheng &csi_top_clk.common, 929524353eaSIcenowy Zheng &csi_mclk_clk.common, 930524353eaSIcenowy Zheng &bus_csi_clk.common, 931524353eaSIcenowy Zheng &hdcp_clk.common, 932524353eaSIcenowy Zheng &bus_hdcp_clk.common, 933524353eaSIcenowy Zheng }; 934524353eaSIcenowy Zheng 935524353eaSIcenowy Zheng static struct clk_hw_onecell_data sun50i_h6_hw_clks = { 936524353eaSIcenowy Zheng .hws = { 937524353eaSIcenowy Zheng [CLK_OSC12M] = &osc12M_clk.hw, 938524353eaSIcenowy Zheng [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 939524353eaSIcenowy Zheng [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 940524353eaSIcenowy Zheng [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 941524353eaSIcenowy Zheng [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 942524353eaSIcenowy Zheng [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.hw, 943524353eaSIcenowy Zheng [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 944524353eaSIcenowy Zheng [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 945524353eaSIcenowy Zheng [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.hw, 946524353eaSIcenowy Zheng [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 947524353eaSIcenowy Zheng [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 948524353eaSIcenowy Zheng [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw, 949524353eaSIcenowy Zheng [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 950524353eaSIcenowy Zheng [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw, 951524353eaSIcenowy Zheng [CLK_PLL_VE] = &pll_ve_clk.common.hw, 952524353eaSIcenowy Zheng [CLK_PLL_DE] = &pll_de_clk.common.hw, 953524353eaSIcenowy Zheng [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 954524353eaSIcenowy Zheng [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 955524353eaSIcenowy Zheng [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 956524353eaSIcenowy Zheng [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 957524353eaSIcenowy Zheng [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 958524353eaSIcenowy Zheng [CLK_CPUX] = &cpux_clk.common.hw, 959524353eaSIcenowy Zheng [CLK_AXI] = &axi_clk.common.hw, 960524353eaSIcenowy Zheng [CLK_CPUX_APB] = &cpux_apb_clk.common.hw, 961524353eaSIcenowy Zheng [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw, 962524353eaSIcenowy Zheng [CLK_AHB3] = &ahb3_clk.common.hw, 963524353eaSIcenowy Zheng [CLK_APB1] = &apb1_clk.common.hw, 964524353eaSIcenowy Zheng [CLK_APB2] = &apb2_clk.common.hw, 965524353eaSIcenowy Zheng [CLK_MBUS] = &mbus_clk.common.hw, 966524353eaSIcenowy Zheng [CLK_DE] = &de_clk.common.hw, 967524353eaSIcenowy Zheng [CLK_BUS_DE] = &bus_de_clk.common.hw, 968524353eaSIcenowy Zheng [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 969524353eaSIcenowy Zheng [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 970524353eaSIcenowy Zheng [CLK_GPU] = &gpu_clk.common.hw, 971524353eaSIcenowy Zheng [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 972524353eaSIcenowy Zheng [CLK_CE] = &ce_clk.common.hw, 973524353eaSIcenowy Zheng [CLK_BUS_CE] = &bus_ce_clk.common.hw, 974524353eaSIcenowy Zheng [CLK_VE] = &ve_clk.common.hw, 975524353eaSIcenowy Zheng [CLK_BUS_VE] = &bus_ve_clk.common.hw, 976524353eaSIcenowy Zheng [CLK_EMCE] = &emce_clk.common.hw, 977524353eaSIcenowy Zheng [CLK_BUS_EMCE] = &bus_emce_clk.common.hw, 978524353eaSIcenowy Zheng [CLK_VP9] = &vp9_clk.common.hw, 979524353eaSIcenowy Zheng [CLK_BUS_VP9] = &bus_vp9_clk.common.hw, 980524353eaSIcenowy Zheng [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 981524353eaSIcenowy Zheng [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 982524353eaSIcenowy Zheng [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 983524353eaSIcenowy Zheng [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 984524353eaSIcenowy Zheng [CLK_AVS] = &avs_clk.common.hw, 985524353eaSIcenowy Zheng [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 986524353eaSIcenowy Zheng [CLK_BUS_PSI] = &bus_psi_clk.common.hw, 987524353eaSIcenowy Zheng [CLK_BUS_PWM] = &bus_pwm_clk.common.hw, 988524353eaSIcenowy Zheng [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw, 989524353eaSIcenowy Zheng [CLK_DRAM] = &dram_clk.common.hw, 990524353eaSIcenowy Zheng [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw, 991524353eaSIcenowy Zheng [CLK_MBUS_VE] = &mbus_ve_clk.common.hw, 992524353eaSIcenowy Zheng [CLK_MBUS_CE] = &mbus_ce_clk.common.hw, 993524353eaSIcenowy Zheng [CLK_MBUS_TS] = &mbus_ts_clk.common.hw, 994524353eaSIcenowy Zheng [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw, 995524353eaSIcenowy Zheng [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw, 996524353eaSIcenowy Zheng [CLK_MBUS_DEINTERLACE] = &mbus_deinterlace_clk.common.hw, 997524353eaSIcenowy Zheng [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 998524353eaSIcenowy Zheng [CLK_NAND0] = &nand0_clk.common.hw, 999524353eaSIcenowy Zheng [CLK_NAND1] = &nand1_clk.common.hw, 1000524353eaSIcenowy Zheng [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 1001524353eaSIcenowy Zheng [CLK_MMC0] = &mmc0_clk.common.hw, 1002524353eaSIcenowy Zheng [CLK_MMC1] = &mmc1_clk.common.hw, 1003524353eaSIcenowy Zheng [CLK_MMC2] = &mmc2_clk.common.hw, 1004524353eaSIcenowy Zheng [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 1005524353eaSIcenowy Zheng [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 1006524353eaSIcenowy Zheng [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 1007524353eaSIcenowy Zheng [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 1008524353eaSIcenowy Zheng [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 1009524353eaSIcenowy Zheng [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 1010524353eaSIcenowy Zheng [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 1011524353eaSIcenowy Zheng [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 1012524353eaSIcenowy Zheng [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 1013524353eaSIcenowy Zheng [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 1014524353eaSIcenowy Zheng [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, 1015524353eaSIcenowy Zheng [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw, 1016524353eaSIcenowy Zheng [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw, 1017524353eaSIcenowy Zheng [CLK_SPI0] = &spi0_clk.common.hw, 1018524353eaSIcenowy Zheng [CLK_SPI1] = &spi1_clk.common.hw, 1019524353eaSIcenowy Zheng [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 1020524353eaSIcenowy Zheng [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 1021524353eaSIcenowy Zheng [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 1022524353eaSIcenowy Zheng [CLK_TS] = &ts_clk.common.hw, 1023524353eaSIcenowy Zheng [CLK_BUS_TS] = &bus_ts_clk.common.hw, 1024524353eaSIcenowy Zheng [CLK_IR_TX] = &ir_tx_clk.common.hw, 1025524353eaSIcenowy Zheng [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw, 1026524353eaSIcenowy Zheng [CLK_BUS_THS] = &bus_ths_clk.common.hw, 1027524353eaSIcenowy Zheng [CLK_I2S3] = &i2s3_clk.common.hw, 1028524353eaSIcenowy Zheng [CLK_I2S0] = &i2s0_clk.common.hw, 1029524353eaSIcenowy Zheng [CLK_I2S1] = &i2s1_clk.common.hw, 1030524353eaSIcenowy Zheng [CLK_I2S2] = &i2s2_clk.common.hw, 1031524353eaSIcenowy Zheng [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 1032524353eaSIcenowy Zheng [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 1033524353eaSIcenowy Zheng [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 1034524353eaSIcenowy Zheng [CLK_BUS_I2S3] = &bus_i2s3_clk.common.hw, 1035524353eaSIcenowy Zheng [CLK_SPDIF] = &spdif_clk.common.hw, 1036524353eaSIcenowy Zheng [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 1037524353eaSIcenowy Zheng [CLK_DMIC] = &dmic_clk.common.hw, 1038524353eaSIcenowy Zheng [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw, 1039524353eaSIcenowy Zheng [CLK_AUDIO_HUB] = &audio_hub_clk.common.hw, 1040524353eaSIcenowy Zheng [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw, 1041524353eaSIcenowy Zheng [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 1042524353eaSIcenowy Zheng [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 1043524353eaSIcenowy Zheng [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 1044524353eaSIcenowy Zheng [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw, 1045524353eaSIcenowy Zheng [CLK_USB_PHY3] = &usb_phy3_clk.common.hw, 1046524353eaSIcenowy Zheng [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, 1047524353eaSIcenowy Zheng [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 1048524353eaSIcenowy Zheng [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 1049524353eaSIcenowy Zheng [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw, 1050524353eaSIcenowy Zheng [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 1051524353eaSIcenowy Zheng [CLK_BUS_XHCI] = &bus_xhci_clk.common.hw, 1052524353eaSIcenowy Zheng [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw, 1053524353eaSIcenowy Zheng [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 1054524353eaSIcenowy Zheng [CLK_PCIE_REF_100M] = &pcie_ref_100m_clk.hw, 1055524353eaSIcenowy Zheng [CLK_PCIE_REF] = &pcie_ref_clk.common.hw, 1056524353eaSIcenowy Zheng [CLK_PCIE_REF_OUT] = &pcie_ref_out_clk.common.hw, 1057524353eaSIcenowy Zheng [CLK_PCIE_MAXI] = &pcie_maxi_clk.common.hw, 1058524353eaSIcenowy Zheng [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw, 1059524353eaSIcenowy Zheng [CLK_BUS_PCIE] = &bus_pcie_clk.common.hw, 1060524353eaSIcenowy Zheng [CLK_HDMI] = &hdmi_clk.common.hw, 1061f422fa55SIcenowy Zheng [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw, 1062524353eaSIcenowy Zheng [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, 1063524353eaSIcenowy Zheng [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 1064524353eaSIcenowy Zheng [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw, 1065524353eaSIcenowy Zheng [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, 1066524353eaSIcenowy Zheng [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, 1067524353eaSIcenowy Zheng [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw, 1068524353eaSIcenowy Zheng [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, 1069524353eaSIcenowy Zheng [CLK_CSI_CCI] = &csi_cci_clk.common.hw, 1070524353eaSIcenowy Zheng [CLK_CSI_TOP] = &csi_top_clk.common.hw, 1071524353eaSIcenowy Zheng [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 1072524353eaSIcenowy Zheng [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 1073524353eaSIcenowy Zheng [CLK_HDCP] = &hdcp_clk.common.hw, 1074524353eaSIcenowy Zheng [CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw, 1075524353eaSIcenowy Zheng }, 1076524353eaSIcenowy Zheng .num = CLK_NUMBER, 1077524353eaSIcenowy Zheng }; 1078524353eaSIcenowy Zheng 1079524353eaSIcenowy Zheng static struct ccu_reset_map sun50i_h6_ccu_resets[] = { 1080524353eaSIcenowy Zheng [RST_MBUS] = { 0x540, BIT(30) }, 1081524353eaSIcenowy Zheng 1082524353eaSIcenowy Zheng [RST_BUS_DE] = { 0x60c, BIT(16) }, 1083524353eaSIcenowy Zheng [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) }, 1084524353eaSIcenowy Zheng [RST_BUS_GPU] = { 0x67c, BIT(16) }, 1085524353eaSIcenowy Zheng [RST_BUS_CE] = { 0x68c, BIT(16) }, 1086524353eaSIcenowy Zheng [RST_BUS_VE] = { 0x69c, BIT(16) }, 1087524353eaSIcenowy Zheng [RST_BUS_EMCE] = { 0x6bc, BIT(16) }, 1088524353eaSIcenowy Zheng [RST_BUS_VP9] = { 0x6cc, BIT(16) }, 1089524353eaSIcenowy Zheng [RST_BUS_DMA] = { 0x70c, BIT(16) }, 1090524353eaSIcenowy Zheng [RST_BUS_MSGBOX] = { 0x71c, BIT(16) }, 1091524353eaSIcenowy Zheng [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) }, 1092524353eaSIcenowy Zheng [RST_BUS_HSTIMER] = { 0x73c, BIT(16) }, 1093524353eaSIcenowy Zheng [RST_BUS_DBG] = { 0x78c, BIT(16) }, 1094524353eaSIcenowy Zheng [RST_BUS_PSI] = { 0x79c, BIT(16) }, 1095524353eaSIcenowy Zheng [RST_BUS_PWM] = { 0x7ac, BIT(16) }, 1096524353eaSIcenowy Zheng [RST_BUS_IOMMU] = { 0x7bc, BIT(16) }, 1097524353eaSIcenowy Zheng [RST_BUS_DRAM] = { 0x80c, BIT(16) }, 1098524353eaSIcenowy Zheng [RST_BUS_NAND] = { 0x82c, BIT(16) }, 1099524353eaSIcenowy Zheng [RST_BUS_MMC0] = { 0x84c, BIT(16) }, 1100524353eaSIcenowy Zheng [RST_BUS_MMC1] = { 0x84c, BIT(17) }, 1101524353eaSIcenowy Zheng [RST_BUS_MMC2] = { 0x84c, BIT(18) }, 1102524353eaSIcenowy Zheng [RST_BUS_UART0] = { 0x90c, BIT(16) }, 1103524353eaSIcenowy Zheng [RST_BUS_UART1] = { 0x90c, BIT(17) }, 1104524353eaSIcenowy Zheng [RST_BUS_UART2] = { 0x90c, BIT(18) }, 1105524353eaSIcenowy Zheng [RST_BUS_UART3] = { 0x90c, BIT(19) }, 1106524353eaSIcenowy Zheng [RST_BUS_I2C0] = { 0x91c, BIT(16) }, 1107524353eaSIcenowy Zheng [RST_BUS_I2C1] = { 0x91c, BIT(17) }, 1108524353eaSIcenowy Zheng [RST_BUS_I2C2] = { 0x91c, BIT(18) }, 1109524353eaSIcenowy Zheng [RST_BUS_I2C3] = { 0x91c, BIT(19) }, 1110524353eaSIcenowy Zheng [RST_BUS_SCR0] = { 0x93c, BIT(16) }, 1111524353eaSIcenowy Zheng [RST_BUS_SCR1] = { 0x93c, BIT(17) }, 1112524353eaSIcenowy Zheng [RST_BUS_SPI0] = { 0x96c, BIT(16) }, 1113524353eaSIcenowy Zheng [RST_BUS_SPI1] = { 0x96c, BIT(17) }, 1114524353eaSIcenowy Zheng [RST_BUS_EMAC] = { 0x97c, BIT(16) }, 1115524353eaSIcenowy Zheng [RST_BUS_TS] = { 0x9bc, BIT(16) }, 1116524353eaSIcenowy Zheng [RST_BUS_IR_TX] = { 0x9cc, BIT(16) }, 1117524353eaSIcenowy Zheng [RST_BUS_THS] = { 0x9fc, BIT(16) }, 1118524353eaSIcenowy Zheng [RST_BUS_I2S0] = { 0xa1c, BIT(16) }, 1119524353eaSIcenowy Zheng [RST_BUS_I2S1] = { 0xa1c, BIT(17) }, 1120524353eaSIcenowy Zheng [RST_BUS_I2S2] = { 0xa1c, BIT(18) }, 1121524353eaSIcenowy Zheng [RST_BUS_I2S3] = { 0xa1c, BIT(19) }, 1122524353eaSIcenowy Zheng [RST_BUS_SPDIF] = { 0xa2c, BIT(16) }, 1123524353eaSIcenowy Zheng [RST_BUS_DMIC] = { 0xa4c, BIT(16) }, 1124524353eaSIcenowy Zheng [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) }, 1125524353eaSIcenowy Zheng 1126524353eaSIcenowy Zheng [RST_USB_PHY0] = { 0xa70, BIT(30) }, 1127524353eaSIcenowy Zheng [RST_USB_PHY1] = { 0xa74, BIT(30) }, 1128524353eaSIcenowy Zheng [RST_USB_PHY3] = { 0xa7c, BIT(30) }, 1129524353eaSIcenowy Zheng [RST_USB_HSIC] = { 0xa7c, BIT(28) }, 1130524353eaSIcenowy Zheng 1131524353eaSIcenowy Zheng [RST_BUS_OHCI0] = { 0xa8c, BIT(16) }, 1132524353eaSIcenowy Zheng [RST_BUS_OHCI3] = { 0xa8c, BIT(19) }, 1133524353eaSIcenowy Zheng [RST_BUS_EHCI0] = { 0xa8c, BIT(20) }, 1134524353eaSIcenowy Zheng [RST_BUS_XHCI] = { 0xa8c, BIT(21) }, 1135524353eaSIcenowy Zheng [RST_BUS_EHCI3] = { 0xa8c, BIT(23) }, 1136524353eaSIcenowy Zheng [RST_BUS_OTG] = { 0xa8c, BIT(24) }, 1137524353eaSIcenowy Zheng [RST_BUS_PCIE] = { 0xabc, BIT(16) }, 1138524353eaSIcenowy Zheng 1139524353eaSIcenowy Zheng [RST_PCIE_POWERUP] = { 0xabc, BIT(17) }, 1140524353eaSIcenowy Zheng 1141524353eaSIcenowy Zheng [RST_BUS_HDMI] = { 0xb1c, BIT(16) }, 1142524353eaSIcenowy Zheng [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) }, 1143524353eaSIcenowy Zheng [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) }, 1144524353eaSIcenowy Zheng [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) }, 1145524353eaSIcenowy Zheng [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) }, 1146524353eaSIcenowy Zheng [RST_BUS_CSI] = { 0xc2c, BIT(16) }, 1147524353eaSIcenowy Zheng [RST_BUS_HDCP] = { 0xc4c, BIT(16) }, 1148524353eaSIcenowy Zheng }; 1149524353eaSIcenowy Zheng 1150524353eaSIcenowy Zheng static const struct sunxi_ccu_desc sun50i_h6_ccu_desc = { 1151524353eaSIcenowy Zheng .ccu_clks = sun50i_h6_ccu_clks, 1152524353eaSIcenowy Zheng .num_ccu_clks = ARRAY_SIZE(sun50i_h6_ccu_clks), 1153524353eaSIcenowy Zheng 1154524353eaSIcenowy Zheng .hw_clks = &sun50i_h6_hw_clks, 1155524353eaSIcenowy Zheng 1156524353eaSIcenowy Zheng .resets = sun50i_h6_ccu_resets, 1157524353eaSIcenowy Zheng .num_resets = ARRAY_SIZE(sun50i_h6_ccu_resets), 1158524353eaSIcenowy Zheng }; 1159524353eaSIcenowy Zheng 1160524353eaSIcenowy Zheng static const u32 pll_regs[] = { 1161524353eaSIcenowy Zheng SUN50I_H6_PLL_CPUX_REG, 1162524353eaSIcenowy Zheng SUN50I_H6_PLL_DDR0_REG, 1163524353eaSIcenowy Zheng SUN50I_H6_PLL_PERIPH0_REG, 1164524353eaSIcenowy Zheng SUN50I_H6_PLL_PERIPH1_REG, 1165524353eaSIcenowy Zheng SUN50I_H6_PLL_GPU_REG, 1166524353eaSIcenowy Zheng SUN50I_H6_PLL_VIDEO0_REG, 1167524353eaSIcenowy Zheng SUN50I_H6_PLL_VIDEO1_REG, 1168524353eaSIcenowy Zheng SUN50I_H6_PLL_VE_REG, 1169524353eaSIcenowy Zheng SUN50I_H6_PLL_DE_REG, 1170524353eaSIcenowy Zheng SUN50I_H6_PLL_HSIC_REG, 1171524353eaSIcenowy Zheng SUN50I_H6_PLL_AUDIO_REG, 1172524353eaSIcenowy Zheng }; 1173524353eaSIcenowy Zheng 1174524353eaSIcenowy Zheng static const u32 pll_video_regs[] = { 1175524353eaSIcenowy Zheng SUN50I_H6_PLL_VIDEO0_REG, 1176524353eaSIcenowy Zheng SUN50I_H6_PLL_VIDEO1_REG, 1177524353eaSIcenowy Zheng }; 1178524353eaSIcenowy Zheng 1179524353eaSIcenowy Zheng static const u32 usb2_clk_regs[] = { 1180524353eaSIcenowy Zheng SUN50I_H6_USB0_CLK_REG, 1181524353eaSIcenowy Zheng SUN50I_H6_USB3_CLK_REG, 1182524353eaSIcenowy Zheng }; 1183524353eaSIcenowy Zheng 1184524353eaSIcenowy Zheng static int sun50i_h6_ccu_probe(struct platform_device *pdev) 1185524353eaSIcenowy Zheng { 1186524353eaSIcenowy Zheng struct resource *res; 1187524353eaSIcenowy Zheng void __iomem *reg; 1188524353eaSIcenowy Zheng u32 val; 1189524353eaSIcenowy Zheng int i; 1190524353eaSIcenowy Zheng 1191524353eaSIcenowy Zheng res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1192524353eaSIcenowy Zheng reg = devm_ioremap_resource(&pdev->dev, res); 1193524353eaSIcenowy Zheng if (IS_ERR(reg)) 1194524353eaSIcenowy Zheng return PTR_ERR(reg); 1195524353eaSIcenowy Zheng 1196524353eaSIcenowy Zheng /* Enable the lock bits on all PLLs */ 1197524353eaSIcenowy Zheng for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { 1198524353eaSIcenowy Zheng val = readl(reg + pll_regs[i]); 1199524353eaSIcenowy Zheng val |= BIT(29); 1200524353eaSIcenowy Zheng writel(val, reg + pll_regs[i]); 1201524353eaSIcenowy Zheng } 1202524353eaSIcenowy Zheng 1203524353eaSIcenowy Zheng /* 1204524353eaSIcenowy Zheng * Force the output divider of video PLLs to 0. 1205524353eaSIcenowy Zheng * 1206524353eaSIcenowy Zheng * See the comment before pll-video0 definition for the reason. 1207524353eaSIcenowy Zheng */ 1208524353eaSIcenowy Zheng for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) { 1209524353eaSIcenowy Zheng val = readl(reg + pll_video_regs[i]); 1210524353eaSIcenowy Zheng val &= ~BIT(0); 1211524353eaSIcenowy Zheng writel(val, reg + pll_video_regs[i]); 1212524353eaSIcenowy Zheng } 1213524353eaSIcenowy Zheng 1214524353eaSIcenowy Zheng /* 1215524353eaSIcenowy Zheng * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz) 1216524353eaSIcenowy Zheng * 1217524353eaSIcenowy Zheng * This clock mux is still mysterious, and the code just enforces 1218524353eaSIcenowy Zheng * it to have a valid clock parent. 1219524353eaSIcenowy Zheng */ 1220524353eaSIcenowy Zheng for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) { 1221524353eaSIcenowy Zheng val = readl(reg + usb2_clk_regs[i]); 1222524353eaSIcenowy Zheng val &= ~GENMASK(25, 24); 1223524353eaSIcenowy Zheng writel (val, reg + usb2_clk_regs[i]); 1224524353eaSIcenowy Zheng } 1225524353eaSIcenowy Zheng 1226524353eaSIcenowy Zheng /* 12273ee5f8abSJernej Skrabec * Force the post-divider of pll-audio to 12 and the output divider 12283ee5f8abSJernej Skrabec * of it to 2, so 24576000 and 22579200 rates can be set exactly. 1229524353eaSIcenowy Zheng */ 1230524353eaSIcenowy Zheng val = readl(reg + SUN50I_H6_PLL_AUDIO_REG); 1231524353eaSIcenowy Zheng val &= ~(GENMASK(21, 16) | BIT(0)); 12323ee5f8abSJernej Skrabec writel(val | (11 << 16) | BIT(0), reg + SUN50I_H6_PLL_AUDIO_REG); 1233524353eaSIcenowy Zheng 123426fae7a4SJernej Skrabec /* 123526fae7a4SJernej Skrabec * First clock parent (osc32K) is unusable for CEC. But since there 123626fae7a4SJernej Skrabec * is no good way to force parent switch (both run with same frequency), 123726fae7a4SJernej Skrabec * just set second clock parent here. 123826fae7a4SJernej Skrabec */ 123926fae7a4SJernej Skrabec val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG); 124026fae7a4SJernej Skrabec val |= BIT(24); 124126fae7a4SJernej Skrabec writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG); 124226fae7a4SJernej Skrabec 12439bec2b9cSSamuel Holland return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_h6_ccu_desc); 1244524353eaSIcenowy Zheng } 1245524353eaSIcenowy Zheng 1246524353eaSIcenowy Zheng static const struct of_device_id sun50i_h6_ccu_ids[] = { 1247524353eaSIcenowy Zheng { .compatible = "allwinner,sun50i-h6-ccu" }, 1248524353eaSIcenowy Zheng { } 1249524353eaSIcenowy Zheng }; 1250524353eaSIcenowy Zheng 1251524353eaSIcenowy Zheng static struct platform_driver sun50i_h6_ccu_driver = { 1252524353eaSIcenowy Zheng .probe = sun50i_h6_ccu_probe, 1253524353eaSIcenowy Zheng .driver = { 1254524353eaSIcenowy Zheng .name = "sun50i-h6-ccu", 1255*66028ddbSSamuel Holland .suppress_bind_attrs = true, 1256524353eaSIcenowy Zheng .of_match_table = sun50i_h6_ccu_ids, 1257524353eaSIcenowy Zheng }, 1258524353eaSIcenowy Zheng }; 1259524353eaSIcenowy Zheng builtin_platform_driver(sun50i_h6_ccu_driver); 1260