1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
4  */
5 
6 #include <linux/clk-provider.h>
7 #include <linux/module.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
13 
14 #include "ccu_div.h"
15 #include "ccu_gate.h"
16 #include "ccu_mp.h"
17 #include "ccu_nm.h"
18 
19 #include "ccu-sun50i-h6-r.h"
20 
21 /*
22  * Information about AR100 and AHB/APB clocks in R_CCU are gathered from
23  * clock definitions in the BSP source code.
24  */
25 
26 static const char * const ar100_r_apb2_parents[] = { "osc24M", "osc32k",
27 						     "iosc", "pll-periph0" };
28 static const struct ccu_mux_var_prediv ar100_r_apb2_predivs[] = {
29 	{ .index = 3, .shift = 0, .width = 5 },
30 };
31 
32 static struct ccu_div ar100_clk = {
33 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
34 
35 	.mux		= {
36 		.shift	= 24,
37 		.width	= 2,
38 
39 		.var_predivs	= ar100_r_apb2_predivs,
40 		.n_var_predivs	= ARRAY_SIZE(ar100_r_apb2_predivs),
41 	},
42 
43 	.common		= {
44 		.reg		= 0x000,
45 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
46 		.hw.init	= CLK_HW_INIT_PARENTS("ar100",
47 						      ar100_r_apb2_parents,
48 						      &ccu_div_ops,
49 						      0),
50 	},
51 };
52 
53 static CLK_FIXED_FACTOR_HW(r_ahb_clk, "r-ahb", &ar100_clk.common.hw, 1, 1, 0);
54 
55 static SUNXI_CCU_M(r_apb1_clk, "r-apb1", "r-ahb", 0x00c, 0, 2, 0);
56 
57 static struct ccu_div r_apb2_clk = {
58 	.div		= _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
59 
60 	.mux		= {
61 		.shift	= 24,
62 		.width	= 2,
63 
64 		.var_predivs	= ar100_r_apb2_predivs,
65 		.n_var_predivs	= ARRAY_SIZE(ar100_r_apb2_predivs),
66 	},
67 
68 	.common		= {
69 		.reg		= 0x010,
70 		.features	= CCU_FEATURE_VARIABLE_PREDIV,
71 		.hw.init	= CLK_HW_INIT_PARENTS("r-apb2",
72 						      ar100_r_apb2_parents,
73 						      &ccu_div_ops,
74 						      0),
75 	},
76 };
77 
78 /*
79  * Information about the gate/resets are gathered from the clock header file
80  * in the BSP source code, although most of them are unused. The existence
81  * of the hardware block is verified with "3.1 Memory Mapping" chapter in
82  * "Allwinner H6 V200 User Manual V1.1"; and the parent APB buses are verified
83  * with "3.3.2.1 System Bus Tree" chapter inthe same document.
84  */
85 static SUNXI_CCU_GATE(r_apb1_timer_clk,	"r-apb1-timer",	"r-apb1",
86 		      0x11c, BIT(0), 0);
87 static SUNXI_CCU_GATE(r_apb1_twd_clk,	"r-apb1-twd",	"r-apb1",
88 		      0x12c, BIT(0), 0);
89 static SUNXI_CCU_GATE(r_apb1_pwm_clk,	"r-apb1-pwm",	"r-apb1",
90 		      0x13c, BIT(0), 0);
91 static SUNXI_CCU_GATE(r_apb2_uart_clk,	"r-apb2-uart",	"r-apb2",
92 		      0x18c, BIT(0), 0);
93 static SUNXI_CCU_GATE(r_apb2_i2c_clk,	"r-apb2-i2c",	"r-apb2",
94 		      0x19c, BIT(0), 0);
95 static SUNXI_CCU_GATE(r_apb2_rsb_clk,	"r-apb2-rsb",	"r-apb2",
96 		      0x1bc, BIT(0), 0);
97 static SUNXI_CCU_GATE(r_apb1_ir_clk,	"r-apb1-ir",	"r-apb1",
98 		      0x1cc, BIT(0), 0);
99 static SUNXI_CCU_GATE(r_apb1_w1_clk,	"r-apb1-w1",	"r-apb1",
100 		      0x1ec, BIT(0), 0);
101 
102 /* Information of IR(RX) mod clock is gathered from BSP source code */
103 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
104 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
105 				  r_mod0_default_parents, 0x1c0,
106 				  0, 5,		/* M */
107 				  8, 2,		/* P */
108 				  24, 1,	/* mux */
109 				  BIT(31),	/* gate */
110 				  0);
111 
112 /*
113  * BSP didn't use the 1-wire function at all now, and the information about
114  * this mod clock is guessed from the IR mod clock above. The existence of
115  * this mod clock is proven by BSP clock header, and the dividers are verified
116  * by contents in the 1-wire related chapter of the User Manual.
117  */
118 
119 static SUNXI_CCU_MP_WITH_MUX_GATE(w1_clk, "w1",
120 				  r_mod0_default_parents, 0x1e0,
121 				  0, 5,		/* M */
122 				  8, 2,		/* P */
123 				  24, 1,	/* mux */
124 				  BIT(31),	/* gate */
125 				  0);
126 
127 static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
128 	&ar100_clk.common,
129 	&r_apb1_clk.common,
130 	&r_apb2_clk.common,
131 	&r_apb1_timer_clk.common,
132 	&r_apb1_twd_clk.common,
133 	&r_apb1_pwm_clk.common,
134 	&r_apb2_uart_clk.common,
135 	&r_apb2_i2c_clk.common,
136 	&r_apb2_rsb_clk.common,
137 	&r_apb1_ir_clk.common,
138 	&r_apb1_w1_clk.common,
139 	&ir_clk.common,
140 	&w1_clk.common,
141 };
142 
143 static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
144 	&r_apb1_clk.common,
145 	&r_apb2_clk.common,
146 	&r_apb1_twd_clk.common,
147 	&r_apb2_i2c_clk.common,
148 	&r_apb2_rsb_clk.common,
149 	&r_apb1_ir_clk.common,
150 	&ir_clk.common,
151 };
152 
153 static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
154 	.hws	= {
155 		[CLK_AR100]		= &ar100_clk.common.hw,
156 		[CLK_R_AHB]		= &r_ahb_clk.hw,
157 		[CLK_R_APB1]		= &r_apb1_clk.common.hw,
158 		[CLK_R_APB2]		= &r_apb2_clk.common.hw,
159 		[CLK_R_APB1_TIMER]	= &r_apb1_timer_clk.common.hw,
160 		[CLK_R_APB1_TWD]	= &r_apb1_twd_clk.common.hw,
161 		[CLK_R_APB1_PWM]	= &r_apb1_pwm_clk.common.hw,
162 		[CLK_R_APB2_UART]	= &r_apb2_uart_clk.common.hw,
163 		[CLK_R_APB2_I2C]	= &r_apb2_i2c_clk.common.hw,
164 		[CLK_R_APB2_RSB]	= &r_apb2_rsb_clk.common.hw,
165 		[CLK_R_APB1_IR]		= &r_apb1_ir_clk.common.hw,
166 		[CLK_R_APB1_W1]		= &r_apb1_w1_clk.common.hw,
167 		[CLK_IR]		= &ir_clk.common.hw,
168 		[CLK_W1]		= &w1_clk.common.hw,
169 	},
170 	.num	= CLK_NUMBER,
171 };
172 
173 static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
174 	.hws	= {
175 		[CLK_R_AHB]		= &r_ahb_clk.hw,
176 		[CLK_R_APB1]		= &r_apb1_clk.common.hw,
177 		[CLK_R_APB2]		= &r_apb2_clk.common.hw,
178 		[CLK_R_APB1_TWD]	= &r_apb1_twd_clk.common.hw,
179 		[CLK_R_APB2_I2C]	= &r_apb2_i2c_clk.common.hw,
180 		[CLK_R_APB2_RSB]	= &r_apb2_rsb_clk.common.hw,
181 		[CLK_R_APB1_IR]		= &r_apb1_ir_clk.common.hw,
182 		[CLK_IR]		= &ir_clk.common.hw,
183 	},
184 	.num	= CLK_NUMBER,
185 };
186 
187 static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
188 	[RST_R_APB1_TIMER]	=  { 0x11c, BIT(16) },
189 	[RST_R_APB1_TWD]	=  { 0x12c, BIT(16) },
190 	[RST_R_APB1_PWM]	=  { 0x13c, BIT(16) },
191 	[RST_R_APB2_UART]	=  { 0x18c, BIT(16) },
192 	[RST_R_APB2_I2C]	=  { 0x19c, BIT(16) },
193 	[RST_R_APB2_RSB]	=  { 0x1bc, BIT(16) },
194 	[RST_R_APB1_IR]		=  { 0x1cc, BIT(16) },
195 	[RST_R_APB1_W1]		=  { 0x1ec, BIT(16) },
196 };
197 
198 static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
199 	[RST_R_APB1_TWD]	=  { 0x12c, BIT(16) },
200 	[RST_R_APB2_I2C]	=  { 0x19c, BIT(16) },
201 	[RST_R_APB2_RSB]	=  { 0x1bc, BIT(16) },
202 	[RST_R_APB1_IR]		=  { 0x1cc, BIT(16) },
203 };
204 
205 static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
206 	.ccu_clks	= sun50i_h6_r_ccu_clks,
207 	.num_ccu_clks	= ARRAY_SIZE(sun50i_h6_r_ccu_clks),
208 
209 	.hw_clks	= &sun50i_h6_r_hw_clks,
210 
211 	.resets		= sun50i_h6_r_ccu_resets,
212 	.num_resets	= ARRAY_SIZE(sun50i_h6_r_ccu_resets),
213 };
214 
215 static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
216 	.ccu_clks	= sun50i_h616_r_ccu_clks,
217 	.num_ccu_clks	= ARRAY_SIZE(sun50i_h616_r_ccu_clks),
218 
219 	.hw_clks	= &sun50i_h616_r_hw_clks,
220 
221 	.resets		= sun50i_h616_r_ccu_resets,
222 	.num_resets	= ARRAY_SIZE(sun50i_h616_r_ccu_resets),
223 };
224 
225 static int sun50i_h6_r_ccu_probe(struct platform_device *pdev)
226 {
227 	const struct sunxi_ccu_desc *desc;
228 	void __iomem *reg;
229 
230 	desc = of_device_get_match_data(&pdev->dev);
231 	if (!desc)
232 		return -EINVAL;
233 
234 	reg = devm_platform_ioremap_resource(pdev, 0);
235 	if (IS_ERR(reg))
236 		return PTR_ERR(reg);
237 
238 	return devm_sunxi_ccu_probe(&pdev->dev, reg, desc);
239 }
240 
241 static const struct of_device_id sun50i_h6_r_ccu_ids[] = {
242 	{
243 		.compatible = "allwinner,sun50i-h6-r-ccu",
244 		.data = &sun50i_h6_r_ccu_desc,
245 	},
246 	{
247 		.compatible = "allwinner,sun50i-h616-r-ccu",
248 		.data = &sun50i_h616_r_ccu_desc,
249 	},
250 	{ }
251 };
252 
253 static struct platform_driver sun50i_h6_r_ccu_driver = {
254 	.probe	= sun50i_h6_r_ccu_probe,
255 	.driver	= {
256 		.name			= "sun50i-h6-r-ccu",
257 		.suppress_bind_attrs	= true,
258 		.of_match_table		= sun50i_h6_r_ccu_ids,
259 	},
260 };
261 module_platform_driver(sun50i_h6_r_ccu_driver);
262 
263 MODULE_IMPORT_NS(SUNXI_CCU);
264 MODULE_LICENSE("GPL");
265