1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 2016 Maxime Ripard
4  *
5  * Maxime Ripard <maxime.ripard@free-electrons.com>
6  */
7 
8 #ifndef _CCU_SUN50I_A64_H_
9 #define _CCU_SUN50I_A64_H_
10 
11 #include <dt-bindings/clock/sun50i-a64-ccu.h>
12 #include <dt-bindings/reset/sun50i-a64-ccu.h>
13 
14 #define CLK_OSC_12M			0
15 #define CLK_PLL_CPUX			1
16 #define CLK_PLL_AUDIO_BASE		2
17 #define CLK_PLL_AUDIO			3
18 #define CLK_PLL_AUDIO_2X		4
19 #define CLK_PLL_AUDIO_4X		5
20 #define CLK_PLL_AUDIO_8X		6
21 
22 /* PLL_VIDEO0 exported for HDMI PHY */
23 
24 #define CLK_PLL_VIDEO0_2X		8
25 #define CLK_PLL_VE			9
26 #define CLK_PLL_DDR0			10
27 
28 /* PLL_PERIPH0 exported for PRCM */
29 
30 #define CLK_PLL_PERIPH0_2X		12
31 #define CLK_PLL_PERIPH1			13
32 #define CLK_PLL_PERIPH1_2X		14
33 #define CLK_PLL_VIDEO1			15
34 #define CLK_PLL_GPU			16
35 #define CLK_PLL_MIPI			17
36 #define CLK_PLL_HSIC			18
37 #define CLK_PLL_DE			19
38 #define CLK_PLL_DDR1			20
39 #define CLK_AXI				22
40 #define CLK_APB				23
41 #define CLK_AHB1			24
42 #define CLK_APB1			25
43 #define CLK_APB2			26
44 #define CLK_AHB2			27
45 
46 /* All the bus gates are exported */
47 
48 /* The first bunch of module clocks are exported */
49 
50 #define CLK_USB_OHCI0_12M		90
51 
52 #define CLK_USB_OHCI1_12M		92
53 
54 #define CLK_DRAM			94
55 
56 /* All the DRAM gates are exported */
57 
58 /* Some more module clocks are exported */
59 
60 #define CLK_MBUS			112
61 
62 /* And the DSI and GPU module clock is exported */
63 
64 #define CLK_NUMBER			(CLK_GPU + 1)
65 
66 #endif /* _CCU_SUN50I_A64_H_ */
67