1 /* 2 * Copyright 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _CCU_SUN50I_A64_H_ 18 #define _CCU_SUN50I_A64_H_ 19 20 #include <dt-bindings/clock/sun50i-a64-ccu.h> 21 #include <dt-bindings/reset/sun50i-a64-ccu.h> 22 23 #define CLK_OSC_12M 0 24 #define CLK_PLL_CPUX 1 25 #define CLK_PLL_AUDIO_BASE 2 26 #define CLK_PLL_AUDIO 3 27 #define CLK_PLL_AUDIO_2X 4 28 #define CLK_PLL_AUDIO_4X 5 29 #define CLK_PLL_AUDIO_8X 6 30 31 /* PLL_VIDEO0 exported for HDMI PHY */ 32 33 #define CLK_PLL_VIDEO0_2X 8 34 #define CLK_PLL_VE 9 35 #define CLK_PLL_DDR0 10 36 37 /* PLL_PERIPH0 exported for PRCM */ 38 39 #define CLK_PLL_PERIPH0_2X 12 40 #define CLK_PLL_PERIPH1 13 41 #define CLK_PLL_PERIPH1_2X 14 42 #define CLK_PLL_VIDEO1 15 43 #define CLK_PLL_GPU 16 44 #define CLK_PLL_MIPI 17 45 #define CLK_PLL_HSIC 18 46 #define CLK_PLL_DE 19 47 #define CLK_PLL_DDR1 20 48 #define CLK_CPUX 21 49 #define CLK_AXI 22 50 #define CLK_APB 23 51 #define CLK_AHB1 24 52 #define CLK_APB1 25 53 #define CLK_APB2 26 54 #define CLK_AHB2 27 55 56 /* All the bus gates are exported */ 57 58 /* The first bunch of module clocks are exported */ 59 60 #define CLK_USB_OHCI0_12M 90 61 62 #define CLK_USB_OHCI1_12M 92 63 64 #define CLK_DRAM 94 65 66 /* All the DRAM gates are exported */ 67 68 /* Some more module clocks are exported */ 69 70 #define CLK_MBUS 112 71 72 /* And the DSI and GPU module clock is exported */ 73 74 #define CLK_NUMBER (CLK_GPU + 1) 75 76 #endif /* _CCU_SUN50I_A64_H_ */ 77