1c6a06374SMaxime Ripard /* 2c6a06374SMaxime Ripard * Copyright 2016 Maxime Ripard 3c6a06374SMaxime Ripard * 4c6a06374SMaxime Ripard * Maxime Ripard <maxime.ripard@free-electrons.com> 5c6a06374SMaxime Ripard * 6c6a06374SMaxime Ripard * This program is free software; you can redistribute it and/or modify 7c6a06374SMaxime Ripard * it under the terms of the GNU General Public License as published by 8c6a06374SMaxime Ripard * the Free Software Foundation; either version 2 of the License, or 9c6a06374SMaxime Ripard * (at your option) any later version. 10c6a06374SMaxime Ripard * 11c6a06374SMaxime Ripard * This program is distributed in the hope that it will be useful, 12c6a06374SMaxime Ripard * but WITHOUT ANY WARRANTY; without even the implied warranty of 13c6a06374SMaxime Ripard * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14c6a06374SMaxime Ripard * GNU General Public License for more details. 15c6a06374SMaxime Ripard */ 16c6a06374SMaxime Ripard 17c6a06374SMaxime Ripard #ifndef _CCU_SUN50I_A64_H_ 18c6a06374SMaxime Ripard #define _CCU_SUN50I_A64_H_ 19c6a06374SMaxime Ripard 20c6a06374SMaxime Ripard #include <dt-bindings/clock/sun50i-a64-ccu.h> 21c6a06374SMaxime Ripard #include <dt-bindings/reset/sun50i-a64-ccu.h> 22c6a06374SMaxime Ripard 23c6a06374SMaxime Ripard #define CLK_OSC_12M 0 24c6a06374SMaxime Ripard #define CLK_PLL_CPUX 1 25c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_BASE 2 26c6a06374SMaxime Ripard #define CLK_PLL_AUDIO 3 27c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_2X 4 28c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_4X 5 29c6a06374SMaxime Ripard #define CLK_PLL_AUDIO_8X 6 30c6a06374SMaxime Ripard #define CLK_PLL_VIDEO0 7 31c6a06374SMaxime Ripard #define CLK_PLL_VIDEO0_2X 8 32c6a06374SMaxime Ripard #define CLK_PLL_VE 9 33c6a06374SMaxime Ripard #define CLK_PLL_DDR0 10 34c6a06374SMaxime Ripard #define CLK_PLL_PERIPH0 11 35c6a06374SMaxime Ripard #define CLK_PLL_PERIPH0_2X 12 36c6a06374SMaxime Ripard #define CLK_PLL_PERIPH1 13 37c6a06374SMaxime Ripard #define CLK_PLL_PERIPH1_2X 14 38c6a06374SMaxime Ripard #define CLK_PLL_VIDEO1 15 39c6a06374SMaxime Ripard #define CLK_PLL_GPU 16 40c6a06374SMaxime Ripard #define CLK_PLL_MIPI 17 41c6a06374SMaxime Ripard #define CLK_PLL_HSIC 18 42c6a06374SMaxime Ripard #define CLK_PLL_DE 19 43c6a06374SMaxime Ripard #define CLK_PLL_DDR1 20 44c6a06374SMaxime Ripard #define CLK_CPUX 21 45c6a06374SMaxime Ripard #define CLK_AXI 22 46c6a06374SMaxime Ripard #define CLK_APB 23 47c6a06374SMaxime Ripard #define CLK_AHB1 24 48c6a06374SMaxime Ripard #define CLK_APB1 25 49c6a06374SMaxime Ripard #define CLK_APB2 26 50c6a06374SMaxime Ripard #define CLK_AHB2 27 51c6a06374SMaxime Ripard 52c6a06374SMaxime Ripard /* All the bus gates are exported */ 53c6a06374SMaxime Ripard 54c6a06374SMaxime Ripard /* The first bunch of module clocks are exported */ 55c6a06374SMaxime Ripard 56c6a06374SMaxime Ripard #define CLK_USB_OHCI0_12M 90 57c6a06374SMaxime Ripard 58c6a06374SMaxime Ripard #define CLK_USB_OHCI1_12M 92 59c6a06374SMaxime Ripard 60c6a06374SMaxime Ripard #define CLK_DRAM 94 61c6a06374SMaxime Ripard 62c6a06374SMaxime Ripard /* All the DRAM gates are exported */ 63c6a06374SMaxime Ripard 64c6a06374SMaxime Ripard /* Some more module clocks are exported */ 65c6a06374SMaxime Ripard 66c6a06374SMaxime Ripard #define CLK_MBUS 112 67c6a06374SMaxime Ripard 68c6a06374SMaxime Ripard /* And the DSI and GPU module clock is exported */ 69c6a06374SMaxime Ripard 70c6a06374SMaxime Ripard #define CLK_NUMBER (CLK_GPU + 1) 71c6a06374SMaxime Ripard 72c6a06374SMaxime Ripard #endif /* _CCU_SUN50I_A64_H_ */ 73