1 /* 2 * Copyright (c) 2016 Maxime Ripard. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/io.h> 16 #include <linux/of_address.h> 17 #include <linux/platform_device.h> 18 19 #include "ccu_common.h" 20 #include "ccu_reset.h" 21 22 #include "ccu_div.h" 23 #include "ccu_gate.h" 24 #include "ccu_mp.h" 25 #include "ccu_mult.h" 26 #include "ccu_nk.h" 27 #include "ccu_nkm.h" 28 #include "ccu_nkmp.h" 29 #include "ccu_nm.h" 30 #include "ccu_phase.h" 31 32 #include "ccu-sun50i-a64.h" 33 34 static struct ccu_nkmp pll_cpux_clk = { 35 .enable = BIT(31), 36 .lock = BIT(28), 37 .n = _SUNXI_CCU_MULT(8, 5), 38 .k = _SUNXI_CCU_MULT(4, 2), 39 .m = _SUNXI_CCU_DIV(0, 2), 40 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 41 .common = { 42 .reg = 0x000, 43 .hw.init = CLK_HW_INIT("pll-cpux", 44 "osc24M", 45 &ccu_nkmp_ops, 46 CLK_SET_RATE_UNGATE), 47 }, 48 }; 49 50 /* 51 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 52 * the base (2x, 4x and 8x), and one variable divider (the one true 53 * pll audio). 54 * 55 * With sigma-delta modulation for fractional-N on the audio PLL, 56 * we have to use specific dividers. This means the variable divider 57 * can no longer be used, as the audio codec requests the exact clock 58 * rates we support through this mechanism. So we now hard code the 59 * variable divider to 1. This means the clock rates will no longer 60 * match the clock names. 61 */ 62 #define SUN50I_A64_PLL_AUDIO_REG 0x008 63 64 static struct ccu_sdm_setting pll_audio_sdm_table[] = { 65 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 66 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 67 }; 68 69 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 70 "osc24M", 0x008, 71 8, 7, /* N */ 72 0, 5, /* M */ 73 pll_audio_sdm_table, BIT(24), 74 0x284, BIT(31), 75 BIT(31), /* gate */ 76 BIT(28), /* lock */ 77 CLK_SET_RATE_UNGATE); 78 79 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", 80 "osc24M", 0x010, 81 192000000, /* Minimum rate */ 82 1008000000, /* Maximum rate */ 83 8, 7, /* N */ 84 0, 4, /* M */ 85 BIT(24), /* frac enable */ 86 BIT(25), /* frac select */ 87 270000000, /* frac rate 0 */ 88 297000000, /* frac rate 1 */ 89 BIT(31), /* gate */ 90 BIT(28), /* lock */ 91 CLK_SET_RATE_UNGATE); 92 93 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 94 "osc24M", 0x018, 95 8, 7, /* N */ 96 0, 4, /* M */ 97 BIT(24), /* frac enable */ 98 BIT(25), /* frac select */ 99 270000000, /* frac rate 0 */ 100 297000000, /* frac rate 1 */ 101 BIT(31), /* gate */ 102 BIT(28), /* lock */ 103 CLK_SET_RATE_UNGATE); 104 105 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 106 "osc24M", 0x020, 107 8, 5, /* N */ 108 4, 2, /* K */ 109 0, 2, /* M */ 110 BIT(31), /* gate */ 111 BIT(28), /* lock */ 112 CLK_SET_RATE_UNGATE); 113 114 static struct ccu_nk pll_periph0_clk = { 115 .enable = BIT(31), 116 .lock = BIT(28), 117 .n = _SUNXI_CCU_MULT(8, 5), 118 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 119 .fixed_post_div = 2, 120 .common = { 121 .reg = 0x028, 122 .features = CCU_FEATURE_FIXED_POSTDIV, 123 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 124 &ccu_nk_ops, CLK_SET_RATE_UNGATE), 125 }, 126 }; 127 128 static struct ccu_nk pll_periph1_clk = { 129 .enable = BIT(31), 130 .lock = BIT(28), 131 .n = _SUNXI_CCU_MULT(8, 5), 132 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 133 .fixed_post_div = 2, 134 .common = { 135 .reg = 0x02c, 136 .features = CCU_FEATURE_FIXED_POSTDIV, 137 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 138 &ccu_nk_ops, CLK_SET_RATE_UNGATE), 139 }, 140 }; 141 142 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", 143 "osc24M", 0x030, 144 192000000, /* Minimum rate */ 145 1008000000, /* Maximum rate */ 146 8, 7, /* N */ 147 0, 4, /* M */ 148 BIT(24), /* frac enable */ 149 BIT(25), /* frac select */ 150 270000000, /* frac rate 0 */ 151 297000000, /* frac rate 1 */ 152 BIT(31), /* gate */ 153 BIT(28), /* lock */ 154 CLK_SET_RATE_UNGATE); 155 156 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 157 "osc24M", 0x038, 158 8, 7, /* N */ 159 0, 4, /* M */ 160 BIT(24), /* frac enable */ 161 BIT(25), /* frac select */ 162 270000000, /* frac rate 0 */ 163 297000000, /* frac rate 1 */ 164 BIT(31), /* gate */ 165 BIT(28), /* lock */ 166 CLK_SET_RATE_UNGATE); 167 168 /* 169 * The output function can be changed to something more complex that 170 * we do not handle yet. 171 * 172 * Hardcode the mode so that we don't fall in that case. 173 */ 174 #define SUN50I_A64_PLL_MIPI_REG 0x040 175 176 static struct ccu_nkm pll_mipi_clk = { 177 /* 178 * The bit 23 and 22 are called "LDO{1,2}_EN" on the SoC's 179 * user manual, and by experiments the PLL doesn't work without 180 * these bits toggled. 181 */ 182 .enable = BIT(31) | BIT(23) | BIT(22), 183 .lock = BIT(28), 184 .n = _SUNXI_CCU_MULT(8, 4), 185 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 186 .m = _SUNXI_CCU_DIV(0, 4), 187 .common = { 188 .reg = 0x040, 189 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0", 190 &ccu_nkm_ops, CLK_SET_RATE_UNGATE), 191 }, 192 }; 193 194 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", 195 "osc24M", 0x044, 196 8, 7, /* N */ 197 0, 4, /* M */ 198 BIT(24), /* frac enable */ 199 BIT(25), /* frac select */ 200 270000000, /* frac rate 0 */ 201 297000000, /* frac rate 1 */ 202 BIT(31), /* gate */ 203 BIT(28), /* lock */ 204 CLK_SET_RATE_UNGATE); 205 206 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 207 "osc24M", 0x048, 208 8, 7, /* N */ 209 0, 4, /* M */ 210 BIT(24), /* frac enable */ 211 BIT(25), /* frac select */ 212 270000000, /* frac rate 0 */ 213 297000000, /* frac rate 1 */ 214 BIT(31), /* gate */ 215 BIT(28), /* lock */ 216 CLK_SET_RATE_UNGATE); 217 218 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 219 "osc24M", 0x04c, 220 8, 7, /* N */ 221 0, 2, /* M */ 222 BIT(31), /* gate */ 223 BIT(28), /* lock */ 224 CLK_SET_RATE_UNGATE); 225 226 static const char * const cpux_parents[] = { "osc32k", "osc24M", 227 "pll-cpux", "pll-cpux" }; 228 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 229 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 230 231 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); 232 233 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 234 "axi", "pll-periph0" }; 235 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 236 { .index = 3, .shift = 6, .width = 2 }, 237 }; 238 static struct ccu_div ahb1_clk = { 239 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 240 241 .mux = { 242 .shift = 12, 243 .width = 2, 244 245 .var_predivs = ahb1_predivs, 246 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 247 }, 248 249 .common = { 250 .reg = 0x054, 251 .features = CCU_FEATURE_VARIABLE_PREDIV, 252 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 253 ahb1_parents, 254 &ccu_div_ops, 255 0), 256 }, 257 }; 258 259 static struct clk_div_table apb1_div_table[] = { 260 { .val = 0, .div = 2 }, 261 { .val = 1, .div = 2 }, 262 { .val = 2, .div = 4 }, 263 { .val = 3, .div = 8 }, 264 { /* Sentinel */ }, 265 }; 266 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 267 0x054, 8, 2, apb1_div_table, 0); 268 269 static const char * const apb2_parents[] = { "osc32k", "osc24M", 270 "pll-periph0-2x", 271 "pll-periph0-2x" }; 272 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 273 0, 5, /* M */ 274 16, 2, /* P */ 275 24, 2, /* mux */ 276 0); 277 278 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" }; 279 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { 280 { .index = 1, .div = 2 }, 281 }; 282 static struct ccu_mux ahb2_clk = { 283 .mux = { 284 .shift = 0, 285 .width = 1, 286 .fixed_predivs = ahb2_fixed_predivs, 287 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), 288 }, 289 290 .common = { 291 .reg = 0x05c, 292 .features = CCU_FEATURE_FIXED_PREDIV, 293 .hw.init = CLK_HW_INIT_PARENTS("ahb2", 294 ahb2_parents, 295 &ccu_mux_ops, 296 0), 297 }, 298 }; 299 300 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 301 0x060, BIT(1), 0); 302 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 303 0x060, BIT(5), 0); 304 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 305 0x060, BIT(6), 0); 306 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 307 0x060, BIT(8), 0); 308 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 309 0x060, BIT(9), 0); 310 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 311 0x060, BIT(10), 0); 312 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 313 0x060, BIT(13), 0); 314 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 315 0x060, BIT(14), 0); 316 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 317 0x060, BIT(17), 0); 318 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", 319 0x060, BIT(18), 0); 320 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 321 0x060, BIT(19), 0); 322 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 323 0x060, BIT(20), 0); 324 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 325 0x060, BIT(21), 0); 326 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 327 0x060, BIT(23), 0); 328 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 329 0x060, BIT(24), 0); 330 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", 331 0x060, BIT(25), 0); 332 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 333 0x060, BIT(28), 0); 334 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", 335 0x060, BIT(29), 0); 336 337 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 338 0x064, BIT(0), 0); 339 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 340 0x064, BIT(3), 0); 341 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", 342 0x064, BIT(4), 0); 343 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", 344 0x064, BIT(5), 0); 345 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 346 0x064, BIT(8), 0); 347 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", 348 0x064, BIT(11), 0); 349 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 350 0x064, BIT(12), 0); 351 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 352 0x064, BIT(20), 0); 353 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 354 0x064, BIT(21), 0); 355 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 356 0x064, BIT(22), 0); 357 358 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 359 0x068, BIT(0), 0); 360 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 361 0x068, BIT(1), 0); 362 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 363 0x068, BIT(5), 0); 364 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 365 0x068, BIT(8), 0); 366 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 367 0x068, BIT(12), 0); 368 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 369 0x068, BIT(13), 0); 370 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 371 0x068, BIT(14), 0); 372 373 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 374 0x06c, BIT(0), 0); 375 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 376 0x06c, BIT(1), 0); 377 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 378 0x06c, BIT(2), 0); 379 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 380 0x06c, BIT(5), 0); 381 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 382 0x06c, BIT(16), 0); 383 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 384 0x06c, BIT(17), 0); 385 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 386 0x06c, BIT(18), 0); 387 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 388 0x06c, BIT(19), 0); 389 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 390 0x06c, BIT(20), 0); 391 392 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 393 0x070, BIT(7), 0); 394 395 static struct clk_div_table ths_div_table[] = { 396 { .val = 0, .div = 1 }, 397 { .val = 1, .div = 2 }, 398 { .val = 2, .div = 4 }, 399 { .val = 3, .div = 6 }, 400 }; 401 static const char * const ths_parents[] = { "osc24M" }; 402 static struct ccu_div ths_clk = { 403 .enable = BIT(31), 404 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table), 405 .mux = _SUNXI_CCU_MUX(24, 2), 406 .common = { 407 .reg = 0x074, 408 .hw.init = CLK_HW_INIT_PARENTS("ths", 409 ths_parents, 410 &ccu_div_ops, 411 0), 412 }, 413 }; 414 415 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 416 "pll-periph1" }; 417 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 418 0, 4, /* M */ 419 16, 2, /* P */ 420 24, 2, /* mux */ 421 BIT(31), /* gate */ 422 0); 423 424 /* 425 * MMC clocks are the new timing mode (see A83T & H3) variety, but without 426 * the mode switch. This means they have a 2x post divider between the clock 427 * and the MMC module. This is not documented in the manual, but is taken 428 * into consideration when setting the mmc module clocks in the BSP kernel. 429 * Without it, MMC performance is degraded. 430 * 431 * We model it here to be consistent with other SoCs supporting this mode. 432 * The alternative would be to add the 2x multiplier when setting the MMC 433 * module clock in the MMC driver, just for the A64. 434 */ 435 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", 436 "pll-periph1-2x" }; 437 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", 438 mmc_default_parents, 0x088, 439 0, 4, /* M */ 440 16, 2, /* P */ 441 24, 2, /* mux */ 442 BIT(31), /* gate */ 443 2, /* post-div */ 444 0); 445 446 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", 447 mmc_default_parents, 0x08c, 448 0, 4, /* M */ 449 16, 2, /* P */ 450 24, 2, /* mux */ 451 BIT(31), /* gate */ 452 2, /* post-div */ 453 0); 454 455 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", 456 mmc_default_parents, 0x090, 457 0, 4, /* M */ 458 16, 2, /* P */ 459 24, 2, /* mux */ 460 BIT(31), /* gate */ 461 2, /* post-div */ 462 0); 463 464 static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; 465 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, 466 0, 4, /* M */ 467 16, 2, /* P */ 468 24, 4, /* mux */ 469 BIT(31), /* gate */ 470 0); 471 472 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, 473 0, 4, /* M */ 474 16, 2, /* P */ 475 24, 2, /* mux */ 476 BIT(31), /* gate */ 477 0); 478 479 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 480 0, 4, /* M */ 481 16, 2, /* P */ 482 24, 2, /* mux */ 483 BIT(31), /* gate */ 484 0); 485 486 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 487 0, 4, /* M */ 488 16, 2, /* P */ 489 24, 2, /* mux */ 490 BIT(31), /* gate */ 491 0); 492 493 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 494 "pll-audio-2x", "pll-audio" }; 495 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 496 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 497 498 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 499 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 500 501 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, 502 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 503 504 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 505 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 506 507 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 508 0x0cc, BIT(8), 0); 509 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 510 0x0cc, BIT(9), 0); 511 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 512 0x0cc, BIT(10), 0); 513 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 514 0x0cc, BIT(11), 0); 515 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 516 0x0cc, BIT(16), 0); 517 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", 518 0x0cc, BIT(17), 0); 519 520 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; 521 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 522 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); 523 524 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 525 0x100, BIT(0), 0); 526 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 527 0x100, BIT(1), 0); 528 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 529 0x100, BIT(2), 0); 530 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 531 0x100, BIT(3), 0); 532 533 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; 534 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 535 0x104, 0, 4, 24, 3, BIT(31), 536 CLK_SET_RATE_PARENT); 537 538 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; 539 static const u8 tcon0_table[] = { 0, 2, }; 540 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 541 tcon0_table, 0x118, 24, 3, BIT(31), 542 CLK_SET_RATE_PARENT); 543 544 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; 545 static const u8 tcon1_table[] = { 0, 2, }; 546 static struct ccu_div tcon1_clk = { 547 .enable = BIT(31), 548 .div = _SUNXI_CCU_DIV(0, 4), 549 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table), 550 .common = { 551 .reg = 0x11c, 552 .hw.init = CLK_HW_INIT_PARENTS("tcon1", 553 tcon1_parents, 554 &ccu_div_ops, 555 CLK_SET_RATE_PARENT), 556 }, 557 }; 558 559 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; 560 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, 561 0x124, 0, 4, 24, 3, BIT(31), 0); 562 563 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 564 0x130, BIT(31), 0); 565 566 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; 567 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 568 0x134, 16, 4, 24, 3, BIT(31), 0); 569 570 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" }; 571 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 572 0x134, 0, 5, 8, 3, BIT(15), 0); 573 574 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 575 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); 576 577 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 578 0x140, BIT(31), CLK_SET_RATE_PARENT); 579 580 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 581 0x140, BIT(30), CLK_SET_RATE_PARENT); 582 583 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 584 0x144, BIT(31), 0); 585 586 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; 587 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 588 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); 589 590 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 591 0x154, BIT(31), 0); 592 593 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 594 "pll-ddr0", "pll-ddr1" }; 595 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 596 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 597 598 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; 599 static const u8 dsi_dphy_table[] = { 0, 2, }; 600 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", 601 dsi_dphy_parents, dsi_dphy_table, 602 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT); 603 604 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 605 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 606 607 /* Fixed Factor clocks */ 608 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0); 609 610 /* We hardcode the divider to 1 for now */ 611 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 612 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 613 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 614 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 615 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 616 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 617 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 618 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 619 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", 620 "pll-periph0", 1, 2, 0); 621 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", 622 "pll-periph1", 1, 2, 0); 623 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", 624 "pll-video0", 1, 2, CLK_SET_RATE_PARENT); 625 626 static struct ccu_common *sun50i_a64_ccu_clks[] = { 627 &pll_cpux_clk.common, 628 &pll_audio_base_clk.common, 629 &pll_video0_clk.common, 630 &pll_ve_clk.common, 631 &pll_ddr0_clk.common, 632 &pll_periph0_clk.common, 633 &pll_periph1_clk.common, 634 &pll_video1_clk.common, 635 &pll_gpu_clk.common, 636 &pll_mipi_clk.common, 637 &pll_hsic_clk.common, 638 &pll_de_clk.common, 639 &pll_ddr1_clk.common, 640 &cpux_clk.common, 641 &axi_clk.common, 642 &ahb1_clk.common, 643 &apb1_clk.common, 644 &apb2_clk.common, 645 &ahb2_clk.common, 646 &bus_mipi_dsi_clk.common, 647 &bus_ce_clk.common, 648 &bus_dma_clk.common, 649 &bus_mmc0_clk.common, 650 &bus_mmc1_clk.common, 651 &bus_mmc2_clk.common, 652 &bus_nand_clk.common, 653 &bus_dram_clk.common, 654 &bus_emac_clk.common, 655 &bus_ts_clk.common, 656 &bus_hstimer_clk.common, 657 &bus_spi0_clk.common, 658 &bus_spi1_clk.common, 659 &bus_otg_clk.common, 660 &bus_ehci0_clk.common, 661 &bus_ehci1_clk.common, 662 &bus_ohci0_clk.common, 663 &bus_ohci1_clk.common, 664 &bus_ve_clk.common, 665 &bus_tcon0_clk.common, 666 &bus_tcon1_clk.common, 667 &bus_deinterlace_clk.common, 668 &bus_csi_clk.common, 669 &bus_hdmi_clk.common, 670 &bus_de_clk.common, 671 &bus_gpu_clk.common, 672 &bus_msgbox_clk.common, 673 &bus_spinlock_clk.common, 674 &bus_codec_clk.common, 675 &bus_spdif_clk.common, 676 &bus_pio_clk.common, 677 &bus_ths_clk.common, 678 &bus_i2s0_clk.common, 679 &bus_i2s1_clk.common, 680 &bus_i2s2_clk.common, 681 &bus_i2c0_clk.common, 682 &bus_i2c1_clk.common, 683 &bus_i2c2_clk.common, 684 &bus_scr_clk.common, 685 &bus_uart0_clk.common, 686 &bus_uart1_clk.common, 687 &bus_uart2_clk.common, 688 &bus_uart3_clk.common, 689 &bus_uart4_clk.common, 690 &bus_dbg_clk.common, 691 &ths_clk.common, 692 &nand_clk.common, 693 &mmc0_clk.common, 694 &mmc1_clk.common, 695 &mmc2_clk.common, 696 &ts_clk.common, 697 &ce_clk.common, 698 &spi0_clk.common, 699 &spi1_clk.common, 700 &i2s0_clk.common, 701 &i2s1_clk.common, 702 &i2s2_clk.common, 703 &spdif_clk.common, 704 &usb_phy0_clk.common, 705 &usb_phy1_clk.common, 706 &usb_hsic_clk.common, 707 &usb_hsic_12m_clk.common, 708 &usb_ohci0_clk.common, 709 &usb_ohci1_clk.common, 710 &dram_clk.common, 711 &dram_ve_clk.common, 712 &dram_csi_clk.common, 713 &dram_deinterlace_clk.common, 714 &dram_ts_clk.common, 715 &de_clk.common, 716 &tcon0_clk.common, 717 &tcon1_clk.common, 718 &deinterlace_clk.common, 719 &csi_misc_clk.common, 720 &csi_sclk_clk.common, 721 &csi_mclk_clk.common, 722 &ve_clk.common, 723 &ac_dig_clk.common, 724 &ac_dig_4x_clk.common, 725 &avs_clk.common, 726 &hdmi_clk.common, 727 &hdmi_ddc_clk.common, 728 &mbus_clk.common, 729 &dsi_dphy_clk.common, 730 &gpu_clk.common, 731 }; 732 733 static struct clk_hw_onecell_data sun50i_a64_hw_clks = { 734 .hws = { 735 [CLK_OSC_12M] = &osc12M_clk.hw, 736 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 737 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 738 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 739 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 740 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 741 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 742 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 743 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, 744 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 745 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 746 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 747 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 748 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 749 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 750 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 751 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 752 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 753 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 754 [CLK_PLL_DE] = &pll_de_clk.common.hw, 755 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 756 [CLK_CPUX] = &cpux_clk.common.hw, 757 [CLK_AXI] = &axi_clk.common.hw, 758 [CLK_AHB1] = &ahb1_clk.common.hw, 759 [CLK_APB1] = &apb1_clk.common.hw, 760 [CLK_APB2] = &apb2_clk.common.hw, 761 [CLK_AHB2] = &ahb2_clk.common.hw, 762 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 763 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 764 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 765 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 766 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 767 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 768 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 769 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 770 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 771 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 772 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 773 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 774 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 775 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 776 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 777 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 778 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 779 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 780 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 781 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 782 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, 783 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 784 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 785 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 786 [CLK_BUS_DE] = &bus_de_clk.common.hw, 787 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 788 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 789 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 790 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 791 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 792 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 793 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 794 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 795 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 796 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 797 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 798 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 799 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 800 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 801 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 802 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 803 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 804 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 805 [CLK_BUS_SCR] = &bus_scr_clk.common.hw, 806 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 807 [CLK_THS] = &ths_clk.common.hw, 808 [CLK_NAND] = &nand_clk.common.hw, 809 [CLK_MMC0] = &mmc0_clk.common.hw, 810 [CLK_MMC1] = &mmc1_clk.common.hw, 811 [CLK_MMC2] = &mmc2_clk.common.hw, 812 [CLK_TS] = &ts_clk.common.hw, 813 [CLK_CE] = &ce_clk.common.hw, 814 [CLK_SPI0] = &spi0_clk.common.hw, 815 [CLK_SPI1] = &spi1_clk.common.hw, 816 [CLK_I2S0] = &i2s0_clk.common.hw, 817 [CLK_I2S1] = &i2s1_clk.common.hw, 818 [CLK_I2S2] = &i2s2_clk.common.hw, 819 [CLK_SPDIF] = &spdif_clk.common.hw, 820 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 821 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 822 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 823 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, 824 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 825 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 826 [CLK_DRAM] = &dram_clk.common.hw, 827 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 828 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 829 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, 830 [CLK_DRAM_TS] = &dram_ts_clk.common.hw, 831 [CLK_DE] = &de_clk.common.hw, 832 [CLK_TCON0] = &tcon0_clk.common.hw, 833 [CLK_TCON1] = &tcon1_clk.common.hw, 834 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 835 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 836 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 837 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 838 [CLK_VE] = &ve_clk.common.hw, 839 [CLK_AC_DIG] = &ac_dig_clk.common.hw, 840 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, 841 [CLK_AVS] = &avs_clk.common.hw, 842 [CLK_HDMI] = &hdmi_clk.common.hw, 843 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, 844 [CLK_MBUS] = &mbus_clk.common.hw, 845 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, 846 [CLK_GPU] = &gpu_clk.common.hw, 847 }, 848 .num = CLK_NUMBER, 849 }; 850 851 static struct ccu_reset_map sun50i_a64_ccu_resets[] = { 852 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 853 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 854 [RST_USB_HSIC] = { 0x0cc, BIT(2) }, 855 856 [RST_DRAM] = { 0x0f4, BIT(31) }, 857 [RST_MBUS] = { 0x0fc, BIT(31) }, 858 859 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 860 [RST_BUS_CE] = { 0x2c0, BIT(5) }, 861 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 862 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 863 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 864 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 865 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 866 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 867 [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 868 [RST_BUS_TS] = { 0x2c0, BIT(18) }, 869 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 870 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 871 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 872 [RST_BUS_OTG] = { 0x2c0, BIT(23) }, 873 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, 874 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, 875 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, 876 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, 877 878 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 879 [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, 880 [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, 881 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, 882 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 883 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, 884 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, 885 [RST_BUS_DE] = { 0x2c4, BIT(12) }, 886 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 887 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, 888 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, 889 [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 890 891 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 892 893 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 894 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, 895 [RST_BUS_THS] = { 0x2d0, BIT(8) }, 896 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 897 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 898 [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, 899 900 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 901 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 902 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 903 [RST_BUS_SCR] = { 0x2d8, BIT(5) }, 904 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 905 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 906 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 907 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 908 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 909 }; 910 911 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { 912 .ccu_clks = sun50i_a64_ccu_clks, 913 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), 914 915 .hw_clks = &sun50i_a64_hw_clks, 916 917 .resets = sun50i_a64_ccu_resets, 918 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), 919 }; 920 921 static int sun50i_a64_ccu_probe(struct platform_device *pdev) 922 { 923 struct resource *res; 924 void __iomem *reg; 925 u32 val; 926 927 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 928 reg = devm_ioremap_resource(&pdev->dev, res); 929 if (IS_ERR(reg)) 930 return PTR_ERR(reg); 931 932 /* Force the PLL-Audio-1x divider to 1 */ 933 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); 934 val &= ~GENMASK(19, 16); 935 writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); 936 937 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); 938 939 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); 940 } 941 942 static const struct of_device_id sun50i_a64_ccu_ids[] = { 943 { .compatible = "allwinner,sun50i-a64-ccu" }, 944 { } 945 }; 946 947 static struct platform_driver sun50i_a64_ccu_driver = { 948 .probe = sun50i_a64_ccu_probe, 949 .driver = { 950 .name = "sun50i-a64-ccu", 951 .of_match_table = sun50i_a64_ccu_ids, 952 }, 953 }; 954 builtin_platform_driver(sun50i_a64_ccu_driver); 955