1 /* 2 * Copyright (c) 2016 Maxime Ripard. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/clk-provider.h> 15 #include <linux/of_address.h> 16 #include <linux/platform_device.h> 17 18 #include "ccu_common.h" 19 #include "ccu_reset.h" 20 21 #include "ccu_div.h" 22 #include "ccu_gate.h" 23 #include "ccu_mp.h" 24 #include "ccu_mult.h" 25 #include "ccu_nk.h" 26 #include "ccu_nkm.h" 27 #include "ccu_nkmp.h" 28 #include "ccu_nm.h" 29 #include "ccu_phase.h" 30 31 #include "ccu-sun50i-a64.h" 32 33 static struct ccu_nkmp pll_cpux_clk = { 34 .enable = BIT(31), 35 .lock = BIT(28), 36 .n = _SUNXI_CCU_MULT(8, 5), 37 .k = _SUNXI_CCU_MULT(4, 2), 38 .m = _SUNXI_CCU_DIV(0, 2), 39 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4), 40 .common = { 41 .reg = 0x000, 42 .hw.init = CLK_HW_INIT("pll-cpux", 43 "osc24M", 44 &ccu_nkmp_ops, 45 CLK_SET_RATE_UNGATE), 46 }, 47 }; 48 49 /* 50 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from 51 * the base (2x, 4x and 8x), and one variable divider (the one true 52 * pll audio). 53 * 54 * We don't have any need for the variable divider for now, so we just 55 * hardcode it to match with the clock names 56 */ 57 #define SUN50I_A64_PLL_AUDIO_REG 0x008 58 59 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", 60 "osc24M", 0x008, 61 8, 7, /* N */ 62 0, 5, /* M */ 63 BIT(31), /* gate */ 64 BIT(28), /* lock */ 65 CLK_SET_RATE_UNGATE); 66 67 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0", 68 "osc24M", 0x010, 69 192000000, /* Minimum rate */ 70 1008000000, /* Maximum rate */ 71 8, 7, /* N */ 72 0, 4, /* M */ 73 BIT(24), /* frac enable */ 74 BIT(25), /* frac select */ 75 270000000, /* frac rate 0 */ 76 297000000, /* frac rate 1 */ 77 BIT(31), /* gate */ 78 BIT(28), /* lock */ 79 CLK_SET_RATE_UNGATE); 80 81 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", 82 "osc24M", 0x018, 83 8, 7, /* N */ 84 0, 4, /* M */ 85 BIT(24), /* frac enable */ 86 BIT(25), /* frac select */ 87 270000000, /* frac rate 0 */ 88 297000000, /* frac rate 1 */ 89 BIT(31), /* gate */ 90 BIT(28), /* lock */ 91 CLK_SET_RATE_UNGATE); 92 93 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0", 94 "osc24M", 0x020, 95 8, 5, /* N */ 96 4, 2, /* K */ 97 0, 2, /* M */ 98 BIT(31), /* gate */ 99 BIT(28), /* lock */ 100 CLK_SET_RATE_UNGATE); 101 102 static struct ccu_nk pll_periph0_clk = { 103 .enable = BIT(31), 104 .lock = BIT(28), 105 .n = _SUNXI_CCU_MULT(8, 5), 106 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 107 .fixed_post_div = 2, 108 .common = { 109 .reg = 0x028, 110 .features = CCU_FEATURE_FIXED_POSTDIV, 111 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M", 112 &ccu_nk_ops, CLK_SET_RATE_UNGATE), 113 }, 114 }; 115 116 static struct ccu_nk pll_periph1_clk = { 117 .enable = BIT(31), 118 .lock = BIT(28), 119 .n = _SUNXI_CCU_MULT(8, 5), 120 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 121 .fixed_post_div = 2, 122 .common = { 123 .reg = 0x02c, 124 .features = CCU_FEATURE_FIXED_POSTDIV, 125 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M", 126 &ccu_nk_ops, CLK_SET_RATE_UNGATE), 127 }, 128 }; 129 130 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video1_clk, "pll-video1", 131 "osc24M", 0x030, 132 192000000, /* Minimum rate */ 133 1008000000, /* Maximum rate */ 134 8, 7, /* N */ 135 0, 4, /* M */ 136 BIT(24), /* frac enable */ 137 BIT(25), /* frac select */ 138 270000000, /* frac rate 0 */ 139 297000000, /* frac rate 1 */ 140 BIT(31), /* gate */ 141 BIT(28), /* lock */ 142 CLK_SET_RATE_UNGATE); 143 144 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", 145 "osc24M", 0x038, 146 8, 7, /* N */ 147 0, 4, /* M */ 148 BIT(24), /* frac enable */ 149 BIT(25), /* frac select */ 150 270000000, /* frac rate 0 */ 151 297000000, /* frac rate 1 */ 152 BIT(31), /* gate */ 153 BIT(28), /* lock */ 154 CLK_SET_RATE_UNGATE); 155 156 /* 157 * The output function can be changed to something more complex that 158 * we do not handle yet. 159 * 160 * Hardcode the mode so that we don't fall in that case. 161 */ 162 #define SUN50I_A64_PLL_MIPI_REG 0x040 163 164 static struct ccu_nkm pll_mipi_clk = { 165 .enable = BIT(31), 166 .lock = BIT(28), 167 .n = _SUNXI_CCU_MULT(8, 4), 168 .k = _SUNXI_CCU_MULT_MIN(4, 2, 2), 169 .m = _SUNXI_CCU_DIV(0, 4), 170 .common = { 171 .reg = 0x040, 172 .hw.init = CLK_HW_INIT("pll-mipi", "pll-video0", 173 &ccu_nkm_ops, CLK_SET_RATE_UNGATE), 174 }, 175 }; 176 177 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic", 178 "osc24M", 0x044, 179 8, 7, /* N */ 180 0, 4, /* M */ 181 BIT(24), /* frac enable */ 182 BIT(25), /* frac select */ 183 270000000, /* frac rate 0 */ 184 297000000, /* frac rate 1 */ 185 BIT(31), /* gate */ 186 BIT(28), /* lock */ 187 CLK_SET_RATE_UNGATE); 188 189 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de", 190 "osc24M", 0x048, 191 8, 7, /* N */ 192 0, 4, /* M */ 193 BIT(24), /* frac enable */ 194 BIT(25), /* frac select */ 195 270000000, /* frac rate 0 */ 196 297000000, /* frac rate 1 */ 197 BIT(31), /* gate */ 198 BIT(28), /* lock */ 199 CLK_SET_RATE_UNGATE); 200 201 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", 202 "osc24M", 0x04c, 203 8, 7, /* N */ 204 0, 2, /* M */ 205 BIT(31), /* gate */ 206 BIT(28), /* lock */ 207 CLK_SET_RATE_UNGATE); 208 209 static const char * const cpux_parents[] = { "osc32k", "osc24M", 210 "pll-cpux", "pll-cpux" }; 211 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, 212 0x050, 16, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); 213 214 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); 215 216 static const char * const ahb1_parents[] = { "osc32k", "osc24M", 217 "axi", "pll-periph0" }; 218 static const struct ccu_mux_var_prediv ahb1_predivs[] = { 219 { .index = 3, .shift = 6, .width = 2 }, 220 }; 221 static struct ccu_div ahb1_clk = { 222 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO), 223 224 .mux = { 225 .shift = 12, 226 .width = 2, 227 228 .var_predivs = ahb1_predivs, 229 .n_var_predivs = ARRAY_SIZE(ahb1_predivs), 230 }, 231 232 .common = { 233 .reg = 0x054, 234 .features = CCU_FEATURE_VARIABLE_PREDIV, 235 .hw.init = CLK_HW_INIT_PARENTS("ahb1", 236 ahb1_parents, 237 &ccu_div_ops, 238 0), 239 }, 240 }; 241 242 static struct clk_div_table apb1_div_table[] = { 243 { .val = 0, .div = 2 }, 244 { .val = 1, .div = 2 }, 245 { .val = 2, .div = 4 }, 246 { .val = 3, .div = 8 }, 247 { /* Sentinel */ }, 248 }; 249 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1", 250 0x054, 8, 2, apb1_div_table, 0); 251 252 static const char * const apb2_parents[] = { "osc32k", "osc24M", 253 "pll-periph0-2x", 254 "pll-periph0-2x" }; 255 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058, 256 0, 5, /* M */ 257 16, 2, /* P */ 258 24, 2, /* mux */ 259 0); 260 261 static const char * const ahb2_parents[] = { "ahb1", "pll-periph0" }; 262 static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = { 263 { .index = 1, .div = 2 }, 264 }; 265 static struct ccu_mux ahb2_clk = { 266 .mux = { 267 .shift = 0, 268 .width = 1, 269 .fixed_predivs = ahb2_fixed_predivs, 270 .n_predivs = ARRAY_SIZE(ahb2_fixed_predivs), 271 }, 272 273 .common = { 274 .reg = 0x05c, 275 .features = CCU_FEATURE_FIXED_PREDIV, 276 .hw.init = CLK_HW_INIT_PARENTS("ahb2", 277 ahb2_parents, 278 &ccu_mux_ops, 279 0), 280 }, 281 }; 282 283 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1", 284 0x060, BIT(1), 0); 285 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "ahb1", 286 0x060, BIT(5), 0); 287 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1", 288 0x060, BIT(6), 0); 289 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1", 290 0x060, BIT(8), 0); 291 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1", 292 0x060, BIT(9), 0); 293 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1", 294 0x060, BIT(10), 0); 295 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1", 296 0x060, BIT(13), 0); 297 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1", 298 0x060, BIT(14), 0); 299 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2", 300 0x060, BIT(17), 0); 301 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb1", 302 0x060, BIT(18), 0); 303 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1", 304 0x060, BIT(19), 0); 305 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1", 306 0x060, BIT(20), 0); 307 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1", 308 0x060, BIT(21), 0); 309 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1", 310 0x060, BIT(23), 0); 311 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb1", 312 0x060, BIT(24), 0); 313 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2", 314 0x060, BIT(25), 0); 315 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb1", 316 0x060, BIT(28), 0); 317 static SUNXI_CCU_GATE(bus_ohci1_clk, "bus-ohci1", "ahb2", 318 0x060, BIT(29), 0); 319 320 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1", 321 0x064, BIT(0), 0); 322 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1", 323 0x064, BIT(3), 0); 324 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1", 325 0x064, BIT(4), 0); 326 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "ahb1", 327 0x064, BIT(5), 0); 328 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1", 329 0x064, BIT(8), 0); 330 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1", 331 0x064, BIT(11), 0); 332 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1", 333 0x064, BIT(12), 0); 334 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1", 335 0x064, BIT(20), 0); 336 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1", 337 0x064, BIT(21), 0); 338 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1", 339 0x064, BIT(22), 0); 340 341 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1", 342 0x068, BIT(0), 0); 343 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 344 0x068, BIT(1), 0); 345 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1", 346 0x068, BIT(5), 0); 347 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 348 0x068, BIT(8), 0); 349 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 350 0x068, BIT(12), 0); 351 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 352 0x068, BIT(13), 0); 353 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 354 0x068, BIT(14), 0); 355 356 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 357 0x06c, BIT(0), 0); 358 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 359 0x06c, BIT(1), 0); 360 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 361 0x06c, BIT(2), 0); 362 static SUNXI_CCU_GATE(bus_scr_clk, "bus-scr", "apb2", 363 0x06c, BIT(5), 0); 364 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 365 0x06c, BIT(16), 0); 366 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 367 0x06c, BIT(17), 0); 368 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 369 0x06c, BIT(18), 0); 370 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 371 0x06c, BIT(19), 0); 372 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2", 373 0x06c, BIT(20), 0); 374 375 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "ahb1", 376 0x070, BIT(7), 0); 377 378 static struct clk_div_table ths_div_table[] = { 379 { .val = 0, .div = 1 }, 380 { .val = 1, .div = 2 }, 381 { .val = 2, .div = 4 }, 382 { .val = 3, .div = 6 }, 383 }; 384 static const char * const ths_parents[] = { "osc24M" }; 385 static struct ccu_div ths_clk = { 386 .enable = BIT(31), 387 .div = _SUNXI_CCU_DIV_TABLE(0, 2, ths_div_table), 388 .mux = _SUNXI_CCU_MUX(24, 2), 389 .common = { 390 .reg = 0x074, 391 .hw.init = CLK_HW_INIT_PARENTS("ths", 392 ths_parents, 393 &ccu_div_ops, 394 0), 395 }, 396 }; 397 398 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0", 399 "pll-periph1" }; 400 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 401 0, 4, /* M */ 402 16, 2, /* P */ 403 24, 2, /* mux */ 404 BIT(31), /* gate */ 405 0); 406 407 /* 408 * MMC clocks are the new timing mode (see A83T & H3) variety, but without 409 * the mode switch. This means they have a 2x post divider between the clock 410 * and the MMC module. This is not documented in the manual, but is taken 411 * into consideration when setting the mmc module clocks in the BSP kernel. 412 * Without it, MMC performance is degraded. 413 * 414 * We model it here to be consistent with other SoCs supporting this mode. 415 * The alternative would be to add the 2x multiplier when setting the MMC 416 * module clock in the MMC driver, just for the A64. 417 */ 418 static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x", 419 "pll-periph1-2x" }; 420 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", 421 mmc_default_parents, 0x088, 422 0, 4, /* M */ 423 16, 2, /* P */ 424 24, 2, /* mux */ 425 BIT(31), /* gate */ 426 2, /* post-div */ 427 0); 428 429 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", 430 mmc_default_parents, 0x08c, 431 0, 4, /* M */ 432 16, 2, /* P */ 433 24, 2, /* mux */ 434 BIT(31), /* gate */ 435 2, /* post-div */ 436 0); 437 438 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", 439 mmc_default_parents, 0x090, 440 0, 4, /* M */ 441 16, 2, /* P */ 442 24, 2, /* mux */ 443 BIT(31), /* gate */ 444 2, /* post-div */ 445 0); 446 447 static const char * const ts_parents[] = { "osc24M", "pll-periph0", }; 448 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x098, 449 0, 4, /* M */ 450 16, 2, /* P */ 451 24, 4, /* mux */ 452 BIT(31), /* gate */ 453 0); 454 455 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", mmc_default_parents, 0x09c, 456 0, 4, /* M */ 457 16, 2, /* P */ 458 24, 2, /* mux */ 459 BIT(31), /* gate */ 460 0); 461 462 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0, 463 0, 4, /* M */ 464 16, 2, /* P */ 465 24, 2, /* mux */ 466 BIT(31), /* gate */ 467 0); 468 469 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4, 470 0, 4, /* M */ 471 16, 2, /* P */ 472 24, 2, /* mux */ 473 BIT(31), /* gate */ 474 0); 475 476 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x", 477 "pll-audio-2x", "pll-audio" }; 478 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents, 479 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 480 481 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents, 482 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 483 484 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", i2s_parents, 485 0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT); 486 487 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio", 488 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT); 489 490 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 491 0x0cc, BIT(8), 0); 492 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 493 0x0cc, BIT(9), 0); 494 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 495 0x0cc, BIT(10), 0); 496 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 497 0x0cc, BIT(11), 0); 498 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 499 0x0cc, BIT(16), 0); 500 static SUNXI_CCU_GATE(usb_ohci1_clk, "usb-ohci1", "usb-ohci0", 501 0x0cc, BIT(17), 0); 502 503 static const char * const dram_parents[] = { "pll-ddr0", "pll-ddr1" }; 504 static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents, 505 0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL); 506 507 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram", 508 0x100, BIT(0), 0); 509 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram", 510 0x100, BIT(1), 0); 511 static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram", 512 0x100, BIT(2), 0); 513 static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram", 514 0x100, BIT(3), 0); 515 516 static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" }; 517 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 518 0x104, 0, 4, 24, 3, BIT(31), 0); 519 520 static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" }; 521 static const u8 tcon0_table[] = { 0, 2, }; 522 static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 523 tcon0_table, 0x118, 24, 3, BIT(31), 524 CLK_SET_RATE_PARENT); 525 526 static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" }; 527 static const u8 tcon1_table[] = { 0, 2, }; 528 static struct ccu_div tcon1_clk = { 529 .enable = BIT(31), 530 .div = _SUNXI_CCU_DIV(0, 4), 531 .mux = _SUNXI_CCU_MUX_TABLE(24, 2, tcon1_table), 532 .common = { 533 .reg = 0x11c, 534 .hw.init = CLK_HW_INIT_PARENTS("tcon1", 535 tcon1_parents, 536 &ccu_div_ops, 537 CLK_SET_RATE_PARENT), 538 }, 539 }; 540 541 static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" }; 542 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents, 543 0x124, 0, 4, 24, 3, BIT(31), 0); 544 545 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 546 0x130, BIT(31), 0); 547 548 static const char * const csi_sclk_parents[] = { "pll-periph0", "pll-periph1" }; 549 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents, 550 0x134, 16, 4, 24, 3, BIT(31), 0); 551 552 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video1", "pll-periph1" }; 553 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk", csi_mclk_parents, 554 0x134, 0, 5, 8, 3, BIT(15), 0); 555 556 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 557 0x13c, 16, 3, BIT(31), 0); 558 559 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", 560 0x140, BIT(31), CLK_SET_RATE_PARENT); 561 562 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 563 0x140, BIT(30), CLK_SET_RATE_PARENT); 564 565 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 566 0x144, BIT(31), 0); 567 568 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" }; 569 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 570 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT); 571 572 static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 573 0x154, BIT(31), 0); 574 575 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", 576 "pll-ddr0", "pll-ddr1" }; 577 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 578 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL); 579 580 static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" }; 581 static const u8 dsi_dphy_table[] = { 0, 2, }; 582 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy", 583 dsi_dphy_parents, dsi_dphy_table, 584 0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT); 585 586 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu", 587 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT); 588 589 /* Fixed Factor clocks */ 590 static CLK_FIXED_FACTOR(osc12M_clk, "osc12M", "osc24M", 2, 1, 0); 591 592 /* We hardcode the divider to 4 for now */ 593 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio", 594 "pll-audio-base", 4, 1, CLK_SET_RATE_PARENT); 595 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x", 596 "pll-audio-base", 2, 1, CLK_SET_RATE_PARENT); 597 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x", 598 "pll-audio-base", 1, 1, CLK_SET_RATE_PARENT); 599 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x", 600 "pll-audio-base", 1, 2, CLK_SET_RATE_PARENT); 601 static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x", 602 "pll-periph0", 1, 2, 0); 603 static CLK_FIXED_FACTOR(pll_periph1_2x_clk, "pll-periph1-2x", 604 "pll-periph1", 1, 2, 0); 605 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x", 606 "pll-video0", 1, 2, CLK_SET_RATE_PARENT); 607 608 static struct ccu_common *sun50i_a64_ccu_clks[] = { 609 &pll_cpux_clk.common, 610 &pll_audio_base_clk.common, 611 &pll_video0_clk.common, 612 &pll_ve_clk.common, 613 &pll_ddr0_clk.common, 614 &pll_periph0_clk.common, 615 &pll_periph1_clk.common, 616 &pll_video1_clk.common, 617 &pll_gpu_clk.common, 618 &pll_mipi_clk.common, 619 &pll_hsic_clk.common, 620 &pll_de_clk.common, 621 &pll_ddr1_clk.common, 622 &cpux_clk.common, 623 &axi_clk.common, 624 &ahb1_clk.common, 625 &apb1_clk.common, 626 &apb2_clk.common, 627 &ahb2_clk.common, 628 &bus_mipi_dsi_clk.common, 629 &bus_ce_clk.common, 630 &bus_dma_clk.common, 631 &bus_mmc0_clk.common, 632 &bus_mmc1_clk.common, 633 &bus_mmc2_clk.common, 634 &bus_nand_clk.common, 635 &bus_dram_clk.common, 636 &bus_emac_clk.common, 637 &bus_ts_clk.common, 638 &bus_hstimer_clk.common, 639 &bus_spi0_clk.common, 640 &bus_spi1_clk.common, 641 &bus_otg_clk.common, 642 &bus_ehci0_clk.common, 643 &bus_ehci1_clk.common, 644 &bus_ohci0_clk.common, 645 &bus_ohci1_clk.common, 646 &bus_ve_clk.common, 647 &bus_tcon0_clk.common, 648 &bus_tcon1_clk.common, 649 &bus_deinterlace_clk.common, 650 &bus_csi_clk.common, 651 &bus_hdmi_clk.common, 652 &bus_de_clk.common, 653 &bus_gpu_clk.common, 654 &bus_msgbox_clk.common, 655 &bus_spinlock_clk.common, 656 &bus_codec_clk.common, 657 &bus_spdif_clk.common, 658 &bus_pio_clk.common, 659 &bus_ths_clk.common, 660 &bus_i2s0_clk.common, 661 &bus_i2s1_clk.common, 662 &bus_i2s2_clk.common, 663 &bus_i2c0_clk.common, 664 &bus_i2c1_clk.common, 665 &bus_i2c2_clk.common, 666 &bus_scr_clk.common, 667 &bus_uart0_clk.common, 668 &bus_uart1_clk.common, 669 &bus_uart2_clk.common, 670 &bus_uart3_clk.common, 671 &bus_uart4_clk.common, 672 &bus_dbg_clk.common, 673 &ths_clk.common, 674 &nand_clk.common, 675 &mmc0_clk.common, 676 &mmc1_clk.common, 677 &mmc2_clk.common, 678 &ts_clk.common, 679 &ce_clk.common, 680 &spi0_clk.common, 681 &spi1_clk.common, 682 &i2s0_clk.common, 683 &i2s1_clk.common, 684 &i2s2_clk.common, 685 &spdif_clk.common, 686 &usb_phy0_clk.common, 687 &usb_phy1_clk.common, 688 &usb_hsic_clk.common, 689 &usb_hsic_12m_clk.common, 690 &usb_ohci0_clk.common, 691 &usb_ohci1_clk.common, 692 &dram_clk.common, 693 &dram_ve_clk.common, 694 &dram_csi_clk.common, 695 &dram_deinterlace_clk.common, 696 &dram_ts_clk.common, 697 &de_clk.common, 698 &tcon0_clk.common, 699 &tcon1_clk.common, 700 &deinterlace_clk.common, 701 &csi_misc_clk.common, 702 &csi_sclk_clk.common, 703 &csi_mclk_clk.common, 704 &ve_clk.common, 705 &ac_dig_clk.common, 706 &ac_dig_4x_clk.common, 707 &avs_clk.common, 708 &hdmi_clk.common, 709 &hdmi_ddc_clk.common, 710 &mbus_clk.common, 711 &dsi_dphy_clk.common, 712 &gpu_clk.common, 713 }; 714 715 static struct clk_hw_onecell_data sun50i_a64_hw_clks = { 716 .hws = { 717 [CLK_OSC_12M] = &osc12M_clk.hw, 718 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw, 719 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw, 720 [CLK_PLL_AUDIO] = &pll_audio_clk.hw, 721 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw, 722 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw, 723 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw, 724 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw, 725 [CLK_PLL_VIDEO0_2X] = &pll_video0_2x_clk.hw, 726 [CLK_PLL_VE] = &pll_ve_clk.common.hw, 727 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw, 728 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, 729 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, 730 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, 731 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, 732 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw, 733 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, 734 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw, 735 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw, 736 [CLK_PLL_DE] = &pll_de_clk.common.hw, 737 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, 738 [CLK_CPUX] = &cpux_clk.common.hw, 739 [CLK_AXI] = &axi_clk.common.hw, 740 [CLK_AHB1] = &ahb1_clk.common.hw, 741 [CLK_APB1] = &apb1_clk.common.hw, 742 [CLK_APB2] = &apb2_clk.common.hw, 743 [CLK_AHB2] = &ahb2_clk.common.hw, 744 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw, 745 [CLK_BUS_CE] = &bus_ce_clk.common.hw, 746 [CLK_BUS_DMA] = &bus_dma_clk.common.hw, 747 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, 748 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, 749 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, 750 [CLK_BUS_NAND] = &bus_nand_clk.common.hw, 751 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw, 752 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw, 753 [CLK_BUS_TS] = &bus_ts_clk.common.hw, 754 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw, 755 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, 756 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, 757 [CLK_BUS_OTG] = &bus_otg_clk.common.hw, 758 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, 759 [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, 760 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, 761 [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, 762 [CLK_BUS_VE] = &bus_ve_clk.common.hw, 763 [CLK_BUS_TCON0] = &bus_tcon0_clk.common.hw, 764 [CLK_BUS_TCON1] = &bus_tcon1_clk.common.hw, 765 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw, 766 [CLK_BUS_CSI] = &bus_csi_clk.common.hw, 767 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw, 768 [CLK_BUS_DE] = &bus_de_clk.common.hw, 769 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw, 770 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw, 771 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, 772 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw, 773 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, 774 [CLK_BUS_PIO] = &bus_pio_clk.common.hw, 775 [CLK_BUS_THS] = &bus_ths_clk.common.hw, 776 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw, 777 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw, 778 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw, 779 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, 780 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, 781 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, 782 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, 783 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, 784 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, 785 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, 786 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, 787 [CLK_BUS_SCR] = &bus_scr_clk.common.hw, 788 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, 789 [CLK_THS] = &ths_clk.common.hw, 790 [CLK_NAND] = &nand_clk.common.hw, 791 [CLK_MMC0] = &mmc0_clk.common.hw, 792 [CLK_MMC1] = &mmc1_clk.common.hw, 793 [CLK_MMC2] = &mmc2_clk.common.hw, 794 [CLK_TS] = &ts_clk.common.hw, 795 [CLK_CE] = &ce_clk.common.hw, 796 [CLK_SPI0] = &spi0_clk.common.hw, 797 [CLK_SPI1] = &spi1_clk.common.hw, 798 [CLK_I2S0] = &i2s0_clk.common.hw, 799 [CLK_I2S1] = &i2s1_clk.common.hw, 800 [CLK_I2S2] = &i2s2_clk.common.hw, 801 [CLK_SPDIF] = &spdif_clk.common.hw, 802 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw, 803 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw, 804 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw, 805 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw, 806 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, 807 [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, 808 [CLK_DRAM] = &dram_clk.common.hw, 809 [CLK_DRAM_VE] = &dram_ve_clk.common.hw, 810 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw, 811 [CLK_DRAM_DEINTERLACE] = &dram_deinterlace_clk.common.hw, 812 [CLK_DRAM_TS] = &dram_ts_clk.common.hw, 813 [CLK_DE] = &de_clk.common.hw, 814 [CLK_TCON0] = &tcon0_clk.common.hw, 815 [CLK_TCON1] = &tcon1_clk.common.hw, 816 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw, 817 [CLK_CSI_MISC] = &csi_misc_clk.common.hw, 818 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw, 819 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw, 820 [CLK_VE] = &ve_clk.common.hw, 821 [CLK_AC_DIG] = &ac_dig_clk.common.hw, 822 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw, 823 [CLK_AVS] = &avs_clk.common.hw, 824 [CLK_HDMI] = &hdmi_clk.common.hw, 825 [CLK_HDMI_DDC] = &hdmi_ddc_clk.common.hw, 826 [CLK_MBUS] = &mbus_clk.common.hw, 827 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw, 828 [CLK_GPU] = &gpu_clk.common.hw, 829 }, 830 .num = CLK_NUMBER, 831 }; 832 833 static struct ccu_reset_map sun50i_a64_ccu_resets[] = { 834 [RST_USB_PHY0] = { 0x0cc, BIT(0) }, 835 [RST_USB_PHY1] = { 0x0cc, BIT(1) }, 836 [RST_USB_HSIC] = { 0x0cc, BIT(2) }, 837 838 [RST_DRAM] = { 0x0f4, BIT(31) }, 839 [RST_MBUS] = { 0x0fc, BIT(31) }, 840 841 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) }, 842 [RST_BUS_CE] = { 0x2c0, BIT(5) }, 843 [RST_BUS_DMA] = { 0x2c0, BIT(6) }, 844 [RST_BUS_MMC0] = { 0x2c0, BIT(8) }, 845 [RST_BUS_MMC1] = { 0x2c0, BIT(9) }, 846 [RST_BUS_MMC2] = { 0x2c0, BIT(10) }, 847 [RST_BUS_NAND] = { 0x2c0, BIT(13) }, 848 [RST_BUS_DRAM] = { 0x2c0, BIT(14) }, 849 [RST_BUS_EMAC] = { 0x2c0, BIT(17) }, 850 [RST_BUS_TS] = { 0x2c0, BIT(18) }, 851 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) }, 852 [RST_BUS_SPI0] = { 0x2c0, BIT(20) }, 853 [RST_BUS_SPI1] = { 0x2c0, BIT(21) }, 854 [RST_BUS_OTG] = { 0x2c0, BIT(23) }, 855 [RST_BUS_EHCI0] = { 0x2c0, BIT(24) }, 856 [RST_BUS_EHCI1] = { 0x2c0, BIT(25) }, 857 [RST_BUS_OHCI0] = { 0x2c0, BIT(28) }, 858 [RST_BUS_OHCI1] = { 0x2c0, BIT(29) }, 859 860 [RST_BUS_VE] = { 0x2c4, BIT(0) }, 861 [RST_BUS_TCON0] = { 0x2c4, BIT(3) }, 862 [RST_BUS_TCON1] = { 0x2c4, BIT(4) }, 863 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) }, 864 [RST_BUS_CSI] = { 0x2c4, BIT(8) }, 865 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) }, 866 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) }, 867 [RST_BUS_DE] = { 0x2c4, BIT(12) }, 868 [RST_BUS_GPU] = { 0x2c4, BIT(20) }, 869 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) }, 870 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) }, 871 [RST_BUS_DBG] = { 0x2c4, BIT(31) }, 872 873 [RST_BUS_LVDS] = { 0x2c8, BIT(0) }, 874 875 [RST_BUS_CODEC] = { 0x2d0, BIT(0) }, 876 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) }, 877 [RST_BUS_THS] = { 0x2d0, BIT(8) }, 878 [RST_BUS_I2S0] = { 0x2d0, BIT(12) }, 879 [RST_BUS_I2S1] = { 0x2d0, BIT(13) }, 880 [RST_BUS_I2S2] = { 0x2d0, BIT(14) }, 881 882 [RST_BUS_I2C0] = { 0x2d8, BIT(0) }, 883 [RST_BUS_I2C1] = { 0x2d8, BIT(1) }, 884 [RST_BUS_I2C2] = { 0x2d8, BIT(2) }, 885 [RST_BUS_SCR] = { 0x2d8, BIT(5) }, 886 [RST_BUS_UART0] = { 0x2d8, BIT(16) }, 887 [RST_BUS_UART1] = { 0x2d8, BIT(17) }, 888 [RST_BUS_UART2] = { 0x2d8, BIT(18) }, 889 [RST_BUS_UART3] = { 0x2d8, BIT(19) }, 890 [RST_BUS_UART4] = { 0x2d8, BIT(20) }, 891 }; 892 893 static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = { 894 .ccu_clks = sun50i_a64_ccu_clks, 895 .num_ccu_clks = ARRAY_SIZE(sun50i_a64_ccu_clks), 896 897 .hw_clks = &sun50i_a64_hw_clks, 898 899 .resets = sun50i_a64_ccu_resets, 900 .num_resets = ARRAY_SIZE(sun50i_a64_ccu_resets), 901 }; 902 903 static int sun50i_a64_ccu_probe(struct platform_device *pdev) 904 { 905 struct resource *res; 906 void __iomem *reg; 907 u32 val; 908 909 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 910 reg = devm_ioremap_resource(&pdev->dev, res); 911 if (IS_ERR(reg)) 912 return PTR_ERR(reg); 913 914 /* Force the PLL-Audio-1x divider to 4 */ 915 val = readl(reg + SUN50I_A64_PLL_AUDIO_REG); 916 val &= ~GENMASK(19, 16); 917 writel(val | (3 << 16), reg + SUN50I_A64_PLL_AUDIO_REG); 918 919 writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG); 920 921 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc); 922 } 923 924 static const struct of_device_id sun50i_a64_ccu_ids[] = { 925 { .compatible = "allwinner,sun50i-a64-ccu" }, 926 { } 927 }; 928 929 static struct platform_driver sun50i_a64_ccu_driver = { 930 .probe = sun50i_a64_ccu_probe, 931 .driver = { 932 .name = "sun50i-a64-ccu", 933 .of_match_table = sun50i_a64_ccu_ids, 934 }, 935 }; 936 builtin_platform_driver(sun50i_a64_ccu_driver); 937