1fb038ce4SYangtao Li /* SPDX-License-Identifier: GPL-2.0 */ 2fb038ce4SYangtao Li /* 3fb038ce4SYangtao Li * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4fb038ce4SYangtao Li */ 5fb038ce4SYangtao Li 6fb038ce4SYangtao Li #ifndef _CCU_SUN50I_A100_H_ 7fb038ce4SYangtao Li #define _CCU_SUN50I_A100_H_ 8fb038ce4SYangtao Li 9fb038ce4SYangtao Li #include <dt-bindings/clock/sun50i-a100-ccu.h> 10fb038ce4SYangtao Li #include <dt-bindings/reset/sun50i-a100-ccu.h> 11fb038ce4SYangtao Li 12fb038ce4SYangtao Li #define CLK_OSC12M 0 13fb038ce4SYangtao Li #define CLK_PLL_CPUX 1 14fb038ce4SYangtao Li #define CLK_PLL_DDR0 2 15fb038ce4SYangtao Li 16fb038ce4SYangtao Li /* PLL_PERIPH0 exported for PRCM */ 17fb038ce4SYangtao Li 18fb038ce4SYangtao Li #define CLK_PLL_PERIPH0_2X 4 19fb038ce4SYangtao Li #define CLK_PLL_PERIPH1 5 20fb038ce4SYangtao Li #define CLK_PLL_PERIPH1_2X 6 21fb038ce4SYangtao Li #define CLK_PLL_GPU 7 22fb038ce4SYangtao Li #define CLK_PLL_VIDEO0 8 23fb038ce4SYangtao Li #define CLK_PLL_VIDEO0_2X 9 24fb038ce4SYangtao Li #define CLK_PLL_VIDEO0_4X 10 25fb038ce4SYangtao Li #define CLK_PLL_VIDEO1 11 26fb038ce4SYangtao Li #define CLK_PLL_VIDEO1_2X 12 27fb038ce4SYangtao Li #define CLK_PLL_VIDEO1_4X 13 28fb038ce4SYangtao Li #define CLK_PLL_VIDEO2 14 29fb038ce4SYangtao Li #define CLK_PLL_VIDEO2_2X 15 30fb038ce4SYangtao Li #define CLK_PLL_VIDEO2_4X 16 31fb038ce4SYangtao Li #define CLK_PLL_VIDEO3 17 32fb038ce4SYangtao Li #define CLK_PLL_VIDEO3_2X 18 33fb038ce4SYangtao Li #define CLK_PLL_VIDEO3_4X 19 34fb038ce4SYangtao Li #define CLK_PLL_VE 20 35fb038ce4SYangtao Li #define CLK_PLL_COM 21 36fb038ce4SYangtao Li #define CLK_PLL_COM_AUDIO 22 37fb038ce4SYangtao Li #define CLK_PLL_AUDIO 23 38fb038ce4SYangtao Li 39fb038ce4SYangtao Li /* CPUX clock exported for DVFS */ 40fb038ce4SYangtao Li 41fb038ce4SYangtao Li #define CLK_AXI 25 42fb038ce4SYangtao Li #define CLK_CPUX_APB 26 43fb038ce4SYangtao Li #define CLK_PSI_AHB1_AHB2 27 44fb038ce4SYangtao Li #define CLK_AHB3 28 45fb038ce4SYangtao Li 46fb038ce4SYangtao Li /* APB1 clock exported for PIO */ 47fb038ce4SYangtao Li 48fb038ce4SYangtao Li #define CLK_APB2 30 49fb038ce4SYangtao Li 50fb038ce4SYangtao Li /* All module clocks and bus gates are exported except DRAM */ 51fb038ce4SYangtao Li 52fb038ce4SYangtao Li #define CLK_BUS_DRAM 58 53fb038ce4SYangtao Li 54fb038ce4SYangtao Li #define CLK_NUMBER (CLK_CSI_ISP + 1) 55fb038ce4SYangtao Li 56fb038ce4SYangtao Li #endif /* _CCU_SUN50I_A100_H_ */ 57