1 /*
2  * Copyright 2017 Priit Laes
3  *
4  * Priit Laes <plaes@plaes.org>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #ifndef _CCU_SUN4I_A10_H_
18 #define _CCU_SUN4I_A10_H_
19 
20 #include <dt-bindings/clock/sun4i-a10-ccu.h>
21 #include <dt-bindings/clock/sun7i-a20-ccu.h>
22 #include <dt-bindings/reset/sun4i-a10-ccu.h>
23 
24 /* The HOSC is exported */
25 #define CLK_PLL_CORE		2
26 #define CLK_PLL_AUDIO_BASE	3
27 #define CLK_PLL_AUDIO		4
28 #define CLK_PLL_AUDIO_2X	5
29 #define CLK_PLL_AUDIO_4X	6
30 #define CLK_PLL_AUDIO_8X	7
31 #define CLK_PLL_VIDEO0		8
32 #define CLK_PLL_VIDEO0_2X	9
33 #define CLK_PLL_VE		10
34 #define CLK_PLL_DDR_BASE	11
35 #define CLK_PLL_DDR		12
36 #define CLK_PLL_DDR_OTHER	13
37 #define CLK_PLL_PERIPH_BASE	14
38 #define CLK_PLL_PERIPH		15
39 #define CLK_PLL_PERIPH_SATA	16
40 #define CLK_PLL_VIDEO1		17
41 #define CLK_PLL_VIDEO1_2X	18
42 #define CLK_PLL_GPU		19
43 
44 /* The CPU clock is exported */
45 #define CLK_AXI			21
46 #define CLK_AXI_DRAM		22
47 #define CLK_AHB			23
48 #define CLK_APB0		24
49 #define CLK_APB1		25
50 
51 /* AHB gates are exported (23..68) */
52 /* APB0 gates are exported (69..78) */
53 /* APB1 gates are exported (79..95) */
54 /* IP module clocks are exported (96..128) */
55 /* DRAM gates are exported (129..142)*/
56 /* Media (display engine clocks & etc) are exported (143..169) */
57 
58 #define CLK_NUMBER_SUN4I	(CLK_MBUS + 1)
59 #define CLK_NUMBER_SUN7I	(CLK_OUT_B + 1)
60 
61 #endif /* _CCU_SUN4I_A10_H_ */
62