1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2017 Priit Laes <plaes@plaes.org>.
4  * Copyright (c) 2017 Maxime Ripard.
5  * Copyright (c) 2017 Jonathan Liu.
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/io.h>
10 #include <linux/of_address.h>
11 
12 #include "ccu_common.h"
13 #include "ccu_reset.h"
14 
15 #include "ccu_div.h"
16 #include "ccu_gate.h"
17 #include "ccu_mp.h"
18 #include "ccu_mult.h"
19 #include "ccu_nk.h"
20 #include "ccu_nkm.h"
21 #include "ccu_nkmp.h"
22 #include "ccu_nm.h"
23 #include "ccu_phase.h"
24 #include "ccu_sdm.h"
25 
26 #include "ccu-sun4i-a10.h"
27 
28 static struct ccu_nkmp pll_core_clk = {
29 	.enable		= BIT(31),
30 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
31 	.k		= _SUNXI_CCU_MULT(4, 2),
32 	.m		= _SUNXI_CCU_DIV(0, 2),
33 	.p		= _SUNXI_CCU_DIV(16, 2),
34 	.common		= {
35 		.reg		= 0x000,
36 		.hw.init	= CLK_HW_INIT("pll-core",
37 					      "hosc",
38 					      &ccu_nkmp_ops,
39 					      0),
40 	},
41 };
42 
43 /*
44  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45  * the base (2x, 4x and 8x), and one variable divider (the one true
46  * pll audio).
47  *
48  * With sigma-delta modulation for fractional-N on the audio PLL,
49  * we have to use specific dividers. This means the variable divider
50  * can no longer be used, as the audio codec requests the exact clock
51  * rates we support through this mechanism. So we now hard code the
52  * variable divider to 1. This means the clock rates will no longer
53  * match the clock names.
54  */
55 #define SUN4I_PLL_AUDIO_REG	0x008
56 
57 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
58 	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
60 };
61 
62 static struct ccu_nm pll_audio_base_clk = {
63 	.enable		= BIT(31),
64 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
65 	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
66 	.sdm		= _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
67 					 0x00c, BIT(31)),
68 	.common		= {
69 		.reg		= 0x008,
70 		.features	= CCU_FEATURE_SIGMA_DELTA_MOD,
71 		.hw.init	= CLK_HW_INIT("pll-audio-base",
72 					      "hosc",
73 					      &ccu_nm_ops,
74 					      0),
75 	},
76 
77 };
78 
79 static struct ccu_mult pll_video0_clk = {
80 	.enable		= BIT(31),
81 	.mult		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
82 	.frac		= _SUNXI_CCU_FRAC(BIT(15), BIT(14),
83 					  270000000, 297000000),
84 	.common		= {
85 		.reg		= 0x010,
86 		.features	= (CCU_FEATURE_FRACTIONAL |
87 				   CCU_FEATURE_ALL_PREDIV),
88 		.prediv		= 8,
89 		.hw.init	= CLK_HW_INIT("pll-video0",
90 					      "hosc",
91 					      &ccu_mult_ops,
92 					      0),
93 	},
94 };
95 
96 static struct ccu_nkmp pll_ve_sun4i_clk = {
97 	.enable		= BIT(31),
98 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
99 	.k		= _SUNXI_CCU_MULT(4, 2),
100 	.m		= _SUNXI_CCU_DIV(0, 2),
101 	.p		= _SUNXI_CCU_DIV(16, 2),
102 	.common		= {
103 		.reg		= 0x018,
104 		.hw.init	= CLK_HW_INIT("pll-ve",
105 					      "hosc",
106 					      &ccu_nkmp_ops,
107 					      0),
108 	},
109 };
110 
111 static struct ccu_nk pll_ve_sun7i_clk = {
112 	.enable		= BIT(31),
113 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
114 	.k		= _SUNXI_CCU_MULT(4, 2),
115 	.common		= {
116 		.reg		= 0x018,
117 		.hw.init	= CLK_HW_INIT("pll-ve",
118 					      "hosc",
119 					      &ccu_nk_ops,
120 					      0),
121 	},
122 };
123 
124 static struct ccu_nk pll_ddr_base_clk = {
125 	.enable		= BIT(31),
126 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
127 	.k		= _SUNXI_CCU_MULT(4, 2),
128 	.common		= {
129 		.reg		= 0x020,
130 		.hw.init	= CLK_HW_INIT("pll-ddr-base",
131 					      "hosc",
132 					      &ccu_nk_ops,
133 					      0),
134 	},
135 };
136 
137 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
138 		   CLK_IS_CRITICAL);
139 
140 static struct ccu_div pll_ddr_other_clk = {
141 	.div		= _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
142 	.common		= {
143 		.reg		= 0x020,
144 		.hw.init	= CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
145 					      &ccu_div_ops,
146 					      0),
147 	},
148 };
149 
150 static struct ccu_nk pll_periph_base_clk = {
151 	.enable		= BIT(31),
152 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
153 	.k		= _SUNXI_CCU_MULT(4, 2),
154 	.common		= {
155 		.reg		= 0x028,
156 		.hw.init	= CLK_HW_INIT("pll-periph-base",
157 					      "hosc",
158 					      &ccu_nk_ops,
159 					      0),
160 	},
161 };
162 
163 static CLK_FIXED_FACTOR(pll_periph_clk, "pll-periph", "pll-periph-base",
164 			2, 1, CLK_SET_RATE_PARENT);
165 
166 /* Not documented on A10 */
167 static struct ccu_div pll_periph_sata_clk = {
168 	.enable		= BIT(14),
169 	.div		= _SUNXI_CCU_DIV(0, 2),
170 	.fixed_post_div	= 6,
171 	.common		= {
172 		.reg		= 0x028,
173 		.features	= CCU_FEATURE_FIXED_POSTDIV,
174 		.hw.init	= CLK_HW_INIT("pll-periph-sata",
175 					      "pll-periph-base",
176 					      &ccu_div_ops, 0),
177 	},
178 };
179 
180 static struct ccu_mult pll_video1_clk = {
181 	.enable		= BIT(31),
182 	.mult		= _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
183 	.frac		= _SUNXI_CCU_FRAC(BIT(15), BIT(14),
184 				  270000000, 297000000),
185 	.common		= {
186 		.reg		= 0x030,
187 		.features	= (CCU_FEATURE_FRACTIONAL |
188 				   CCU_FEATURE_ALL_PREDIV),
189 		.prediv		= 8,
190 		.hw.init	= CLK_HW_INIT("pll-video1",
191 					      "hosc",
192 					      &ccu_mult_ops,
193 					      0),
194 	},
195 };
196 
197 /* Not present on A10 */
198 static struct ccu_nk pll_gpu_clk = {
199 	.enable		= BIT(31),
200 	.n		= _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
201 	.k		= _SUNXI_CCU_MULT(4, 2),
202 	.common		= {
203 		.reg		= 0x040,
204 		.hw.init	= CLK_HW_INIT("pll-gpu",
205 					      "hosc",
206 					      &ccu_nk_ops,
207 					      0),
208 	},
209 };
210 
211 static SUNXI_CCU_GATE(hosc_clk,	"hosc",	"osc24M", 0x050, BIT(0), 0);
212 
213 static const char *const cpu_parents[] = { "osc32k", "hosc",
214 					   "pll-core", "pll-periph" };
215 static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
216 	{ .index = 3, .div = 3, },
217 };
218 
219 #define SUN4I_AHB_REG		0x054
220 static struct ccu_mux cpu_clk = {
221 	.mux		= {
222 		.shift		= 16,
223 		.width		= 2,
224 		.fixed_predivs	= cpu_predivs,
225 		.n_predivs	= ARRAY_SIZE(cpu_predivs),
226 	},
227 	.common		= {
228 		.reg		= 0x054,
229 		.features	= CCU_FEATURE_FIXED_PREDIV,
230 		.hw.init	= CLK_HW_INIT_PARENTS("cpu",
231 						      cpu_parents,
232 						      &ccu_mux_ops,
233 						      CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
234 	}
235 };
236 
237 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
238 
239 static struct ccu_div ahb_sun4i_clk = {
240 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
241 	.common		= {
242 		.reg		= 0x054,
243 		.hw.init	= CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
244 	},
245 };
246 
247 static const char *const ahb_sun7i_parents[] = { "axi", "pll-periph",
248 						 "pll-periph" };
249 static const struct ccu_mux_fixed_prediv ahb_sun7i_predivs[] = {
250 	{ .index = 1, .div = 2, },
251 	{ /* Sentinel */ },
252 };
253 static struct ccu_div ahb_sun7i_clk = {
254 	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
255 	.mux		= {
256 		.shift		= 6,
257 		.width		= 2,
258 		.fixed_predivs	= ahb_sun7i_predivs,
259 		.n_predivs	= ARRAY_SIZE(ahb_sun7i_predivs),
260 	},
261 
262 	.common		= {
263 		.reg		= 0x054,
264 		.hw.init	= CLK_HW_INIT_PARENTS("ahb",
265 						      ahb_sun7i_parents,
266 						      &ccu_div_ops,
267 						      0),
268 	},
269 };
270 
271 static struct clk_div_table apb0_div_table[] = {
272 	{ .val = 0, .div = 2 },
273 	{ .val = 1, .div = 2 },
274 	{ .val = 2, .div = 4 },
275 	{ .val = 3, .div = 8 },
276 	{ /* Sentinel */ },
277 };
278 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
279 			   0x054, 8, 2, apb0_div_table, 0);
280 
281 static const char *const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
282 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
283 			     0, 5,	/* M */
284 			     16, 2,	/* P */
285 			     24, 2,	/* mux */
286 			     0);
287 
288 /* Not present on A20 */
289 static SUNXI_CCU_GATE(axi_dram_clk,	"axi-dram",	"ahb",
290 		      0x05c, BIT(31), 0);
291 
292 static SUNXI_CCU_GATE(ahb_otg_clk,	"ahb-otg",	"ahb",
293 		      0x060, BIT(0), 0);
294 static SUNXI_CCU_GATE(ahb_ehci0_clk,	"ahb-ehci0",	"ahb",
295 		      0x060, BIT(1), 0);
296 static SUNXI_CCU_GATE(ahb_ohci0_clk,	"ahb-ohci0",	"ahb",
297 		      0x060, BIT(2), 0);
298 static SUNXI_CCU_GATE(ahb_ehci1_clk,	"ahb-ehci1",	"ahb",
299 		      0x060, BIT(3), 0);
300 static SUNXI_CCU_GATE(ahb_ohci1_clk,	"ahb-ohci1",	"ahb",
301 		      0x060, BIT(4), 0);
302 static SUNXI_CCU_GATE(ahb_ss_clk,	"ahb-ss",	"ahb",
303 		      0x060, BIT(5), 0);
304 static SUNXI_CCU_GATE(ahb_dma_clk,	"ahb-dma",	"ahb",
305 		      0x060, BIT(6), 0);
306 static SUNXI_CCU_GATE(ahb_bist_clk,	"ahb-bist",	"ahb",
307 		      0x060, BIT(7), 0);
308 static SUNXI_CCU_GATE(ahb_mmc0_clk,	"ahb-mmc0",	"ahb",
309 		      0x060, BIT(8), 0);
310 static SUNXI_CCU_GATE(ahb_mmc1_clk,	"ahb-mmc1",	"ahb",
311 		      0x060, BIT(9), 0);
312 static SUNXI_CCU_GATE(ahb_mmc2_clk,	"ahb-mmc2",	"ahb",
313 		      0x060, BIT(10), 0);
314 static SUNXI_CCU_GATE(ahb_mmc3_clk,	"ahb-mmc3",	"ahb",
315 		      0x060, BIT(11), 0);
316 static SUNXI_CCU_GATE(ahb_ms_clk,	"ahb-ms",	"ahb",
317 		      0x060, BIT(12), 0);
318 static SUNXI_CCU_GATE(ahb_nand_clk,	"ahb-nand",	"ahb",
319 		      0x060, BIT(13), 0);
320 static SUNXI_CCU_GATE(ahb_sdram_clk,	"ahb-sdram",	"ahb",
321 		      0x060, BIT(14), CLK_IS_CRITICAL);
322 
323 static SUNXI_CCU_GATE(ahb_ace_clk,	"ahb-ace",	"ahb",
324 		      0x060, BIT(16), 0);
325 static SUNXI_CCU_GATE(ahb_emac_clk,	"ahb-emac",	"ahb",
326 		      0x060, BIT(17), 0);
327 static SUNXI_CCU_GATE(ahb_ts_clk,	"ahb-ts",	"ahb",
328 		      0x060, BIT(18), 0);
329 static SUNXI_CCU_GATE(ahb_spi0_clk,	"ahb-spi0",	"ahb",
330 		      0x060, BIT(20), 0);
331 static SUNXI_CCU_GATE(ahb_spi1_clk,	"ahb-spi1",	"ahb",
332 		      0x060, BIT(21), 0);
333 static SUNXI_CCU_GATE(ahb_spi2_clk,	"ahb-spi2",	"ahb",
334 		      0x060, BIT(22), 0);
335 static SUNXI_CCU_GATE(ahb_spi3_clk,	"ahb-spi3",	"ahb",
336 		      0x060, BIT(23), 0);
337 static SUNXI_CCU_GATE(ahb_pata_clk,	"ahb-pata",	"ahb",
338 		      0x060, BIT(24), 0);
339 /* Not documented on A20 */
340 static SUNXI_CCU_GATE(ahb_sata_clk,	"ahb-sata",	"ahb",
341 		      0x060, BIT(25), 0);
342 /* Not present on A20 */
343 static SUNXI_CCU_GATE(ahb_gps_clk,	"ahb-gps",	"ahb",
344 		      0x060, BIT(26), 0);
345 /* Not present on A10 */
346 static SUNXI_CCU_GATE(ahb_hstimer_clk,	"ahb-hstimer",	"ahb",
347 		      0x060, BIT(28), 0);
348 
349 static SUNXI_CCU_GATE(ahb_ve_clk,	"ahb-ve",	"ahb",
350 		      0x064, BIT(0), 0);
351 static SUNXI_CCU_GATE(ahb_tvd_clk,	"ahb-tvd",	"ahb",
352 		      0x064, BIT(1), 0);
353 static SUNXI_CCU_GATE(ahb_tve0_clk,	"ahb-tve0",	"ahb",
354 		      0x064, BIT(2), 0);
355 static SUNXI_CCU_GATE(ahb_tve1_clk,	"ahb-tve1",	"ahb",
356 		      0x064, BIT(3), 0);
357 static SUNXI_CCU_GATE(ahb_lcd0_clk,	"ahb-lcd0",	"ahb",
358 		      0x064, BIT(4), 0);
359 static SUNXI_CCU_GATE(ahb_lcd1_clk,	"ahb-lcd1",	"ahb",
360 		      0x064, BIT(5), 0);
361 static SUNXI_CCU_GATE(ahb_csi0_clk,	"ahb-csi0",	"ahb",
362 		      0x064, BIT(8), 0);
363 static SUNXI_CCU_GATE(ahb_csi1_clk,	"ahb-csi1",	"ahb",
364 		      0x064, BIT(9), 0);
365 /* Not present on A10 */
366 static SUNXI_CCU_GATE(ahb_hdmi1_clk,	"ahb-hdmi1",	"ahb",
367 		      0x064, BIT(10), 0);
368 static SUNXI_CCU_GATE(ahb_hdmi0_clk,	"ahb-hdmi0",	"ahb",
369 		      0x064, BIT(11), 0);
370 static SUNXI_CCU_GATE(ahb_de_be0_clk,	"ahb-de-be0",	"ahb",
371 		      0x064, BIT(12), 0);
372 static SUNXI_CCU_GATE(ahb_de_be1_clk,	"ahb-de-be1",	"ahb",
373 		      0x064, BIT(13), 0);
374 static SUNXI_CCU_GATE(ahb_de_fe0_clk,	"ahb-de-fe0",	"ahb",
375 		      0x064, BIT(14), 0);
376 static SUNXI_CCU_GATE(ahb_de_fe1_clk,	"ahb-de-fe1",	"ahb",
377 		      0x064, BIT(15), 0);
378 /* Not present on A10 */
379 static SUNXI_CCU_GATE(ahb_gmac_clk,	"ahb-gmac",	"ahb",
380 		      0x064, BIT(17), 0);
381 static SUNXI_CCU_GATE(ahb_mp_clk,	"ahb-mp",	"ahb",
382 		      0x064, BIT(18), 0);
383 static SUNXI_CCU_GATE(ahb_gpu_clk,	"ahb-gpu",	"ahb",
384 		      0x064, BIT(20), 0);
385 
386 static SUNXI_CCU_GATE(apb0_codec_clk,	"apb0-codec",	"apb0",
387 		      0x068, BIT(0), 0);
388 static SUNXI_CCU_GATE(apb0_spdif_clk,	"apb0-spdif",	"apb0",
389 		      0x068, BIT(1), 0);
390 static SUNXI_CCU_GATE(apb0_ac97_clk,	"apb0-ac97",	"apb0",
391 		      0x068, BIT(2), 0);
392 static SUNXI_CCU_GATE(apb0_i2s0_clk,	"apb0-i2s0",	"apb0",
393 		      0x068, BIT(3), 0);
394 /* Not present on A10 */
395 static SUNXI_CCU_GATE(apb0_i2s1_clk,	"apb0-i2s1",	"apb0",
396 		      0x068, BIT(4), 0);
397 static SUNXI_CCU_GATE(apb0_pio_clk,	"apb0-pio",	"apb0",
398 		      0x068, BIT(5), 0);
399 static SUNXI_CCU_GATE(apb0_ir0_clk,	"apb0-ir0",	"apb0",
400 		      0x068, BIT(6), 0);
401 static SUNXI_CCU_GATE(apb0_ir1_clk,	"apb0-ir1",	"apb0",
402 		      0x068, BIT(7), 0);
403 /* Not present on A10 */
404 static SUNXI_CCU_GATE(apb0_i2s2_clk,	"apb0-i2s2",	"apb0",
405 		      0x068, BIT(8), 0);
406 static SUNXI_CCU_GATE(apb0_keypad_clk,	"apb0-keypad",	"apb0",
407 		      0x068, BIT(10), 0);
408 
409 static SUNXI_CCU_GATE(apb1_i2c0_clk,	"apb1-i2c0",	"apb1",
410 		      0x06c, BIT(0), 0);
411 static SUNXI_CCU_GATE(apb1_i2c1_clk,	"apb1-i2c1",	"apb1",
412 		      0x06c, BIT(1), 0);
413 static SUNXI_CCU_GATE(apb1_i2c2_clk,	"apb1-i2c2",	"apb1",
414 		      0x06c, BIT(2), 0);
415 /* Not present on A10 */
416 static SUNXI_CCU_GATE(apb1_i2c3_clk,	"apb1-i2c3",	"apb1",
417 		      0x06c, BIT(3), 0);
418 static SUNXI_CCU_GATE(apb1_can_clk,	"apb1-can",	"apb1",
419 		      0x06c, BIT(4), 0);
420 static SUNXI_CCU_GATE(apb1_scr_clk,	"apb1-scr",	"apb1",
421 		      0x06c, BIT(5), 0);
422 static SUNXI_CCU_GATE(apb1_ps20_clk,	"apb1-ps20",	"apb1",
423 		      0x06c, BIT(6), 0);
424 static SUNXI_CCU_GATE(apb1_ps21_clk,	"apb1-ps21",	"apb1",
425 		      0x06c, BIT(7), 0);
426 /* Not present on A10 */
427 static SUNXI_CCU_GATE(apb1_i2c4_clk,	"apb1-i2c4",	"apb1",
428 		      0x06c, BIT(15), 0);
429 static SUNXI_CCU_GATE(apb1_uart0_clk,	"apb1-uart0",	"apb1",
430 		      0x06c, BIT(16), 0);
431 static SUNXI_CCU_GATE(apb1_uart1_clk,	"apb1-uart1",	"apb1",
432 		      0x06c, BIT(17), 0);
433 static SUNXI_CCU_GATE(apb1_uart2_clk,	"apb1-uart2",	"apb1",
434 		      0x06c, BIT(18), 0);
435 static SUNXI_CCU_GATE(apb1_uart3_clk,	"apb1-uart3",	"apb1",
436 		      0x06c, BIT(19), 0);
437 static SUNXI_CCU_GATE(apb1_uart4_clk,	"apb1-uart4",	"apb1",
438 		      0x06c, BIT(20), 0);
439 static SUNXI_CCU_GATE(apb1_uart5_clk,	"apb1-uart5",	"apb1",
440 		      0x06c, BIT(21), 0);
441 static SUNXI_CCU_GATE(apb1_uart6_clk,	"apb1-uart6",	"apb1",
442 		      0x06c, BIT(22), 0);
443 static SUNXI_CCU_GATE(apb1_uart7_clk,	"apb1-uart7",	"apb1",
444 		      0x06c, BIT(23), 0);
445 
446 static const char *const mod0_default_parents[] = { "hosc", "pll-periph",
447 						     "pll-ddr-other" };
448 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
449 				  0, 4,		/* M */
450 				  16, 2,	/* P */
451 				  24, 2,	/* mux */
452 				  BIT(31),	/* gate */
453 				  0);
454 
455 /* Undocumented on A10 */
456 static SUNXI_CCU_MP_WITH_MUX_GATE(ms_clk, "ms", mod0_default_parents, 0x084,
457 				  0, 4,		/* M */
458 				  16, 2,	/* P */
459 				  24, 2,	/* mux */
460 				  BIT(31),	/* gate */
461 				  0);
462 
463 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
464 				  0, 4,		/* M */
465 				  16, 2,	/* P */
466 				  24, 2,	/* mux */
467 				  BIT(31),	/* gate */
468 				  0);
469 
470 /* MMC output and sample clocks are not present on A10 */
471 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
472 		       0x088, 8, 3, 0);
473 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
474 		       0x088, 20, 3, 0);
475 
476 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
477 				  0, 4,		/* M */
478 				  16, 2,	/* P */
479 				  24, 2,	/* mux */
480 				  BIT(31),	/* gate */
481 				  0);
482 
483 /* MMC output and sample clocks are not present on A10 */
484 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
485 		       0x08c, 8, 3, 0);
486 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
487 		       0x08c, 20, 3, 0);
488 
489 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
490 				  0, 4,		/* M */
491 				  16, 2,	/* P */
492 				  24, 2,	/* mux */
493 				  BIT(31),	/* gate */
494 				  0);
495 
496 /* MMC output and sample clocks are not present on A10 */
497 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
498 		       0x090, 8, 3, 0);
499 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
500 		       0x090, 20, 3, 0);
501 
502 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc3_clk, "mmc3", mod0_default_parents, 0x094,
503 				  0, 4,		/* M */
504 				  16, 2,	/* P */
505 				  24, 2,	/* mux */
506 				  BIT(31),	/* gate */
507 				  0);
508 
509 /* MMC output and sample clocks are not present on A10 */
510 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3_output", "mmc3",
511 		       0x094, 8, 3, 0);
512 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3_sample", "mmc3",
513 		       0x094, 20, 3, 0);
514 
515 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
516 				  0, 4,		/* M */
517 				  16, 2,	/* P */
518 				  24, 2,	/* mux */
519 				  BIT(31),	/* gate */
520 				  0);
521 
522 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
523 				  0, 4,		/* M */
524 				  16, 2,	/* P */
525 				  24, 2,	/* mux */
526 				  BIT(31),	/* gate */
527 				  0);
528 
529 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
530 				  0, 4,		/* M */
531 				  16, 2,	/* P */
532 				  24, 2,	/* mux */
533 				  BIT(31),	/* gate */
534 				  0);
535 
536 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
537 				  0, 4,		/* M */
538 				  16, 2,	/* P */
539 				  24, 2,	/* mux */
540 				  BIT(31),	/* gate */
541 				  0);
542 
543 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
544 				  0, 4,		/* M */
545 				  16, 2,	/* P */
546 				  24, 2,	/* mux */
547 				  BIT(31),	/* gate */
548 				  0);
549 
550 /* Undocumented on A10 */
551 static SUNXI_CCU_MP_WITH_MUX_GATE(pata_clk, "pata", mod0_default_parents, 0x0ac,
552 				  0, 4,		/* M */
553 				  16, 2,	/* P */
554 				  24, 2,	/* mux */
555 				  BIT(31),	/* gate */
556 				  0);
557 
558 /* TODO: Check whether A10 actually supports osc32k as 4th parent? */
559 static const char *const ir_parents_sun4i[] = { "hosc", "pll-periph",
560 						"pll-ddr-other" };
561 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun4i_clk, "ir0", ir_parents_sun4i, 0x0b0,
562 				  0, 4,		/* M */
563 				  16, 2,	/* P */
564 				  24, 2,	/* mux */
565 				  BIT(31),	/* gate */
566 				  0);
567 
568 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun4i_clk, "ir1", ir_parents_sun4i, 0x0b4,
569 				  0, 4,		/* M */
570 				  16, 2,	/* P */
571 				  24, 2,	/* mux */
572 				  BIT(31),	/* gate */
573 				  0);
574 static const char *const ir_parents_sun7i[] = { "hosc", "pll-periph",
575 						"pll-ddr-other", "osc32k" };
576 static SUNXI_CCU_MP_WITH_MUX_GATE(ir0_sun7i_clk, "ir0", ir_parents_sun7i, 0x0b0,
577 				  0, 4,		/* M */
578 				  16, 2,	/* P */
579 				  24, 2,	/* mux */
580 				  BIT(31),	/* gate */
581 				  0);
582 
583 static SUNXI_CCU_MP_WITH_MUX_GATE(ir1_sun7i_clk, "ir1", ir_parents_sun7i, 0x0b4,
584 				  0, 4,		/* M */
585 				  16, 2,	/* P */
586 				  24, 2,	/* mux */
587 				  BIT(31),	/* gate */
588 				  0);
589 
590 static const char *const audio_parents[] = { "pll-audio-8x", "pll-audio-4x",
591 					      "pll-audio-2x", "pll-audio" };
592 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", audio_parents,
593 			       0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
594 
595 static SUNXI_CCU_MUX_WITH_GATE(ac97_clk, "ac97", audio_parents,
596 			       0x0bc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
597 
598 /* Undocumented on A10 */
599 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", audio_parents,
600 			       0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
601 
602 static const char *const keypad_parents[] = { "hosc", "losc"};
603 static const u8 keypad_table[] = { 0, 2 };
604 static struct ccu_mp keypad_clk = {
605 	.enable		= BIT(31),
606 	.m		= _SUNXI_CCU_DIV(0, 5),
607 	.p		= _SUNXI_CCU_DIV(16, 2),
608 	.mux		= _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
609 	.common		= {
610 		.reg		= 0x0c4,
611 		.hw.init	= CLK_HW_INIT_PARENTS("keypad",
612 						      keypad_parents,
613 						      &ccu_mp_ops,
614 						      0),
615 	},
616 };
617 
618 /*
619  * SATA supports external clock as parent via BIT(24) and is probably an
620  * optional crystal or oscillator that can be connected to the
621  * SATA-CLKM / SATA-CLKP pins.
622  */
623 static const char *const sata_parents[] = {"pll-periph-sata", "sata-ext"};
624 static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
625 			       0x0c8, 24, 1, BIT(31), CLK_SET_RATE_PARENT);
626 
627 
628 static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"pll-periph",
629 		      0x0cc, BIT(6), 0);
630 static SUNXI_CCU_GATE(usb_ohci1_clk,	"usb-ohci1",	"pll-periph",
631 		      0x0cc, BIT(7), 0);
632 static SUNXI_CCU_GATE(usb_phy_clk,	"usb-phy",	"pll-periph",
633 		      0x0cc, BIT(8), 0);
634 
635 /* TODO: GPS CLK 0x0d0 */
636 
637 static SUNXI_CCU_MP_WITH_MUX_GATE(spi3_clk, "spi3", mod0_default_parents, 0x0d4,
638 				  0, 4,		/* M */
639 				  16, 2,	/* P */
640 				  24, 2,	/* mux */
641 				  BIT(31),	/* gate */
642 				  0);
643 
644 /* Not present on A10 */
645 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", audio_parents,
646 			       0x0d8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
647 
648 /* Not present on A10 */
649 static SUNXI_CCU_MUX_WITH_GATE(i2s2_clk, "i2s2", audio_parents,
650 			       0x0dc, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
651 
652 static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"pll-ddr",
653 		      0x100, BIT(0), 0);
654 static SUNXI_CCU_GATE(dram_csi0_clk,	"dram-csi0",	"pll-ddr",
655 		      0x100, BIT(1), 0);
656 static SUNXI_CCU_GATE(dram_csi1_clk,	"dram-csi1",	"pll-ddr",
657 		      0x100, BIT(2), 0);
658 static SUNXI_CCU_GATE(dram_ts_clk,	"dram-ts",	"pll-ddr",
659 		      0x100, BIT(3), 0);
660 static SUNXI_CCU_GATE(dram_tvd_clk,	"dram-tvd",	"pll-ddr",
661 		      0x100, BIT(4), 0);
662 static SUNXI_CCU_GATE(dram_tve0_clk,	"dram-tve0",	"pll-ddr",
663 		      0x100, BIT(5), 0);
664 static SUNXI_CCU_GATE(dram_tve1_clk,	"dram-tve1",	"pll-ddr",
665 		      0x100, BIT(6), 0);
666 
667 /* Clock seems to be critical only on sun4i */
668 static SUNXI_CCU_GATE(dram_out_clk,	"dram-out",	"pll-ddr",
669 		      0x100, BIT(15), CLK_IS_CRITICAL);
670 static SUNXI_CCU_GATE(dram_de_fe1_clk,	"dram-de-fe1",	"pll-ddr",
671 		      0x100, BIT(24), 0);
672 static SUNXI_CCU_GATE(dram_de_fe0_clk,	"dram-de-fe0",	"pll-ddr",
673 		      0x100, BIT(25), 0);
674 static SUNXI_CCU_GATE(dram_de_be0_clk,	"dram-de-be0",	"pll-ddr",
675 		      0x100, BIT(26), 0);
676 static SUNXI_CCU_GATE(dram_de_be1_clk,	"dram-de-be1",	"pll-ddr",
677 		      0x100, BIT(27), 0);
678 static SUNXI_CCU_GATE(dram_mp_clk,	"dram-mp",	"pll-ddr",
679 		      0x100, BIT(28), 0);
680 static SUNXI_CCU_GATE(dram_ace_clk,	"dram-ace",	"pll-ddr",
681 		      0x100, BIT(29), 0);
682 
683 static const char *const de_parents[] = { "pll-video0", "pll-video1",
684 					   "pll-ddr-other" };
685 static SUNXI_CCU_M_WITH_MUX_GATE(de_be0_clk, "de-be0", de_parents,
686 				 0x104, 0, 4, 24, 2, BIT(31), 0);
687 
688 static SUNXI_CCU_M_WITH_MUX_GATE(de_be1_clk, "de-be1", de_parents,
689 				 0x108, 0, 4, 24, 2, BIT(31), 0);
690 
691 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe0_clk, "de-fe0", de_parents,
692 				 0x10c, 0, 4, 24, 2, BIT(31), 0);
693 
694 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe1_clk, "de-fe1", de_parents,
695 				 0x110, 0, 4, 24, 2, BIT(31), 0);
696 
697 /* Undocumented on A10 */
698 static SUNXI_CCU_M_WITH_MUX_GATE(de_mp_clk, "de-mp", de_parents,
699 				 0x114, 0, 4, 24, 2, BIT(31), 0);
700 
701 static const char *const disp_parents[] = { "pll-video0", "pll-video1",
702 					    "pll-video0-2x", "pll-video1-2x" };
703 static SUNXI_CCU_MUX_WITH_GATE(tcon0_ch0_clk, "tcon0-ch0-sclk", disp_parents,
704 			       0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
705 static SUNXI_CCU_MUX_WITH_GATE(tcon1_ch0_clk, "tcon1-ch0-sclk", disp_parents,
706 			       0x11c, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
707 
708 static const char *const csi_sclk_parents[] = { "pll-video0", "pll-ve",
709 						"pll-ddr-other", "pll-periph" };
710 
711 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
712 				 csi_sclk_parents,
713 				 0x120, 0, 4, 24, 2, BIT(31), 0);
714 
715 /* TVD clock setup for A10 */
716 static const char *const tvd_parents[] = { "pll-video0", "pll-video1" };
717 static SUNXI_CCU_MUX_WITH_GATE(tvd_sun4i_clk, "tvd", tvd_parents,
718 			       0x128, 24, 1, BIT(31), 0);
719 
720 /* TVD clock setup for A20 */
721 static SUNXI_CCU_MP_WITH_MUX_GATE(tvd_sclk2_sun7i_clk,
722 				  "tvd-sclk2", tvd_parents,
723 				  0x128,
724 				  0, 4,		/* M */
725 				  16, 4,	/* P */
726 				  8, 1,		/* mux */
727 				  BIT(15),	/* gate */
728 				  0);
729 
730 static SUNXI_CCU_M_WITH_GATE(tvd_sclk1_sun7i_clk, "tvd-sclk1", "tvd-sclk2",
731 			     0x128, 0, 4, BIT(31), 0);
732 
733 static SUNXI_CCU_M_WITH_MUX_GATE(tcon0_ch1_sclk2_clk, "tcon0-ch1-sclk2",
734 				 disp_parents,
735 				 0x12c, 0, 4, 24, 2, BIT(31),
736 				 CLK_SET_RATE_PARENT);
737 
738 static SUNXI_CCU_M_WITH_GATE(tcon0_ch1_clk,
739 			     "tcon0-ch1-sclk1", "tcon0-ch1-sclk2",
740 			     0x12c, 11, 1, BIT(15),
741 			     CLK_SET_RATE_PARENT);
742 
743 static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_ch1_sclk2_clk, "tcon1-ch1-sclk2",
744 				 disp_parents,
745 				 0x130, 0, 4, 24, 2, BIT(31),
746 				 CLK_SET_RATE_PARENT);
747 
748 static SUNXI_CCU_M_WITH_GATE(tcon1_ch1_clk,
749 			     "tcon1-ch1-sclk1", "tcon1-ch1-sclk2",
750 			     0x130, 11, 1, BIT(15),
751 			     CLK_SET_RATE_PARENT);
752 
753 static const char *const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
754 					   "pll-video0-2x", "pll-video1-2x"};
755 static const u8 csi_table[] = { 0, 1, 2, 5, 6};
756 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_clk, "csi0",
757 				       csi_parents, csi_table,
758 				       0x134, 0, 5, 24, 3, BIT(31), 0);
759 
760 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_clk, "csi1",
761 				       csi_parents, csi_table,
762 				       0x138, 0, 5, 24, 3, BIT(31), 0);
763 
764 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 8, BIT(31), 0);
765 
766 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio",
767 		      0x140, BIT(31), CLK_SET_RATE_PARENT);
768 
769 static SUNXI_CCU_GATE(avs_clk, "avs", "hosc", 0x144, BIT(31), 0);
770 
771 static const char *const ace_parents[] = { "pll-ve", "pll-ddr-other" };
772 static SUNXI_CCU_M_WITH_MUX_GATE(ace_clk, "ace", ace_parents,
773 				 0x148, 0, 4, 24, 1, BIT(31), 0);
774 
775 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", disp_parents,
776 				 0x150, 0, 4, 24, 2, BIT(31),
777 				 CLK_SET_RATE_PARENT);
778 
779 static const char *const gpu_parents_sun4i[] = { "pll-video0", "pll-ve",
780 						 "pll-ddr-other",
781 						 "pll-video1" };
782 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_sun4i_clk, "gpu", gpu_parents_sun4i,
783 				 0x154, 0, 4, 24, 2, BIT(31),
784 				 CLK_SET_RATE_PARENT);
785 
786 static const char *const gpu_parents_sun7i[] = { "pll-video0", "pll-ve",
787 						 "pll-ddr-other", "pll-video1",
788 						 "pll-gpu" };
789 static const u8 gpu_table_sun7i[] = { 0, 1, 2, 3, 4 };
790 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_sun7i_clk, "gpu",
791 				       gpu_parents_sun7i, gpu_table_sun7i,
792 				       0x154, 0, 4, 24, 3, BIT(31),
793 				       CLK_SET_RATE_PARENT);
794 
795 static const char *const mbus_sun4i_parents[] = { "hosc", "pll-periph",
796 						  "pll-ddr-other" };
797 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun4i_clk, "mbus", mbus_sun4i_parents,
798 				  0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
799 				  0);
800 static const char *const mbus_sun7i_parents[] = { "hosc", "pll-periph-base",
801 						  "pll-ddr-other" };
802 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_sun7i_clk, "mbus", mbus_sun7i_parents,
803 				  0x15c, 0, 4, 16, 2, 24, 2, BIT(31),
804 				  CLK_IS_CRITICAL);
805 
806 static SUNXI_CCU_GATE(hdmi1_slow_clk, "hdmi1-slow", "hosc", 0x178, BIT(31), 0);
807 
808 static const char *const hdmi1_parents[] = { "pll-video0", "pll-video1" };
809 static const u8 hdmi1_table[] = { 0, 1};
810 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi1_clk, "hdmi1",
811 				       hdmi1_parents, hdmi1_table,
812 				       0x17c, 0, 4, 24, 2, BIT(31),
813 				       CLK_SET_RATE_PARENT);
814 
815 static const char *const out_parents[] = { "hosc", "osc32k", "hosc" };
816 static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
817 	{ .index = 0, .div = 750, },
818 };
819 
820 static struct ccu_mp out_a_clk = {
821 	.enable		= BIT(31),
822 	.m		= _SUNXI_CCU_DIV(8, 5),
823 	.p		= _SUNXI_CCU_DIV(20, 2),
824 	.mux		= {
825 		.shift		= 24,
826 		.width		= 2,
827 		.fixed_predivs	= clk_out_predivs,
828 		.n_predivs	= ARRAY_SIZE(clk_out_predivs),
829 	},
830 	.common		= {
831 		.reg		= 0x1f0,
832 		.features	= CCU_FEATURE_FIXED_PREDIV,
833 		.hw.init	= CLK_HW_INIT_PARENTS("out-a",
834 						      out_parents,
835 						      &ccu_mp_ops,
836 						      0),
837 	},
838 };
839 static struct ccu_mp out_b_clk = {
840 	.enable		= BIT(31),
841 	.m		= _SUNXI_CCU_DIV(8, 5),
842 	.p		= _SUNXI_CCU_DIV(20, 2),
843 	.mux		= {
844 		.shift		= 24,
845 		.width		= 2,
846 		.fixed_predivs	= clk_out_predivs,
847 		.n_predivs	= ARRAY_SIZE(clk_out_predivs),
848 	},
849 	.common		= {
850 		.reg		= 0x1f4,
851 		.features	= CCU_FEATURE_FIXED_PREDIV,
852 		.hw.init	= CLK_HW_INIT_PARENTS("out-b",
853 						      out_parents,
854 						      &ccu_mp_ops,
855 						      0),
856 	},
857 };
858 
859 static struct ccu_common *sun4i_sun7i_ccu_clks[] = {
860 	&hosc_clk.common,
861 	&pll_core_clk.common,
862 	&pll_audio_base_clk.common,
863 	&pll_video0_clk.common,
864 	&pll_ve_sun4i_clk.common,
865 	&pll_ve_sun7i_clk.common,
866 	&pll_ddr_base_clk.common,
867 	&pll_ddr_clk.common,
868 	&pll_ddr_other_clk.common,
869 	&pll_periph_base_clk.common,
870 	&pll_periph_sata_clk.common,
871 	&pll_video1_clk.common,
872 	&pll_gpu_clk.common,
873 	&cpu_clk.common,
874 	&axi_clk.common,
875 	&axi_dram_clk.common,
876 	&ahb_sun4i_clk.common,
877 	&ahb_sun7i_clk.common,
878 	&apb0_clk.common,
879 	&apb1_clk.common,
880 	&ahb_otg_clk.common,
881 	&ahb_ehci0_clk.common,
882 	&ahb_ohci0_clk.common,
883 	&ahb_ehci1_clk.common,
884 	&ahb_ohci1_clk.common,
885 	&ahb_ss_clk.common,
886 	&ahb_dma_clk.common,
887 	&ahb_bist_clk.common,
888 	&ahb_mmc0_clk.common,
889 	&ahb_mmc1_clk.common,
890 	&ahb_mmc2_clk.common,
891 	&ahb_mmc3_clk.common,
892 	&ahb_ms_clk.common,
893 	&ahb_nand_clk.common,
894 	&ahb_sdram_clk.common,
895 	&ahb_ace_clk.common,
896 	&ahb_emac_clk.common,
897 	&ahb_ts_clk.common,
898 	&ahb_spi0_clk.common,
899 	&ahb_spi1_clk.common,
900 	&ahb_spi2_clk.common,
901 	&ahb_spi3_clk.common,
902 	&ahb_pata_clk.common,
903 	&ahb_sata_clk.common,
904 	&ahb_gps_clk.common,
905 	&ahb_hstimer_clk.common,
906 	&ahb_ve_clk.common,
907 	&ahb_tvd_clk.common,
908 	&ahb_tve0_clk.common,
909 	&ahb_tve1_clk.common,
910 	&ahb_lcd0_clk.common,
911 	&ahb_lcd1_clk.common,
912 	&ahb_csi0_clk.common,
913 	&ahb_csi1_clk.common,
914 	&ahb_hdmi1_clk.common,
915 	&ahb_hdmi0_clk.common,
916 	&ahb_de_be0_clk.common,
917 	&ahb_de_be1_clk.common,
918 	&ahb_de_fe0_clk.common,
919 	&ahb_de_fe1_clk.common,
920 	&ahb_gmac_clk.common,
921 	&ahb_mp_clk.common,
922 	&ahb_gpu_clk.common,
923 	&apb0_codec_clk.common,
924 	&apb0_spdif_clk.common,
925 	&apb0_ac97_clk.common,
926 	&apb0_i2s0_clk.common,
927 	&apb0_i2s1_clk.common,
928 	&apb0_pio_clk.common,
929 	&apb0_ir0_clk.common,
930 	&apb0_ir1_clk.common,
931 	&apb0_i2s2_clk.common,
932 	&apb0_keypad_clk.common,
933 	&apb1_i2c0_clk.common,
934 	&apb1_i2c1_clk.common,
935 	&apb1_i2c2_clk.common,
936 	&apb1_i2c3_clk.common,
937 	&apb1_can_clk.common,
938 	&apb1_scr_clk.common,
939 	&apb1_ps20_clk.common,
940 	&apb1_ps21_clk.common,
941 	&apb1_i2c4_clk.common,
942 	&apb1_uart0_clk.common,
943 	&apb1_uart1_clk.common,
944 	&apb1_uart2_clk.common,
945 	&apb1_uart3_clk.common,
946 	&apb1_uart4_clk.common,
947 	&apb1_uart5_clk.common,
948 	&apb1_uart6_clk.common,
949 	&apb1_uart7_clk.common,
950 	&nand_clk.common,
951 	&ms_clk.common,
952 	&mmc0_clk.common,
953 	&mmc0_output_clk.common,
954 	&mmc0_sample_clk.common,
955 	&mmc1_clk.common,
956 	&mmc1_output_clk.common,
957 	&mmc1_sample_clk.common,
958 	&mmc2_clk.common,
959 	&mmc2_output_clk.common,
960 	&mmc2_sample_clk.common,
961 	&mmc3_clk.common,
962 	&mmc3_output_clk.common,
963 	&mmc3_sample_clk.common,
964 	&ts_clk.common,
965 	&ss_clk.common,
966 	&spi0_clk.common,
967 	&spi1_clk.common,
968 	&spi2_clk.common,
969 	&pata_clk.common,
970 	&ir0_sun4i_clk.common,
971 	&ir1_sun4i_clk.common,
972 	&ir0_sun7i_clk.common,
973 	&ir1_sun7i_clk.common,
974 	&i2s0_clk.common,
975 	&ac97_clk.common,
976 	&spdif_clk.common,
977 	&keypad_clk.common,
978 	&sata_clk.common,
979 	&usb_ohci0_clk.common,
980 	&usb_ohci1_clk.common,
981 	&usb_phy_clk.common,
982 	&spi3_clk.common,
983 	&i2s1_clk.common,
984 	&i2s2_clk.common,
985 	&dram_ve_clk.common,
986 	&dram_csi0_clk.common,
987 	&dram_csi1_clk.common,
988 	&dram_ts_clk.common,
989 	&dram_tvd_clk.common,
990 	&dram_tve0_clk.common,
991 	&dram_tve1_clk.common,
992 	&dram_out_clk.common,
993 	&dram_de_fe1_clk.common,
994 	&dram_de_fe0_clk.common,
995 	&dram_de_be0_clk.common,
996 	&dram_de_be1_clk.common,
997 	&dram_mp_clk.common,
998 	&dram_ace_clk.common,
999 	&de_be0_clk.common,
1000 	&de_be1_clk.common,
1001 	&de_fe0_clk.common,
1002 	&de_fe1_clk.common,
1003 	&de_mp_clk.common,
1004 	&tcon0_ch0_clk.common,
1005 	&tcon1_ch0_clk.common,
1006 	&csi_sclk_clk.common,
1007 	&tvd_sun4i_clk.common,
1008 	&tvd_sclk1_sun7i_clk.common,
1009 	&tvd_sclk2_sun7i_clk.common,
1010 	&tcon0_ch1_sclk2_clk.common,
1011 	&tcon0_ch1_clk.common,
1012 	&tcon1_ch1_sclk2_clk.common,
1013 	&tcon1_ch1_clk.common,
1014 	&csi0_clk.common,
1015 	&csi1_clk.common,
1016 	&ve_clk.common,
1017 	&codec_clk.common,
1018 	&avs_clk.common,
1019 	&ace_clk.common,
1020 	&hdmi_clk.common,
1021 	&gpu_sun4i_clk.common,
1022 	&gpu_sun7i_clk.common,
1023 	&mbus_sun4i_clk.common,
1024 	&mbus_sun7i_clk.common,
1025 	&hdmi1_slow_clk.common,
1026 	&hdmi1_clk.common,
1027 	&out_a_clk.common,
1028 	&out_b_clk.common
1029 };
1030 
1031 /* Post-divider for pll-audio is hardcoded to 1 */
1032 static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
1033 			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1034 static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
1035 			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
1036 static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
1037 			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
1038 static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
1039 			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
1040 static CLK_FIXED_FACTOR(pll_video0_2x_clk, "pll-video0-2x",
1041 			"pll-video0", 1, 2, CLK_SET_RATE_PARENT);
1042 static CLK_FIXED_FACTOR(pll_video1_2x_clk, "pll-video1-2x",
1043 			"pll-video1", 1, 2, CLK_SET_RATE_PARENT);
1044 
1045 
1046 static struct clk_hw_onecell_data sun4i_a10_hw_clks = {
1047 	.hws	= {
1048 		[CLK_HOSC]		= &hosc_clk.common.hw,
1049 		[CLK_PLL_CORE]		= &pll_core_clk.common.hw,
1050 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
1051 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
1052 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
1053 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
1054 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
1055 		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
1056 		[CLK_PLL_VIDEO0_2X]	= &pll_video0_2x_clk.hw,
1057 		[CLK_PLL_VE]		= &pll_ve_sun4i_clk.common.hw,
1058 		[CLK_PLL_DDR_BASE]	= &pll_ddr_base_clk.common.hw,
1059 		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
1060 		[CLK_PLL_DDR_OTHER]	= &pll_ddr_other_clk.common.hw,
1061 		[CLK_PLL_PERIPH_BASE]	= &pll_periph_base_clk.common.hw,
1062 		[CLK_PLL_PERIPH]	= &pll_periph_clk.hw,
1063 		[CLK_PLL_PERIPH_SATA]	= &pll_periph_sata_clk.common.hw,
1064 		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
1065 		[CLK_PLL_VIDEO1_2X]	= &pll_video1_2x_clk.hw,
1066 		[CLK_CPU]		= &cpu_clk.common.hw,
1067 		[CLK_AXI]		= &axi_clk.common.hw,
1068 		[CLK_AXI_DRAM]		= &axi_dram_clk.common.hw,
1069 		[CLK_AHB]		= &ahb_sun4i_clk.common.hw,
1070 		[CLK_APB0]		= &apb0_clk.common.hw,
1071 		[CLK_APB1]		= &apb1_clk.common.hw,
1072 		[CLK_AHB_OTG]		= &ahb_otg_clk.common.hw,
1073 		[CLK_AHB_EHCI0]		= &ahb_ehci0_clk.common.hw,
1074 		[CLK_AHB_OHCI0]		= &ahb_ohci0_clk.common.hw,
1075 		[CLK_AHB_EHCI1]		= &ahb_ehci1_clk.common.hw,
1076 		[CLK_AHB_OHCI1]		= &ahb_ohci1_clk.common.hw,
1077 		[CLK_AHB_SS]		= &ahb_ss_clk.common.hw,
1078 		[CLK_AHB_DMA]		= &ahb_dma_clk.common.hw,
1079 		[CLK_AHB_BIST]		= &ahb_bist_clk.common.hw,
1080 		[CLK_AHB_MMC0]		= &ahb_mmc0_clk.common.hw,
1081 		[CLK_AHB_MMC1]		= &ahb_mmc1_clk.common.hw,
1082 		[CLK_AHB_MMC2]		= &ahb_mmc2_clk.common.hw,
1083 		[CLK_AHB_MMC3]		= &ahb_mmc3_clk.common.hw,
1084 		[CLK_AHB_MS]		= &ahb_ms_clk.common.hw,
1085 		[CLK_AHB_NAND]		= &ahb_nand_clk.common.hw,
1086 		[CLK_AHB_SDRAM]		= &ahb_sdram_clk.common.hw,
1087 		[CLK_AHB_ACE]		= &ahb_ace_clk.common.hw,
1088 		[CLK_AHB_EMAC]		= &ahb_emac_clk.common.hw,
1089 		[CLK_AHB_TS]		= &ahb_ts_clk.common.hw,
1090 		[CLK_AHB_SPI0]		= &ahb_spi0_clk.common.hw,
1091 		[CLK_AHB_SPI1]		= &ahb_spi1_clk.common.hw,
1092 		[CLK_AHB_SPI2]		= &ahb_spi2_clk.common.hw,
1093 		[CLK_AHB_SPI3]		= &ahb_spi3_clk.common.hw,
1094 		[CLK_AHB_PATA]		= &ahb_pata_clk.common.hw,
1095 		[CLK_AHB_SATA]		= &ahb_sata_clk.common.hw,
1096 		[CLK_AHB_GPS]		= &ahb_gps_clk.common.hw,
1097 		[CLK_AHB_VE]		= &ahb_ve_clk.common.hw,
1098 		[CLK_AHB_TVD]		= &ahb_tvd_clk.common.hw,
1099 		[CLK_AHB_TVE0]		= &ahb_tve0_clk.common.hw,
1100 		[CLK_AHB_TVE1]		= &ahb_tve1_clk.common.hw,
1101 		[CLK_AHB_LCD0]		= &ahb_lcd0_clk.common.hw,
1102 		[CLK_AHB_LCD1]		= &ahb_lcd1_clk.common.hw,
1103 		[CLK_AHB_CSI0]		= &ahb_csi0_clk.common.hw,
1104 		[CLK_AHB_CSI1]		= &ahb_csi1_clk.common.hw,
1105 		[CLK_AHB_HDMI0]		= &ahb_hdmi0_clk.common.hw,
1106 		[CLK_AHB_DE_BE0]	= &ahb_de_be0_clk.common.hw,
1107 		[CLK_AHB_DE_BE1]	= &ahb_de_be1_clk.common.hw,
1108 		[CLK_AHB_DE_FE0]	= &ahb_de_fe0_clk.common.hw,
1109 		[CLK_AHB_DE_FE1]	= &ahb_de_fe1_clk.common.hw,
1110 		[CLK_AHB_MP]		= &ahb_mp_clk.common.hw,
1111 		[CLK_AHB_GPU]		= &ahb_gpu_clk.common.hw,
1112 		[CLK_APB0_CODEC]	= &apb0_codec_clk.common.hw,
1113 		[CLK_APB0_SPDIF]	= &apb0_spdif_clk.common.hw,
1114 		[CLK_APB0_AC97]		= &apb0_ac97_clk.common.hw,
1115 		[CLK_APB0_I2S0]		= &apb0_i2s0_clk.common.hw,
1116 		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,
1117 		[CLK_APB0_IR0]		= &apb0_ir0_clk.common.hw,
1118 		[CLK_APB0_IR1]		= &apb0_ir1_clk.common.hw,
1119 		[CLK_APB0_KEYPAD]	= &apb0_keypad_clk.common.hw,
1120 		[CLK_APB1_I2C0]		= &apb1_i2c0_clk.common.hw,
1121 		[CLK_APB1_I2C1]		= &apb1_i2c1_clk.common.hw,
1122 		[CLK_APB1_I2C2]		= &apb1_i2c2_clk.common.hw,
1123 		[CLK_APB1_CAN]		= &apb1_can_clk.common.hw,
1124 		[CLK_APB1_SCR]		= &apb1_scr_clk.common.hw,
1125 		[CLK_APB1_PS20]		= &apb1_ps20_clk.common.hw,
1126 		[CLK_APB1_PS21]		= &apb1_ps21_clk.common.hw,
1127 		[CLK_APB1_UART0]	= &apb1_uart0_clk.common.hw,
1128 		[CLK_APB1_UART1]	= &apb1_uart1_clk.common.hw,
1129 		[CLK_APB1_UART2]	= &apb1_uart2_clk.common.hw,
1130 		[CLK_APB1_UART3]	= &apb1_uart3_clk.common.hw,
1131 		[CLK_APB1_UART4]	= &apb1_uart4_clk.common.hw,
1132 		[CLK_APB1_UART5]	= &apb1_uart5_clk.common.hw,
1133 		[CLK_APB1_UART6]	= &apb1_uart6_clk.common.hw,
1134 		[CLK_APB1_UART7]	= &apb1_uart7_clk.common.hw,
1135 		[CLK_NAND]		= &nand_clk.common.hw,
1136 		[CLK_MS]		= &ms_clk.common.hw,
1137 		[CLK_MMC0]		= &mmc0_clk.common.hw,
1138 		[CLK_MMC1]		= &mmc1_clk.common.hw,
1139 		[CLK_MMC2]		= &mmc2_clk.common.hw,
1140 		[CLK_MMC3]		= &mmc3_clk.common.hw,
1141 		[CLK_TS]		= &ts_clk.common.hw,
1142 		[CLK_SS]		= &ss_clk.common.hw,
1143 		[CLK_SPI0]		= &spi0_clk.common.hw,
1144 		[CLK_SPI1]		= &spi1_clk.common.hw,
1145 		[CLK_SPI2]		= &spi2_clk.common.hw,
1146 		[CLK_PATA]		= &pata_clk.common.hw,
1147 		[CLK_IR0]		= &ir0_sun4i_clk.common.hw,
1148 		[CLK_IR1]		= &ir1_sun4i_clk.common.hw,
1149 		[CLK_I2S0]		= &i2s0_clk.common.hw,
1150 		[CLK_AC97]		= &ac97_clk.common.hw,
1151 		[CLK_SPDIF]		= &spdif_clk.common.hw,
1152 		[CLK_KEYPAD]		= &keypad_clk.common.hw,
1153 		[CLK_SATA]		= &sata_clk.common.hw,
1154 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
1155 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
1156 		[CLK_USB_PHY]		= &usb_phy_clk.common.hw,
1157 		/* CLK_GPS is unimplemented */
1158 		[CLK_SPI3]		= &spi3_clk.common.hw,
1159 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
1160 		[CLK_DRAM_CSI0]		= &dram_csi0_clk.common.hw,
1161 		[CLK_DRAM_CSI1]		= &dram_csi1_clk.common.hw,
1162 		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
1163 		[CLK_DRAM_TVD]		= &dram_tvd_clk.common.hw,
1164 		[CLK_DRAM_TVE0]		= &dram_tve0_clk.common.hw,
1165 		[CLK_DRAM_TVE1]		= &dram_tve1_clk.common.hw,
1166 		[CLK_DRAM_OUT]		= &dram_out_clk.common.hw,
1167 		[CLK_DRAM_DE_FE1]	= &dram_de_fe1_clk.common.hw,
1168 		[CLK_DRAM_DE_FE0]	= &dram_de_fe0_clk.common.hw,
1169 		[CLK_DRAM_DE_BE0]	= &dram_de_be0_clk.common.hw,
1170 		[CLK_DRAM_DE_BE1]	= &dram_de_be1_clk.common.hw,
1171 		[CLK_DRAM_MP]		= &dram_mp_clk.common.hw,
1172 		[CLK_DRAM_ACE]		= &dram_ace_clk.common.hw,
1173 		[CLK_DE_BE0]		= &de_be0_clk.common.hw,
1174 		[CLK_DE_BE1]		= &de_be1_clk.common.hw,
1175 		[CLK_DE_FE0]		= &de_fe0_clk.common.hw,
1176 		[CLK_DE_FE1]		= &de_fe1_clk.common.hw,
1177 		[CLK_DE_MP]		= &de_mp_clk.common.hw,
1178 		[CLK_TCON0_CH0]		= &tcon0_ch0_clk.common.hw,
1179 		[CLK_TCON1_CH0]		= &tcon1_ch0_clk.common.hw,
1180 		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
1181 		[CLK_TVD]		= &tvd_sun4i_clk.common.hw,
1182 		[CLK_TCON0_CH1_SCLK2]	= &tcon0_ch1_sclk2_clk.common.hw,
1183 		[CLK_TCON0_CH1]		= &tcon0_ch1_clk.common.hw,
1184 		[CLK_TCON1_CH1_SCLK2]	= &tcon1_ch1_sclk2_clk.common.hw,
1185 		[CLK_TCON1_CH1]		= &tcon1_ch1_clk.common.hw,
1186 		[CLK_CSI0]		= &csi0_clk.common.hw,
1187 		[CLK_CSI1]		= &csi1_clk.common.hw,
1188 		[CLK_VE]		= &ve_clk.common.hw,
1189 		[CLK_CODEC]		= &codec_clk.common.hw,
1190 		[CLK_AVS]		= &avs_clk.common.hw,
1191 		[CLK_ACE]		= &ace_clk.common.hw,
1192 		[CLK_HDMI]		= &hdmi_clk.common.hw,
1193 		[CLK_GPU]		= &gpu_sun7i_clk.common.hw,
1194 		[CLK_MBUS]		= &mbus_sun4i_clk.common.hw,
1195 	},
1196 	.num	= CLK_NUMBER_SUN4I,
1197 };
1198 static struct clk_hw_onecell_data sun7i_a20_hw_clks = {
1199 	.hws	= {
1200 		[CLK_HOSC]		= &hosc_clk.common.hw,
1201 		[CLK_PLL_CORE]		= &pll_core_clk.common.hw,
1202 		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
1203 		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
1204 		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
1205 		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
1206 		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
1207 		[CLK_PLL_VIDEO0]	= &pll_video0_clk.common.hw,
1208 		[CLK_PLL_VIDEO0_2X]	= &pll_video0_2x_clk.hw,
1209 		[CLK_PLL_VE]		= &pll_ve_sun7i_clk.common.hw,
1210 		[CLK_PLL_DDR_BASE]	= &pll_ddr_base_clk.common.hw,
1211 		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
1212 		[CLK_PLL_DDR_OTHER]	= &pll_ddr_other_clk.common.hw,
1213 		[CLK_PLL_PERIPH_BASE]	= &pll_periph_base_clk.common.hw,
1214 		[CLK_PLL_PERIPH]	= &pll_periph_clk.hw,
1215 		[CLK_PLL_PERIPH_SATA]	= &pll_periph_sata_clk.common.hw,
1216 		[CLK_PLL_VIDEO1]	= &pll_video1_clk.common.hw,
1217 		[CLK_PLL_VIDEO1_2X]	= &pll_video1_2x_clk.hw,
1218 		[CLK_PLL_GPU]		= &pll_gpu_clk.common.hw,
1219 		[CLK_CPU]		= &cpu_clk.common.hw,
1220 		[CLK_AXI]		= &axi_clk.common.hw,
1221 		[CLK_AHB]		= &ahb_sun7i_clk.common.hw,
1222 		[CLK_APB0]		= &apb0_clk.common.hw,
1223 		[CLK_APB1]		= &apb1_clk.common.hw,
1224 		[CLK_AHB_OTG]		= &ahb_otg_clk.common.hw,
1225 		[CLK_AHB_EHCI0]		= &ahb_ehci0_clk.common.hw,
1226 		[CLK_AHB_OHCI0]		= &ahb_ohci0_clk.common.hw,
1227 		[CLK_AHB_EHCI1]		= &ahb_ehci1_clk.common.hw,
1228 		[CLK_AHB_OHCI1]		= &ahb_ohci1_clk.common.hw,
1229 		[CLK_AHB_SS]		= &ahb_ss_clk.common.hw,
1230 		[CLK_AHB_DMA]		= &ahb_dma_clk.common.hw,
1231 		[CLK_AHB_BIST]		= &ahb_bist_clk.common.hw,
1232 		[CLK_AHB_MMC0]		= &ahb_mmc0_clk.common.hw,
1233 		[CLK_AHB_MMC1]		= &ahb_mmc1_clk.common.hw,
1234 		[CLK_AHB_MMC2]		= &ahb_mmc2_clk.common.hw,
1235 		[CLK_AHB_MMC3]		= &ahb_mmc3_clk.common.hw,
1236 		[CLK_AHB_MS]		= &ahb_ms_clk.common.hw,
1237 		[CLK_AHB_NAND]		= &ahb_nand_clk.common.hw,
1238 		[CLK_AHB_SDRAM]		= &ahb_sdram_clk.common.hw,
1239 		[CLK_AHB_ACE]		= &ahb_ace_clk.common.hw,
1240 		[CLK_AHB_EMAC]		= &ahb_emac_clk.common.hw,
1241 		[CLK_AHB_TS]		= &ahb_ts_clk.common.hw,
1242 		[CLK_AHB_SPI0]		= &ahb_spi0_clk.common.hw,
1243 		[CLK_AHB_SPI1]		= &ahb_spi1_clk.common.hw,
1244 		[CLK_AHB_SPI2]		= &ahb_spi2_clk.common.hw,
1245 		[CLK_AHB_SPI3]		= &ahb_spi3_clk.common.hw,
1246 		[CLK_AHB_PATA]		= &ahb_pata_clk.common.hw,
1247 		[CLK_AHB_SATA]		= &ahb_sata_clk.common.hw,
1248 		[CLK_AHB_HSTIMER]	= &ahb_hstimer_clk.common.hw,
1249 		[CLK_AHB_VE]		= &ahb_ve_clk.common.hw,
1250 		[CLK_AHB_TVD]		= &ahb_tvd_clk.common.hw,
1251 		[CLK_AHB_TVE0]		= &ahb_tve0_clk.common.hw,
1252 		[CLK_AHB_TVE1]		= &ahb_tve1_clk.common.hw,
1253 		[CLK_AHB_LCD0]		= &ahb_lcd0_clk.common.hw,
1254 		[CLK_AHB_LCD1]		= &ahb_lcd1_clk.common.hw,
1255 		[CLK_AHB_CSI0]		= &ahb_csi0_clk.common.hw,
1256 		[CLK_AHB_CSI1]		= &ahb_csi1_clk.common.hw,
1257 		[CLK_AHB_HDMI1]		= &ahb_hdmi1_clk.common.hw,
1258 		[CLK_AHB_HDMI0]		= &ahb_hdmi0_clk.common.hw,
1259 		[CLK_AHB_DE_BE0]	= &ahb_de_be0_clk.common.hw,
1260 		[CLK_AHB_DE_BE1]	= &ahb_de_be1_clk.common.hw,
1261 		[CLK_AHB_DE_FE0]	= &ahb_de_fe0_clk.common.hw,
1262 		[CLK_AHB_DE_FE1]	= &ahb_de_fe1_clk.common.hw,
1263 		[CLK_AHB_GMAC]		= &ahb_gmac_clk.common.hw,
1264 		[CLK_AHB_MP]		= &ahb_mp_clk.common.hw,
1265 		[CLK_AHB_GPU]		= &ahb_gpu_clk.common.hw,
1266 		[CLK_APB0_CODEC]	= &apb0_codec_clk.common.hw,
1267 		[CLK_APB0_SPDIF]	= &apb0_spdif_clk.common.hw,
1268 		[CLK_APB0_AC97]		= &apb0_ac97_clk.common.hw,
1269 		[CLK_APB0_I2S0]		= &apb0_i2s0_clk.common.hw,
1270 		[CLK_APB0_I2S1]		= &apb0_i2s1_clk.common.hw,
1271 		[CLK_APB0_PIO]		= &apb0_pio_clk.common.hw,
1272 		[CLK_APB0_IR0]		= &apb0_ir0_clk.common.hw,
1273 		[CLK_APB0_IR1]		= &apb0_ir1_clk.common.hw,
1274 		[CLK_APB0_I2S2]		= &apb0_i2s2_clk.common.hw,
1275 		[CLK_APB0_KEYPAD]	= &apb0_keypad_clk.common.hw,
1276 		[CLK_APB1_I2C0]		= &apb1_i2c0_clk.common.hw,
1277 		[CLK_APB1_I2C1]		= &apb1_i2c1_clk.common.hw,
1278 		[CLK_APB1_I2C2]		= &apb1_i2c2_clk.common.hw,
1279 		[CLK_APB1_I2C3]		= &apb1_i2c3_clk.common.hw,
1280 		[CLK_APB1_CAN]		= &apb1_can_clk.common.hw,
1281 		[CLK_APB1_SCR]		= &apb1_scr_clk.common.hw,
1282 		[CLK_APB1_PS20]		= &apb1_ps20_clk.common.hw,
1283 		[CLK_APB1_PS21]		= &apb1_ps21_clk.common.hw,
1284 		[CLK_APB1_I2C4]		= &apb1_i2c4_clk.common.hw,
1285 		[CLK_APB1_UART0]	= &apb1_uart0_clk.common.hw,
1286 		[CLK_APB1_UART1]	= &apb1_uart1_clk.common.hw,
1287 		[CLK_APB1_UART2]	= &apb1_uart2_clk.common.hw,
1288 		[CLK_APB1_UART3]	= &apb1_uart3_clk.common.hw,
1289 		[CLK_APB1_UART4]	= &apb1_uart4_clk.common.hw,
1290 		[CLK_APB1_UART5]	= &apb1_uart5_clk.common.hw,
1291 		[CLK_APB1_UART6]	= &apb1_uart6_clk.common.hw,
1292 		[CLK_APB1_UART7]	= &apb1_uart7_clk.common.hw,
1293 		[CLK_NAND]		= &nand_clk.common.hw,
1294 		[CLK_MS]		= &ms_clk.common.hw,
1295 		[CLK_MMC0]		= &mmc0_clk.common.hw,
1296 		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
1297 		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
1298 		[CLK_MMC1]		= &mmc1_clk.common.hw,
1299 		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
1300 		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
1301 		[CLK_MMC2]		= &mmc2_clk.common.hw,
1302 		[CLK_MMC2_OUTPUT]	= &mmc2_output_clk.common.hw,
1303 		[CLK_MMC2_SAMPLE]	= &mmc2_sample_clk.common.hw,
1304 		[CLK_MMC3]		= &mmc3_clk.common.hw,
1305 		[CLK_MMC3_OUTPUT]	= &mmc3_output_clk.common.hw,
1306 		[CLK_MMC3_SAMPLE]	= &mmc3_sample_clk.common.hw,
1307 		[CLK_TS]		= &ts_clk.common.hw,
1308 		[CLK_SS]		= &ss_clk.common.hw,
1309 		[CLK_SPI0]		= &spi0_clk.common.hw,
1310 		[CLK_SPI1]		= &spi1_clk.common.hw,
1311 		[CLK_SPI2]		= &spi2_clk.common.hw,
1312 		[CLK_PATA]		= &pata_clk.common.hw,
1313 		[CLK_IR0]		= &ir0_sun7i_clk.common.hw,
1314 		[CLK_IR1]		= &ir1_sun7i_clk.common.hw,
1315 		[CLK_I2S0]		= &i2s0_clk.common.hw,
1316 		[CLK_AC97]		= &ac97_clk.common.hw,
1317 		[CLK_SPDIF]		= &spdif_clk.common.hw,
1318 		[CLK_KEYPAD]		= &keypad_clk.common.hw,
1319 		[CLK_SATA]		= &sata_clk.common.hw,
1320 		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
1321 		[CLK_USB_OHCI1]		= &usb_ohci1_clk.common.hw,
1322 		[CLK_USB_PHY]		= &usb_phy_clk.common.hw,
1323 		/* CLK_GPS is unimplemented */
1324 		[CLK_SPI3]		= &spi3_clk.common.hw,
1325 		[CLK_I2S1]		= &i2s1_clk.common.hw,
1326 		[CLK_I2S2]		= &i2s2_clk.common.hw,
1327 		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
1328 		[CLK_DRAM_CSI0]		= &dram_csi0_clk.common.hw,
1329 		[CLK_DRAM_CSI1]		= &dram_csi1_clk.common.hw,
1330 		[CLK_DRAM_TS]		= &dram_ts_clk.common.hw,
1331 		[CLK_DRAM_TVD]		= &dram_tvd_clk.common.hw,
1332 		[CLK_DRAM_TVE0]		= &dram_tve0_clk.common.hw,
1333 		[CLK_DRAM_TVE1]		= &dram_tve1_clk.common.hw,
1334 		[CLK_DRAM_OUT]		= &dram_out_clk.common.hw,
1335 		[CLK_DRAM_DE_FE1]	= &dram_de_fe1_clk.common.hw,
1336 		[CLK_DRAM_DE_FE0]	= &dram_de_fe0_clk.common.hw,
1337 		[CLK_DRAM_DE_BE0]	= &dram_de_be0_clk.common.hw,
1338 		[CLK_DRAM_DE_BE1]	= &dram_de_be1_clk.common.hw,
1339 		[CLK_DRAM_MP]		= &dram_mp_clk.common.hw,
1340 		[CLK_DRAM_ACE]		= &dram_ace_clk.common.hw,
1341 		[CLK_DE_BE0]		= &de_be0_clk.common.hw,
1342 		[CLK_DE_BE1]		= &de_be1_clk.common.hw,
1343 		[CLK_DE_FE0]		= &de_fe0_clk.common.hw,
1344 		[CLK_DE_FE1]		= &de_fe1_clk.common.hw,
1345 		[CLK_DE_MP]		= &de_mp_clk.common.hw,
1346 		[CLK_TCON0_CH0]		= &tcon0_ch0_clk.common.hw,
1347 		[CLK_TCON1_CH0]		= &tcon1_ch0_clk.common.hw,
1348 		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,
1349 		[CLK_TVD_SCLK2]		= &tvd_sclk2_sun7i_clk.common.hw,
1350 		[CLK_TVD]		= &tvd_sclk1_sun7i_clk.common.hw,
1351 		[CLK_TCON0_CH1_SCLK2]	= &tcon0_ch1_sclk2_clk.common.hw,
1352 		[CLK_TCON0_CH1]		= &tcon0_ch1_clk.common.hw,
1353 		[CLK_TCON1_CH1_SCLK2]	= &tcon1_ch1_sclk2_clk.common.hw,
1354 		[CLK_TCON1_CH1]		= &tcon1_ch1_clk.common.hw,
1355 		[CLK_CSI0]		= &csi0_clk.common.hw,
1356 		[CLK_CSI1]		= &csi1_clk.common.hw,
1357 		[CLK_VE]		= &ve_clk.common.hw,
1358 		[CLK_CODEC]		= &codec_clk.common.hw,
1359 		[CLK_AVS]		= &avs_clk.common.hw,
1360 		[CLK_ACE]		= &ace_clk.common.hw,
1361 		[CLK_HDMI]		= &hdmi_clk.common.hw,
1362 		[CLK_GPU]		= &gpu_sun7i_clk.common.hw,
1363 		[CLK_MBUS]		= &mbus_sun7i_clk.common.hw,
1364 		[CLK_HDMI1_SLOW]	= &hdmi1_slow_clk.common.hw,
1365 		[CLK_HDMI1]		= &hdmi1_clk.common.hw,
1366 		[CLK_OUT_A]		= &out_a_clk.common.hw,
1367 		[CLK_OUT_B]		= &out_b_clk.common.hw,
1368 	},
1369 	.num	= CLK_NUMBER_SUN7I,
1370 };
1371 
1372 static struct ccu_reset_map sunxi_a10_a20_ccu_resets[] = {
1373 	[RST_USB_PHY0]		= { 0x0cc, BIT(0) },
1374 	[RST_USB_PHY1]		= { 0x0cc, BIT(1) },
1375 	[RST_USB_PHY2]		= { 0x0cc, BIT(2) },
1376 	[RST_GPS]		= { 0x0d0, BIT(0) },
1377 	[RST_DE_BE0]		= { 0x104, BIT(30) },
1378 	[RST_DE_BE1]		= { 0x108, BIT(30) },
1379 	[RST_DE_FE0]		= { 0x10c, BIT(30) },
1380 	[RST_DE_FE1]		= { 0x110, BIT(30) },
1381 	[RST_DE_MP]		= { 0x114, BIT(30) },
1382 	[RST_TVE0]		= { 0x118, BIT(29) },
1383 	[RST_TCON0]		= { 0x118, BIT(30) },
1384 	[RST_TVE1]		= { 0x11c, BIT(29) },
1385 	[RST_TCON1]		= { 0x11c, BIT(30) },
1386 	[RST_CSI0]		= { 0x134, BIT(30) },
1387 	[RST_CSI1]		= { 0x138, BIT(30) },
1388 	[RST_VE]		= { 0x13c, BIT(0) },
1389 	[RST_ACE]		= { 0x148, BIT(16) },
1390 	[RST_LVDS]		= { 0x14c, BIT(0) },
1391 	[RST_GPU]		= { 0x154, BIT(30) },
1392 	[RST_HDMI_H]		= { 0x170, BIT(0) },
1393 	[RST_HDMI_SYS]		= { 0x170, BIT(1) },
1394 	[RST_HDMI_AUDIO_DMA]	= { 0x170, BIT(2) },
1395 };
1396 
1397 static const struct sunxi_ccu_desc sun4i_a10_ccu_desc = {
1398 	.ccu_clks	= sun4i_sun7i_ccu_clks,
1399 	.num_ccu_clks	= ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1400 
1401 	.hw_clks	= &sun4i_a10_hw_clks,
1402 
1403 	.resets		= sunxi_a10_a20_ccu_resets,
1404 	.num_resets	= ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1405 };
1406 
1407 static const struct sunxi_ccu_desc sun7i_a20_ccu_desc = {
1408 	.ccu_clks	= sun4i_sun7i_ccu_clks,
1409 	.num_ccu_clks	= ARRAY_SIZE(sun4i_sun7i_ccu_clks),
1410 
1411 	.hw_clks	= &sun7i_a20_hw_clks,
1412 
1413 	.resets		= sunxi_a10_a20_ccu_resets,
1414 	.num_resets	= ARRAY_SIZE(sunxi_a10_a20_ccu_resets),
1415 };
1416 
1417 static void __init sun4i_ccu_init(struct device_node *node,
1418 				  const struct sunxi_ccu_desc *desc)
1419 {
1420 	void __iomem *reg;
1421 	u32 val;
1422 
1423 	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
1424 	if (IS_ERR(reg)) {
1425 		pr_err("%s: Could not map the clock registers\n",
1426 		       of_node_full_name(node));
1427 		return;
1428 	}
1429 
1430 	val = readl(reg + SUN4I_PLL_AUDIO_REG);
1431 
1432 	/*
1433 	 * Force VCO and PLL bias current to lowest setting. Higher
1434 	 * settings interfere with sigma-delta modulation and result
1435 	 * in audible noise and distortions when using SPDIF or I2S.
1436 	 */
1437 	val &= ~GENMASK(25, 16);
1438 
1439 	/* Force the PLL-Audio-1x divider to 1 */
1440 	val &= ~GENMASK(29, 26);
1441 	writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
1442 
1443 	/*
1444 	 * Use the peripheral PLL6 as the AHB parent, instead of CPU /
1445 	 * AXI which have rate changes due to cpufreq.
1446 	 *
1447 	 * This is especially a big deal for the HS timer whose parent
1448 	 * clock is AHB.
1449 	 *
1450 	 * NB! These bits are undocumented in A10 manual.
1451 	 */
1452 	val = readl(reg + SUN4I_AHB_REG);
1453 	val &= ~GENMASK(7, 6);
1454 	writel(val | (2 << 6), reg + SUN4I_AHB_REG);
1455 
1456 	sunxi_ccu_probe(node, reg, desc);
1457 }
1458 
1459 static void __init sun4i_a10_ccu_setup(struct device_node *node)
1460 {
1461 	sun4i_ccu_init(node, &sun4i_a10_ccu_desc);
1462 }
1463 CLK_OF_DECLARE(sun4i_a10_ccu, "allwinner,sun4i-a10-ccu",
1464 	       sun4i_a10_ccu_setup);
1465 
1466 static void __init sun7i_a20_ccu_setup(struct device_node *node)
1467 {
1468 	sun4i_ccu_init(node, &sun7i_a20_ccu_desc);
1469 }
1470 CLK_OF_DECLARE(sun7i_a20_ccu, "allwinner,sun7i-a20-ccu",
1471 	       sun7i_a20_ccu_setup);
1472