1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 4 * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/module.h> 9 #include <linux/of_address.h> 10 #include <linux/platform_device.h> 11 #include <dt-bindings/clock/stm32mp13-clks.h> 12 #include "clk-stm32-core.h" 13 #include "stm32mp13_rcc.h" 14 15 #define RCC_CLR_OFFSET 0x4 16 17 /* STM32 Gates definition */ 18 enum enum_gate_cfg { 19 GATE_MCO1, 20 GATE_MCO2, 21 GATE_DBGCK, 22 GATE_TRACECK, 23 GATE_DDRC1, 24 GATE_DDRC1LP, 25 GATE_DDRPHYC, 26 GATE_DDRPHYCLP, 27 GATE_DDRCAPB, 28 GATE_DDRCAPBLP, 29 GATE_AXIDCG, 30 GATE_DDRPHYCAPB, 31 GATE_DDRPHYCAPBLP, 32 GATE_TIM2, 33 GATE_TIM3, 34 GATE_TIM4, 35 GATE_TIM5, 36 GATE_TIM6, 37 GATE_TIM7, 38 GATE_LPTIM1, 39 GATE_SPI2, 40 GATE_SPI3, 41 GATE_USART3, 42 GATE_UART4, 43 GATE_UART5, 44 GATE_UART7, 45 GATE_UART8, 46 GATE_I2C1, 47 GATE_I2C2, 48 GATE_SPDIF, 49 GATE_TIM1, 50 GATE_TIM8, 51 GATE_SPI1, 52 GATE_USART6, 53 GATE_SAI1, 54 GATE_SAI2, 55 GATE_DFSDM, 56 GATE_ADFSDM, 57 GATE_FDCAN, 58 GATE_LPTIM2, 59 GATE_LPTIM3, 60 GATE_LPTIM4, 61 GATE_LPTIM5, 62 GATE_VREF, 63 GATE_DTS, 64 GATE_PMBCTRL, 65 GATE_HDP, 66 GATE_SYSCFG, 67 GATE_DCMIPP, 68 GATE_DDRPERFM, 69 GATE_IWDG2APB, 70 GATE_USBPHY, 71 GATE_STGENRO, 72 GATE_LTDC, 73 GATE_RTCAPB, 74 GATE_TZC, 75 GATE_ETZPC, 76 GATE_IWDG1APB, 77 GATE_BSEC, 78 GATE_STGENC, 79 GATE_USART1, 80 GATE_USART2, 81 GATE_SPI4, 82 GATE_SPI5, 83 GATE_I2C3, 84 GATE_I2C4, 85 GATE_I2C5, 86 GATE_TIM12, 87 GATE_TIM13, 88 GATE_TIM14, 89 GATE_TIM15, 90 GATE_TIM16, 91 GATE_TIM17, 92 GATE_DMA1, 93 GATE_DMA2, 94 GATE_DMAMUX1, 95 GATE_DMA3, 96 GATE_DMAMUX2, 97 GATE_ADC1, 98 GATE_ADC2, 99 GATE_USBO, 100 GATE_TSC, 101 GATE_GPIOA, 102 GATE_GPIOB, 103 GATE_GPIOC, 104 GATE_GPIOD, 105 GATE_GPIOE, 106 GATE_GPIOF, 107 GATE_GPIOG, 108 GATE_GPIOH, 109 GATE_GPIOI, 110 GATE_PKA, 111 GATE_SAES, 112 GATE_CRYP1, 113 GATE_HASH1, 114 GATE_RNG1, 115 GATE_BKPSRAM, 116 GATE_AXIMC, 117 GATE_MCE, 118 GATE_ETH1CK, 119 GATE_ETH1TX, 120 GATE_ETH1RX, 121 GATE_ETH1MAC, 122 GATE_FMC, 123 GATE_QSPI, 124 GATE_SDMMC1, 125 GATE_SDMMC2, 126 GATE_CRC1, 127 GATE_USBH, 128 GATE_ETH2CK, 129 GATE_ETH2TX, 130 GATE_ETH2RX, 131 GATE_ETH2MAC, 132 GATE_ETH1STP, 133 GATE_ETH2STP, 134 GATE_MDMA, 135 GATE_NB 136 }; 137 138 #define _CFG_GATE(_id, _offset, _bit_idx, _offset_clr)\ 139 [(_id)] = {\ 140 .offset = (_offset),\ 141 .bit_idx = (_bit_idx),\ 142 .set_clr = (_offset_clr),\ 143 } 144 145 #define CFG_GATE(_id, _offset, _bit_idx)\ 146 _CFG_GATE(_id, _offset, _bit_idx, 0) 147 148 #define CFG_GATE_SETCLR(_id, _offset, _bit_idx)\ 149 _CFG_GATE(_id, _offset, _bit_idx, RCC_CLR_OFFSET) 150 151 static struct stm32_gate_cfg stm32mp13_gates[] = { 152 CFG_GATE(GATE_MCO1, RCC_MCO1CFGR, 12), 153 CFG_GATE(GATE_MCO2, RCC_MCO2CFGR, 12), 154 CFG_GATE(GATE_DBGCK, RCC_DBGCFGR, 8), 155 CFG_GATE(GATE_TRACECK, RCC_DBGCFGR, 9), 156 CFG_GATE(GATE_DDRC1, RCC_DDRITFCR, 0), 157 CFG_GATE(GATE_DDRC1LP, RCC_DDRITFCR, 1), 158 CFG_GATE(GATE_DDRPHYC, RCC_DDRITFCR, 4), 159 CFG_GATE(GATE_DDRPHYCLP, RCC_DDRITFCR, 5), 160 CFG_GATE(GATE_DDRCAPB, RCC_DDRITFCR, 6), 161 CFG_GATE(GATE_DDRCAPBLP, RCC_DDRITFCR, 7), 162 CFG_GATE(GATE_AXIDCG, RCC_DDRITFCR, 8), 163 CFG_GATE(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9), 164 CFG_GATE(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10), 165 CFG_GATE_SETCLR(GATE_TIM2, RCC_MP_APB1ENSETR, 0), 166 CFG_GATE_SETCLR(GATE_TIM3, RCC_MP_APB1ENSETR, 1), 167 CFG_GATE_SETCLR(GATE_TIM4, RCC_MP_APB1ENSETR, 2), 168 CFG_GATE_SETCLR(GATE_TIM5, RCC_MP_APB1ENSETR, 3), 169 CFG_GATE_SETCLR(GATE_TIM6, RCC_MP_APB1ENSETR, 4), 170 CFG_GATE_SETCLR(GATE_TIM7, RCC_MP_APB1ENSETR, 5), 171 CFG_GATE_SETCLR(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9), 172 CFG_GATE_SETCLR(GATE_SPI2, RCC_MP_APB1ENSETR, 11), 173 CFG_GATE_SETCLR(GATE_SPI3, RCC_MP_APB1ENSETR, 12), 174 CFG_GATE_SETCLR(GATE_USART3, RCC_MP_APB1ENSETR, 15), 175 CFG_GATE_SETCLR(GATE_UART4, RCC_MP_APB1ENSETR, 16), 176 CFG_GATE_SETCLR(GATE_UART5, RCC_MP_APB1ENSETR, 17), 177 CFG_GATE_SETCLR(GATE_UART7, RCC_MP_APB1ENSETR, 18), 178 CFG_GATE_SETCLR(GATE_UART8, RCC_MP_APB1ENSETR, 19), 179 CFG_GATE_SETCLR(GATE_I2C1, RCC_MP_APB1ENSETR, 21), 180 CFG_GATE_SETCLR(GATE_I2C2, RCC_MP_APB1ENSETR, 22), 181 CFG_GATE_SETCLR(GATE_SPDIF, RCC_MP_APB1ENSETR, 26), 182 CFG_GATE_SETCLR(GATE_TIM1, RCC_MP_APB2ENSETR, 0), 183 CFG_GATE_SETCLR(GATE_TIM8, RCC_MP_APB2ENSETR, 1), 184 CFG_GATE_SETCLR(GATE_SPI1, RCC_MP_APB2ENSETR, 8), 185 CFG_GATE_SETCLR(GATE_USART6, RCC_MP_APB2ENSETR, 13), 186 CFG_GATE_SETCLR(GATE_SAI1, RCC_MP_APB2ENSETR, 16), 187 CFG_GATE_SETCLR(GATE_SAI2, RCC_MP_APB2ENSETR, 17), 188 CFG_GATE_SETCLR(GATE_DFSDM, RCC_MP_APB2ENSETR, 20), 189 CFG_GATE_SETCLR(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21), 190 CFG_GATE_SETCLR(GATE_FDCAN, RCC_MP_APB2ENSETR, 24), 191 CFG_GATE_SETCLR(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0), 192 CFG_GATE_SETCLR(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1), 193 CFG_GATE_SETCLR(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2), 194 CFG_GATE_SETCLR(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3), 195 CFG_GATE_SETCLR(GATE_VREF, RCC_MP_APB3ENSETR, 13), 196 CFG_GATE_SETCLR(GATE_DTS, RCC_MP_APB3ENSETR, 16), 197 CFG_GATE_SETCLR(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17), 198 CFG_GATE_SETCLR(GATE_HDP, RCC_MP_APB3ENSETR, 20), 199 CFG_GATE_SETCLR(GATE_SYSCFG, RCC_MP_NS_APB3ENSETR, 0), 200 CFG_GATE_SETCLR(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1), 201 CFG_GATE_SETCLR(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8), 202 CFG_GATE_SETCLR(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15), 203 CFG_GATE_SETCLR(GATE_USBPHY, RCC_MP_APB4ENSETR, 16), 204 CFG_GATE_SETCLR(GATE_STGENRO, RCC_MP_APB4ENSETR, 20), 205 CFG_GATE_SETCLR(GATE_LTDC, RCC_MP_NS_APB4ENSETR, 0), 206 CFG_GATE_SETCLR(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8), 207 CFG_GATE_SETCLR(GATE_TZC, RCC_MP_APB5ENSETR, 11), 208 CFG_GATE_SETCLR(GATE_ETZPC, RCC_MP_APB5ENSETR, 13), 209 CFG_GATE_SETCLR(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15), 210 CFG_GATE_SETCLR(GATE_BSEC, RCC_MP_APB5ENSETR, 16), 211 CFG_GATE_SETCLR(GATE_STGENC, RCC_MP_APB5ENSETR, 20), 212 CFG_GATE_SETCLR(GATE_USART1, RCC_MP_APB6ENSETR, 0), 213 CFG_GATE_SETCLR(GATE_USART2, RCC_MP_APB6ENSETR, 1), 214 CFG_GATE_SETCLR(GATE_SPI4, RCC_MP_APB6ENSETR, 2), 215 CFG_GATE_SETCLR(GATE_SPI5, RCC_MP_APB6ENSETR, 3), 216 CFG_GATE_SETCLR(GATE_I2C3, RCC_MP_APB6ENSETR, 4), 217 CFG_GATE_SETCLR(GATE_I2C4, RCC_MP_APB6ENSETR, 5), 218 CFG_GATE_SETCLR(GATE_I2C5, RCC_MP_APB6ENSETR, 6), 219 CFG_GATE_SETCLR(GATE_TIM12, RCC_MP_APB6ENSETR, 7), 220 CFG_GATE_SETCLR(GATE_TIM13, RCC_MP_APB6ENSETR, 8), 221 CFG_GATE_SETCLR(GATE_TIM14, RCC_MP_APB6ENSETR, 9), 222 CFG_GATE_SETCLR(GATE_TIM15, RCC_MP_APB6ENSETR, 10), 223 CFG_GATE_SETCLR(GATE_TIM16, RCC_MP_APB6ENSETR, 11), 224 CFG_GATE_SETCLR(GATE_TIM17, RCC_MP_APB6ENSETR, 12), 225 CFG_GATE_SETCLR(GATE_DMA1, RCC_MP_AHB2ENSETR, 0), 226 CFG_GATE_SETCLR(GATE_DMA2, RCC_MP_AHB2ENSETR, 1), 227 CFG_GATE_SETCLR(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2), 228 CFG_GATE_SETCLR(GATE_DMA3, RCC_MP_AHB2ENSETR, 3), 229 CFG_GATE_SETCLR(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4), 230 CFG_GATE_SETCLR(GATE_ADC1, RCC_MP_AHB2ENSETR, 5), 231 CFG_GATE_SETCLR(GATE_ADC2, RCC_MP_AHB2ENSETR, 6), 232 CFG_GATE_SETCLR(GATE_USBO, RCC_MP_AHB2ENSETR, 8), 233 CFG_GATE_SETCLR(GATE_TSC, RCC_MP_AHB4ENSETR, 15), 234 CFG_GATE_SETCLR(GATE_GPIOA, RCC_MP_NS_AHB4ENSETR, 0), 235 CFG_GATE_SETCLR(GATE_GPIOB, RCC_MP_NS_AHB4ENSETR, 1), 236 CFG_GATE_SETCLR(GATE_GPIOC, RCC_MP_NS_AHB4ENSETR, 2), 237 CFG_GATE_SETCLR(GATE_GPIOD, RCC_MP_NS_AHB4ENSETR, 3), 238 CFG_GATE_SETCLR(GATE_GPIOE, RCC_MP_NS_AHB4ENSETR, 4), 239 CFG_GATE_SETCLR(GATE_GPIOF, RCC_MP_NS_AHB4ENSETR, 5), 240 CFG_GATE_SETCLR(GATE_GPIOG, RCC_MP_NS_AHB4ENSETR, 6), 241 CFG_GATE_SETCLR(GATE_GPIOH, RCC_MP_NS_AHB4ENSETR, 7), 242 CFG_GATE_SETCLR(GATE_GPIOI, RCC_MP_NS_AHB4ENSETR, 8), 243 CFG_GATE_SETCLR(GATE_PKA, RCC_MP_AHB5ENSETR, 2), 244 CFG_GATE_SETCLR(GATE_SAES, RCC_MP_AHB5ENSETR, 3), 245 CFG_GATE_SETCLR(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4), 246 CFG_GATE_SETCLR(GATE_HASH1, RCC_MP_AHB5ENSETR, 5), 247 CFG_GATE_SETCLR(GATE_RNG1, RCC_MP_AHB5ENSETR, 6), 248 CFG_GATE_SETCLR(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8), 249 CFG_GATE_SETCLR(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16), 250 CFG_GATE_SETCLR(GATE_MCE, RCC_MP_AHB6ENSETR, 1), 251 CFG_GATE_SETCLR(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7), 252 CFG_GATE_SETCLR(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8), 253 CFG_GATE_SETCLR(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9), 254 CFG_GATE_SETCLR(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10), 255 CFG_GATE_SETCLR(GATE_FMC, RCC_MP_AHB6ENSETR, 12), 256 CFG_GATE_SETCLR(GATE_QSPI, RCC_MP_AHB6ENSETR, 14), 257 CFG_GATE_SETCLR(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16), 258 CFG_GATE_SETCLR(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17), 259 CFG_GATE_SETCLR(GATE_CRC1, RCC_MP_AHB6ENSETR, 20), 260 CFG_GATE_SETCLR(GATE_USBH, RCC_MP_AHB6ENSETR, 24), 261 CFG_GATE_SETCLR(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27), 262 CFG_GATE_SETCLR(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28), 263 CFG_GATE_SETCLR(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29), 264 CFG_GATE_SETCLR(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30), 265 CFG_GATE_SETCLR(GATE_ETH1STP, RCC_MP_AHB6LPENSETR, 11), 266 CFG_GATE_SETCLR(GATE_ETH2STP, RCC_MP_AHB6LPENSETR, 31), 267 CFG_GATE_SETCLR(GATE_MDMA, RCC_MP_NS_AHB6ENSETR, 0), 268 }; 269 270 /* STM32 Divivers definition */ 271 enum enum_div_cfg { 272 DIV_RTC, 273 DIV_HSI, 274 DIV_MCO1, 275 DIV_MCO2, 276 DIV_TRACE, 277 DIV_ETH1PTP, 278 DIV_ETH2PTP, 279 DIV_NB 280 }; 281 282 static const struct clk_div_table ck_trace_div_table[] = { 283 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 284 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 }, 285 { 0 }, 286 }; 287 288 #define CFG_DIV(_id, _offset, _shift, _width, _flags, _table, _ready)\ 289 [(_id)] = {\ 290 .offset = (_offset),\ 291 .shift = (_shift),\ 292 .width = (_width),\ 293 .flags = (_flags),\ 294 .table = (_table),\ 295 .ready = (_ready),\ 296 } 297 298 static const struct stm32_div_cfg stm32mp13_dividers[DIV_NB] = { 299 CFG_DIV(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY), 300 CFG_DIV(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_RDY), 301 CFG_DIV(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_RDY), 302 CFG_DIV(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table, DIV_NO_RDY), 303 CFG_DIV(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_RDY), 304 CFG_DIV(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_RDY), 305 }; 306 307 /* STM32 Muxes definition */ 308 enum enum_mux_cfg { 309 MUX_ADC1, 310 MUX_ADC2, 311 MUX_DCMIPP, 312 MUX_ETH1, 313 MUX_ETH2, 314 MUX_FDCAN, 315 MUX_FMC, 316 MUX_I2C12, 317 MUX_I2C3, 318 MUX_I2C4, 319 MUX_I2C5, 320 MUX_LPTIM1, 321 MUX_LPTIM2, 322 MUX_LPTIM3, 323 MUX_LPTIM45, 324 MUX_MCO1, 325 MUX_MCO2, 326 MUX_QSPI, 327 MUX_RNG1, 328 MUX_SAES, 329 MUX_SAI1, 330 MUX_SAI2, 331 MUX_SDMMC1, 332 MUX_SDMMC2, 333 MUX_SPDIF, 334 MUX_SPI1, 335 MUX_SPI23, 336 MUX_SPI4, 337 MUX_SPI5, 338 MUX_STGEN, 339 MUX_UART1, 340 MUX_UART2, 341 MUX_UART4, 342 MUX_UART6, 343 MUX_UART35, 344 MUX_UART78, 345 MUX_USBO, 346 MUX_USBPHY, 347 MUX_NB 348 }; 349 350 #define _CFG_MUX(_id, _offset, _shift, _witdh, _ready, _flags)\ 351 [_id] = {\ 352 .offset = (_offset),\ 353 .shift = (_shift),\ 354 .width = (_witdh),\ 355 .ready = (_ready),\ 356 .flags = (_flags),\ 357 } 358 359 #define CFG_MUX(_id, _offset, _shift, _witdh)\ 360 _CFG_MUX(_id, _offset, _shift, _witdh, MUX_NO_RDY, 0) 361 362 static const struct stm32_mux_cfg stm32mp13_muxes[] = { 363 CFG_MUX(MUX_I2C12, RCC_I2C12CKSELR, 0, 3), 364 CFG_MUX(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3), 365 CFG_MUX(MUX_SPI23, RCC_SPI2S23CKSELR, 0, 3), 366 CFG_MUX(MUX_UART35, RCC_UART35CKSELR, 0, 3), 367 CFG_MUX(MUX_UART78, RCC_UART78CKSELR, 0, 3), 368 CFG_MUX(MUX_ADC1, RCC_ADC12CKSELR, 0, 2), 369 CFG_MUX(MUX_ADC2, RCC_ADC12CKSELR, 2, 2), 370 CFG_MUX(MUX_DCMIPP, RCC_DCMIPPCKSELR, 0, 2), 371 CFG_MUX(MUX_ETH1, RCC_ETH12CKSELR, 0, 2), 372 CFG_MUX(MUX_ETH2, RCC_ETH12CKSELR, 8, 2), 373 CFG_MUX(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2), 374 CFG_MUX(MUX_I2C3, RCC_I2C345CKSELR, 0, 3), 375 CFG_MUX(MUX_I2C4, RCC_I2C345CKSELR, 3, 3), 376 CFG_MUX(MUX_I2C5, RCC_I2C345CKSELR, 6, 3), 377 CFG_MUX(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3), 378 CFG_MUX(MUX_LPTIM2, RCC_LPTIM23CKSELR, 0, 3), 379 CFG_MUX(MUX_LPTIM3, RCC_LPTIM23CKSELR, 3, 3), 380 CFG_MUX(MUX_MCO1, RCC_MCO1CFGR, 0, 3), 381 CFG_MUX(MUX_MCO2, RCC_MCO2CFGR, 0, 3), 382 CFG_MUX(MUX_RNG1, RCC_RNG1CKSELR, 0, 2), 383 CFG_MUX(MUX_SAES, RCC_SAESCKSELR, 0, 2), 384 CFG_MUX(MUX_SAI1, RCC_SAI1CKSELR, 0, 3), 385 CFG_MUX(MUX_SAI2, RCC_SAI2CKSELR, 0, 3), 386 CFG_MUX(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2), 387 CFG_MUX(MUX_SPI1, RCC_SPI2S1CKSELR, 0, 3), 388 CFG_MUX(MUX_SPI4, RCC_SPI45CKSELR, 0, 3), 389 CFG_MUX(MUX_SPI5, RCC_SPI45CKSELR, 3, 3), 390 CFG_MUX(MUX_STGEN, RCC_STGENCKSELR, 0, 2), 391 CFG_MUX(MUX_UART1, RCC_UART12CKSELR, 0, 3), 392 CFG_MUX(MUX_UART2, RCC_UART12CKSELR, 3, 3), 393 CFG_MUX(MUX_UART4, RCC_UART4CKSELR, 0, 3), 394 CFG_MUX(MUX_UART6, RCC_UART6CKSELR, 0, 3), 395 CFG_MUX(MUX_USBO, RCC_USBCKSELR, 4, 1), 396 CFG_MUX(MUX_USBPHY, RCC_USBCKSELR, 0, 2), 397 CFG_MUX(MUX_FMC, RCC_FMCCKSELR, 0, 2), 398 CFG_MUX(MUX_QSPI, RCC_QSPICKSELR, 0, 2), 399 CFG_MUX(MUX_SDMMC1, RCC_SDMMC12CKSELR, 0, 3), 400 CFG_MUX(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3), 401 }; 402 403 struct clk_stm32_securiy { 404 u32 offset; 405 u8 bit_idx; 406 unsigned long scmi_id; 407 }; 408 409 enum security_clk { 410 SECF_NONE, 411 SECF_LPTIM2, 412 SECF_LPTIM3, 413 SECF_VREF, 414 SECF_DCMIPP, 415 SECF_USBPHY, 416 SECF_TZC, 417 SECF_ETZPC, 418 SECF_IWDG1, 419 SECF_BSEC, 420 SECF_STGENC, 421 SECF_STGENRO, 422 SECF_USART1, 423 SECF_USART2, 424 SECF_SPI4, 425 SECF_SPI5, 426 SECF_I2C3, 427 SECF_I2C4, 428 SECF_I2C5, 429 SECF_TIM12, 430 SECF_TIM13, 431 SECF_TIM14, 432 SECF_TIM15, 433 SECF_TIM16, 434 SECF_TIM17, 435 SECF_DMA3, 436 SECF_DMAMUX2, 437 SECF_ADC1, 438 SECF_ADC2, 439 SECF_USBO, 440 SECF_TSC, 441 SECF_PKA, 442 SECF_SAES, 443 SECF_CRYP1, 444 SECF_HASH1, 445 SECF_RNG1, 446 SECF_BKPSRAM, 447 SECF_MCE, 448 SECF_FMC, 449 SECF_QSPI, 450 SECF_SDMMC1, 451 SECF_SDMMC2, 452 SECF_ETH1CK, 453 SECF_ETH1TX, 454 SECF_ETH1RX, 455 SECF_ETH1MAC, 456 SECF_ETH1STP, 457 SECF_ETH2CK, 458 SECF_ETH2TX, 459 SECF_ETH2RX, 460 SECF_ETH2MAC, 461 SECF_ETH2STP, 462 SECF_MCO1, 463 SECF_MCO2 464 }; 465 466 #define SECF(_sec_id, _offset, _bit_idx)[_sec_id] = {\ 467 .offset = _offset,\ 468 .bit_idx = _bit_idx,\ 469 .scmi_id = -1,\ 470 } 471 472 static const struct clk_stm32_securiy stm32mp13_security[] = { 473 SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF), 474 SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF), 475 SECF(SECF_VREF, RCC_APB3SECSR, RCC_APB3SECSR_VREFSECF), 476 SECF(SECF_DCMIPP, RCC_APB4SECSR, RCC_APB4SECSR_DCMIPPSECF), 477 SECF(SECF_USBPHY, RCC_APB4SECSR, RCC_APB4SECSR_USBPHYSECF), 478 SECF(SECF_TZC, RCC_APB5SECSR, RCC_APB5SECSR_TZCSECF), 479 SECF(SECF_ETZPC, RCC_APB5SECSR, RCC_APB5SECSR_ETZPCSECF), 480 SECF(SECF_IWDG1, RCC_APB5SECSR, RCC_APB5SECSR_IWDG1SECF), 481 SECF(SECF_BSEC, RCC_APB5SECSR, RCC_APB5SECSR_BSECSECF), 482 SECF(SECF_STGENC, RCC_APB5SECSR, RCC_APB5SECSR_STGENCSECF), 483 SECF(SECF_STGENRO, RCC_APB5SECSR, RCC_APB5SECSR_STGENROSECF), 484 SECF(SECF_USART1, RCC_APB6SECSR, RCC_APB6SECSR_USART1SECF), 485 SECF(SECF_USART2, RCC_APB6SECSR, RCC_APB6SECSR_USART2SECF), 486 SECF(SECF_SPI4, RCC_APB6SECSR, RCC_APB6SECSR_SPI4SECF), 487 SECF(SECF_SPI5, RCC_APB6SECSR, RCC_APB6SECSR_SPI5SECF), 488 SECF(SECF_I2C3, RCC_APB6SECSR, RCC_APB6SECSR_I2C3SECF), 489 SECF(SECF_I2C4, RCC_APB6SECSR, RCC_APB6SECSR_I2C4SECF), 490 SECF(SECF_I2C5, RCC_APB6SECSR, RCC_APB6SECSR_I2C5SECF), 491 SECF(SECF_TIM12, RCC_APB6SECSR, RCC_APB6SECSR_TIM12SECF), 492 SECF(SECF_TIM13, RCC_APB6SECSR, RCC_APB6SECSR_TIM13SECF), 493 SECF(SECF_TIM14, RCC_APB6SECSR, RCC_APB6SECSR_TIM14SECF), 494 SECF(SECF_TIM15, RCC_APB6SECSR, RCC_APB6SECSR_TIM15SECF), 495 SECF(SECF_TIM16, RCC_APB6SECSR, RCC_APB6SECSR_TIM16SECF), 496 SECF(SECF_TIM17, RCC_APB6SECSR, RCC_APB6SECSR_TIM17SECF), 497 SECF(SECF_DMA3, RCC_AHB2SECSR, RCC_AHB2SECSR_DMA3SECF), 498 SECF(SECF_DMAMUX2, RCC_AHB2SECSR, RCC_AHB2SECSR_DMAMUX2SECF), 499 SECF(SECF_ADC1, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC1SECF), 500 SECF(SECF_ADC2, RCC_AHB2SECSR, RCC_AHB2SECSR_ADC2SECF), 501 SECF(SECF_USBO, RCC_AHB2SECSR, RCC_AHB2SECSR_USBOSECF), 502 SECF(SECF_TSC, RCC_AHB4SECSR, RCC_AHB4SECSR_TSCSECF), 503 SECF(SECF_PKA, RCC_AHB5SECSR, RCC_AHB5SECSR_PKASECF), 504 SECF(SECF_SAES, RCC_AHB5SECSR, RCC_AHB5SECSR_SAESSECF), 505 SECF(SECF_CRYP1, RCC_AHB5SECSR, RCC_AHB5SECSR_CRYP1SECF), 506 SECF(SECF_HASH1, RCC_AHB5SECSR, RCC_AHB5SECSR_HASH1SECF), 507 SECF(SECF_RNG1, RCC_AHB5SECSR, RCC_AHB5SECSR_RNG1SECF), 508 SECF(SECF_BKPSRAM, RCC_AHB5SECSR, RCC_AHB5SECSR_BKPSRAMSECF), 509 SECF(SECF_MCE, RCC_AHB6SECSR, RCC_AHB6SECSR_MCESECF), 510 SECF(SECF_FMC, RCC_AHB6SECSR, RCC_AHB6SECSR_FMCSECF), 511 SECF(SECF_QSPI, RCC_AHB6SECSR, RCC_AHB6SECSR_QSPISECF), 512 SECF(SECF_SDMMC1, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC1SECF), 513 SECF(SECF_SDMMC2, RCC_AHB6SECSR, RCC_AHB6SECSR_SDMMC2SECF), 514 SECF(SECF_ETH1CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1CKSECF), 515 SECF(SECF_ETH1TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1TXSECF), 516 SECF(SECF_ETH1RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1RXSECF), 517 SECF(SECF_ETH1MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1MACSECF), 518 SECF(SECF_ETH1STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH1STPSECF), 519 SECF(SECF_ETH2CK, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2CKSECF), 520 SECF(SECF_ETH2TX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2TXSECF), 521 SECF(SECF_ETH2RX, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2RXSECF), 522 SECF(SECF_ETH2MAC, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2MACSECF), 523 SECF(SECF_ETH2STP, RCC_AHB6SECSR, RCC_AHB6SECSR_ETH2STPSECF), 524 SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SEC), 525 SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SEC), 526 }; 527 528 static const char * const adc12_src[] = { 529 "pll4_r", "ck_per", "pll3_q" 530 }; 531 532 static const char * const dcmipp_src[] = { 533 "ck_axi", "pll2_q", "pll4_p", "ck_per", 534 }; 535 536 static const char * const eth12_src[] = { 537 "pll4_p", "pll3_q" 538 }; 539 540 static const char * const fdcan_src[] = { 541 "ck_hse", "pll3_q", "pll4_q", "pll4_r" 542 }; 543 544 static const char * const fmc_src[] = { 545 "ck_axi", "pll3_r", "pll4_p", "ck_per" 546 }; 547 548 static const char * const i2c12_src[] = { 549 "pclk1", "pll4_r", "ck_hsi", "ck_csi" 550 }; 551 552 static const char * const i2c345_src[] = { 553 "pclk6", "pll4_r", "ck_hsi", "ck_csi" 554 }; 555 556 static const char * const lptim1_src[] = { 557 "pclk1", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per" 558 }; 559 560 static const char * const lptim23_src[] = { 561 "pclk3", "pll4_q", "ck_per", "ck_lse", "ck_lsi" 562 }; 563 564 static const char * const lptim45_src[] = { 565 "pclk3", "pll4_p", "pll3_q", "ck_lse", "ck_lsi", "ck_per" 566 }; 567 568 static const char * const mco1_src[] = { 569 "ck_hsi", "ck_hse", "ck_csi", "ck_lsi", "ck_lse" 570 }; 571 572 static const char * const mco2_src[] = { 573 "ck_mpu", "ck_axi", "ck_mlahb", "pll4_p", "ck_hse", "ck_hsi" 574 }; 575 576 static const char * const qspi_src[] = { 577 "ck_axi", "pll3_r", "pll4_p", "ck_per" 578 }; 579 580 static const char * const rng1_src[] = { 581 "ck_csi", "pll4_r", "ck_lse", "ck_lsi" 582 }; 583 584 static const char * const saes_src[] = { 585 "ck_axi", "ck_per", "pll4_r", "ck_lsi" 586 }; 587 588 static const char * const sai1_src[] = { 589 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "pll3_r" 590 }; 591 592 static const char * const sai2_src[] = { 593 "pll4_q", "pll3_q", "i2s_ckin", "ck_per", "spdif_ck_symb", "pll3_r" 594 }; 595 596 static const char * const sdmmc12_src[] = { 597 "ck_axi", "pll3_r", "pll4_p", "ck_hsi" 598 }; 599 600 static const char * const spdif_src[] = { 601 "pll4_p", "pll3_q", "ck_hsi" 602 }; 603 604 static const char * const spi123_src[] = { 605 "pll4_p", "pll3_q", "i2s_ckin", "ck_per", "pll3_r" 606 }; 607 608 static const char * const spi4_src[] = { 609 "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse", "i2s_ckin" 610 }; 611 612 static const char * const spi5_src[] = { 613 "pclk6", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" 614 }; 615 616 static const char * const stgen_src[] = { 617 "ck_hsi", "ck_hse" 618 }; 619 620 static const char * const usart12_src[] = { 621 "pclk6", "pll3_q", "ck_hsi", "ck_csi", "pll4_q", "ck_hse" 622 }; 623 624 static const char * const usart34578_src[] = { 625 "pclk1", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" 626 }; 627 628 static const char * const usart6_src[] = { 629 "pclk2", "pll4_q", "ck_hsi", "ck_csi", "ck_hse" 630 }; 631 632 static const char * const usbo_src[] = { 633 "pll4_r", "ck_usbo_48m" 634 }; 635 636 static const char * const usbphy_src[] = { 637 "ck_hse", "pll4_r", "clk-hse-div2" 638 }; 639 640 /* Timer clocks */ 641 static struct clk_stm32_gate tim2_k = { 642 .gate_id = GATE_TIM2, 643 .hw.init = CLK_HW_INIT("tim2_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 644 }; 645 646 static struct clk_stm32_gate tim3_k = { 647 .gate_id = GATE_TIM3, 648 .hw.init = CLK_HW_INIT("tim3_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 649 }; 650 651 static struct clk_stm32_gate tim4_k = { 652 .gate_id = GATE_TIM4, 653 .hw.init = CLK_HW_INIT("tim4_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 654 }; 655 656 static struct clk_stm32_gate tim5_k = { 657 .gate_id = GATE_TIM5, 658 .hw.init = CLK_HW_INIT("tim5_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 659 }; 660 661 static struct clk_stm32_gate tim6_k = { 662 .gate_id = GATE_TIM6, 663 .hw.init = CLK_HW_INIT("tim6_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 664 }; 665 666 static struct clk_stm32_gate tim7_k = { 667 .gate_id = GATE_TIM7, 668 .hw.init = CLK_HW_INIT("tim7_k", "timg1_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 669 }; 670 671 static struct clk_stm32_gate tim1_k = { 672 .gate_id = GATE_TIM1, 673 .hw.init = CLK_HW_INIT("tim1_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 674 }; 675 676 static struct clk_stm32_gate tim8_k = { 677 .gate_id = GATE_TIM8, 678 .hw.init = CLK_HW_INIT("tim8_k", "timg2_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 679 }; 680 681 static struct clk_stm32_gate tim12_k = { 682 .gate_id = GATE_TIM12, 683 .hw.init = CLK_HW_INIT("tim12_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 684 }; 685 686 static struct clk_stm32_gate tim13_k = { 687 .gate_id = GATE_TIM13, 688 .hw.init = CLK_HW_INIT("tim13_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 689 }; 690 691 static struct clk_stm32_gate tim14_k = { 692 .gate_id = GATE_TIM14, 693 .hw.init = CLK_HW_INIT("tim14_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 694 }; 695 696 static struct clk_stm32_gate tim15_k = { 697 .gate_id = GATE_TIM15, 698 .hw.init = CLK_HW_INIT("tim15_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 699 }; 700 701 static struct clk_stm32_gate tim16_k = { 702 .gate_id = GATE_TIM16, 703 .hw.init = CLK_HW_INIT("tim16_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 704 }; 705 706 static struct clk_stm32_gate tim17_k = { 707 .gate_id = GATE_TIM17, 708 .hw.init = CLK_HW_INIT("tim17_k", "timg3_ck", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 709 }; 710 711 /* Peripheral clocks */ 712 static struct clk_stm32_gate sai1 = { 713 .gate_id = GATE_SAI1, 714 .hw.init = CLK_HW_INIT("sai1", "pclk2", &clk_stm32_gate_ops, 0), 715 }; 716 717 static struct clk_stm32_gate sai2 = { 718 .gate_id = GATE_SAI2, 719 .hw.init = CLK_HW_INIT("sai2", "pclk2", &clk_stm32_gate_ops, 0), 720 }; 721 722 static struct clk_stm32_gate syscfg = { 723 .gate_id = GATE_SYSCFG, 724 .hw.init = CLK_HW_INIT("syscfg", "pclk3", &clk_stm32_gate_ops, 0), 725 }; 726 727 static struct clk_stm32_gate vref = { 728 .gate_id = GATE_VREF, 729 .hw.init = CLK_HW_INIT("vref", "pclk3", &clk_stm32_gate_ops, 0), 730 }; 731 732 static struct clk_stm32_gate dts = { 733 .gate_id = GATE_DTS, 734 .hw.init = CLK_HW_INIT("dts", "pclk3", &clk_stm32_gate_ops, 0), 735 }; 736 737 static struct clk_stm32_gate pmbctrl = { 738 .gate_id = GATE_PMBCTRL, 739 .hw.init = CLK_HW_INIT("pmbctrl", "pclk3", &clk_stm32_gate_ops, 0), 740 }; 741 742 static struct clk_stm32_gate hdp = { 743 .gate_id = GATE_HDP, 744 .hw.init = CLK_HW_INIT("hdp", "pclk3", &clk_stm32_gate_ops, 0), 745 }; 746 747 static struct clk_stm32_gate iwdg2 = { 748 .gate_id = GATE_IWDG2APB, 749 .hw.init = CLK_HW_INIT("iwdg2", "pclk4", &clk_stm32_gate_ops, 0), 750 }; 751 752 static struct clk_stm32_gate stgenro = { 753 .gate_id = GATE_STGENRO, 754 .hw.init = CLK_HW_INIT("stgenro", "pclk4", &clk_stm32_gate_ops, 0), 755 }; 756 757 static struct clk_stm32_gate gpioa = { 758 .gate_id = GATE_GPIOA, 759 .hw.init = CLK_HW_INIT("gpioa", "pclk4", &clk_stm32_gate_ops, 0), 760 }; 761 762 static struct clk_stm32_gate gpiob = { 763 .gate_id = GATE_GPIOB, 764 .hw.init = CLK_HW_INIT("gpiob", "pclk4", &clk_stm32_gate_ops, 0), 765 }; 766 767 static struct clk_stm32_gate gpioc = { 768 .gate_id = GATE_GPIOC, 769 .hw.init = CLK_HW_INIT("gpioc", "pclk4", &clk_stm32_gate_ops, 0), 770 }; 771 772 static struct clk_stm32_gate gpiod = { 773 .gate_id = GATE_GPIOD, 774 .hw.init = CLK_HW_INIT("gpiod", "pclk4", &clk_stm32_gate_ops, 0), 775 }; 776 777 static struct clk_stm32_gate gpioe = { 778 .gate_id = GATE_GPIOE, 779 .hw.init = CLK_HW_INIT("gpioe", "pclk4", &clk_stm32_gate_ops, 0), 780 }; 781 782 static struct clk_stm32_gate gpiof = { 783 .gate_id = GATE_GPIOF, 784 .hw.init = CLK_HW_INIT("gpiof", "pclk4", &clk_stm32_gate_ops, 0), 785 }; 786 787 static struct clk_stm32_gate gpiog = { 788 .gate_id = GATE_GPIOG, 789 .hw.init = CLK_HW_INIT("gpiog", "pclk4", &clk_stm32_gate_ops, 0), 790 }; 791 792 static struct clk_stm32_gate gpioh = { 793 .gate_id = GATE_GPIOH, 794 .hw.init = CLK_HW_INIT("gpioh", "pclk4", &clk_stm32_gate_ops, 0), 795 }; 796 797 static struct clk_stm32_gate gpioi = { 798 .gate_id = GATE_GPIOI, 799 .hw.init = CLK_HW_INIT("gpioi", "pclk4", &clk_stm32_gate_ops, 0), 800 }; 801 802 static struct clk_stm32_gate tsc = { 803 .gate_id = GATE_TSC, 804 .hw.init = CLK_HW_INIT("tsc", "pclk4", &clk_stm32_gate_ops, 0), 805 }; 806 807 static struct clk_stm32_gate ddrperfm = { 808 .gate_id = GATE_DDRPERFM, 809 .hw.init = CLK_HW_INIT("ddrperfm", "pclk4", &clk_stm32_gate_ops, 0), 810 }; 811 812 static struct clk_stm32_gate tzpc = { 813 .gate_id = GATE_TZC, 814 .hw.init = CLK_HW_INIT("tzpc", "pclk5", &clk_stm32_gate_ops, 0), 815 }; 816 817 static struct clk_stm32_gate iwdg1 = { 818 .gate_id = GATE_IWDG1APB, 819 .hw.init = CLK_HW_INIT("iwdg1", "pclk5", &clk_stm32_gate_ops, 0), 820 }; 821 822 static struct clk_stm32_gate bsec = { 823 .gate_id = GATE_BSEC, 824 .hw.init = CLK_HW_INIT("bsec", "pclk5", &clk_stm32_gate_ops, 0), 825 }; 826 827 static struct clk_stm32_gate dma1 = { 828 .gate_id = GATE_DMA1, 829 .hw.init = CLK_HW_INIT("dma1", "ck_mlahb", &clk_stm32_gate_ops, 0), 830 }; 831 832 static struct clk_stm32_gate dma2 = { 833 .gate_id = GATE_DMA2, 834 .hw.init = CLK_HW_INIT("dma2", "ck_mlahb", &clk_stm32_gate_ops, 0), 835 }; 836 837 static struct clk_stm32_gate dmamux1 = { 838 .gate_id = GATE_DMAMUX1, 839 .hw.init = CLK_HW_INIT("dmamux1", "ck_mlahb", &clk_stm32_gate_ops, 0), 840 }; 841 842 static struct clk_stm32_gate dma3 = { 843 .gate_id = GATE_DMA3, 844 .hw.init = CLK_HW_INIT("dma3", "ck_mlahb", &clk_stm32_gate_ops, 0), 845 }; 846 847 static struct clk_stm32_gate dmamux2 = { 848 .gate_id = GATE_DMAMUX2, 849 .hw.init = CLK_HW_INIT("dmamux2", "ck_mlahb", &clk_stm32_gate_ops, 0), 850 }; 851 852 static struct clk_stm32_gate adc1 = { 853 .gate_id = GATE_ADC1, 854 .hw.init = CLK_HW_INIT("adc1", "ck_mlahb", &clk_stm32_gate_ops, 0), 855 }; 856 857 static struct clk_stm32_gate adc2 = { 858 .gate_id = GATE_ADC2, 859 .hw.init = CLK_HW_INIT("adc2", "ck_mlahb", &clk_stm32_gate_ops, 0), 860 }; 861 862 static struct clk_stm32_gate pka = { 863 .gate_id = GATE_PKA, 864 .hw.init = CLK_HW_INIT("pka", "ck_axi", &clk_stm32_gate_ops, 0), 865 }; 866 867 static struct clk_stm32_gate cryp1 = { 868 .gate_id = GATE_CRYP1, 869 .hw.init = CLK_HW_INIT("cryp1", "ck_axi", &clk_stm32_gate_ops, 0), 870 }; 871 872 static struct clk_stm32_gate hash1 = { 873 .gate_id = GATE_HASH1, 874 .hw.init = CLK_HW_INIT("hash1", "ck_axi", &clk_stm32_gate_ops, 0), 875 }; 876 877 static struct clk_stm32_gate bkpsram = { 878 .gate_id = GATE_BKPSRAM, 879 .hw.init = CLK_HW_INIT("bkpsram", "ck_axi", &clk_stm32_gate_ops, 0), 880 }; 881 882 static struct clk_stm32_gate mdma = { 883 .gate_id = GATE_MDMA, 884 .hw.init = CLK_HW_INIT("mdma", "ck_axi", &clk_stm32_gate_ops, 0), 885 }; 886 887 static struct clk_stm32_gate eth1tx = { 888 .gate_id = GATE_ETH1TX, 889 .hw.init = CLK_HW_INIT("eth1tx", "ck_axi", &clk_stm32_gate_ops, 0), 890 }; 891 892 static struct clk_stm32_gate eth1rx = { 893 .gate_id = GATE_ETH1RX, 894 .hw.init = CLK_HW_INIT("eth1rx", "ck_axi", &clk_stm32_gate_ops, 0), 895 }; 896 897 static struct clk_stm32_gate eth1mac = { 898 .gate_id = GATE_ETH1MAC, 899 .hw.init = CLK_HW_INIT("eth1mac", "ck_axi", &clk_stm32_gate_ops, 0), 900 }; 901 902 static struct clk_stm32_gate eth2tx = { 903 .gate_id = GATE_ETH2TX, 904 .hw.init = CLK_HW_INIT("eth2tx", "ck_axi", &clk_stm32_gate_ops, 0), 905 }; 906 907 static struct clk_stm32_gate eth2rx = { 908 .gate_id = GATE_ETH2RX, 909 .hw.init = CLK_HW_INIT("eth2rx", "ck_axi", &clk_stm32_gate_ops, 0), 910 }; 911 912 static struct clk_stm32_gate eth2mac = { 913 .gate_id = GATE_ETH2MAC, 914 .hw.init = CLK_HW_INIT("eth2mac", "ck_axi", &clk_stm32_gate_ops, 0), 915 }; 916 917 static struct clk_stm32_gate crc1 = { 918 .gate_id = GATE_CRC1, 919 .hw.init = CLK_HW_INIT("crc1", "ck_axi", &clk_stm32_gate_ops, 0), 920 }; 921 922 static struct clk_stm32_gate usbh = { 923 .gate_id = GATE_USBH, 924 .hw.init = CLK_HW_INIT("usbh", "ck_axi", &clk_stm32_gate_ops, 0), 925 }; 926 927 static struct clk_stm32_gate eth1stp = { 928 .gate_id = GATE_ETH1STP, 929 .hw.init = CLK_HW_INIT("eth1stp", "ck_axi", &clk_stm32_gate_ops, 0), 930 }; 931 932 static struct clk_stm32_gate eth2stp = { 933 .gate_id = GATE_ETH2STP, 934 .hw.init = CLK_HW_INIT("eth2stp", "ck_axi", &clk_stm32_gate_ops, 0), 935 }; 936 937 /* Kernel clocks */ 938 static struct clk_stm32_composite sdmmc1_k = { 939 .gate_id = GATE_SDMMC1, 940 .mux_id = MUX_SDMMC1, 941 .div_id = NO_STM32_DIV, 942 .hw.init = CLK_HW_INIT_PARENTS("sdmmc1_k", sdmmc12_src, &clk_stm32_composite_ops, 943 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 944 }; 945 946 static struct clk_stm32_composite sdmmc2_k = { 947 .gate_id = GATE_SDMMC2, 948 .mux_id = MUX_SDMMC2, 949 .div_id = NO_STM32_DIV, 950 .hw.init = CLK_HW_INIT_PARENTS("sdmmc2_k", sdmmc12_src, &clk_stm32_composite_ops, 951 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 952 }; 953 954 static struct clk_stm32_composite fmc_k = { 955 .gate_id = GATE_FMC, 956 .mux_id = MUX_FMC, 957 .div_id = NO_STM32_DIV, 958 .hw.init = CLK_HW_INIT_PARENTS("fmc_k", fmc_src, &clk_stm32_composite_ops, 959 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 960 }; 961 962 static struct clk_stm32_composite qspi_k = { 963 .gate_id = GATE_QSPI, 964 .mux_id = MUX_QSPI, 965 .div_id = NO_STM32_DIV, 966 .hw.init = CLK_HW_INIT_PARENTS("qspi_k", qspi_src, &clk_stm32_composite_ops, 967 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 968 }; 969 970 static struct clk_stm32_composite spi2_k = { 971 .gate_id = GATE_SPI2, 972 .mux_id = MUX_SPI23, 973 .div_id = NO_STM32_DIV, 974 .hw.init = CLK_HW_INIT_PARENTS("spi2_k", spi123_src, &clk_stm32_composite_ops, 975 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 976 }; 977 978 static struct clk_stm32_composite spi3_k = { 979 .gate_id = GATE_SPI3, 980 .mux_id = MUX_SPI23, 981 .div_id = NO_STM32_DIV, 982 .hw.init = CLK_HW_INIT_PARENTS("spi3_k", spi123_src, &clk_stm32_composite_ops, 983 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 984 }; 985 986 static struct clk_stm32_composite i2c1_k = { 987 .gate_id = GATE_I2C1, 988 .mux_id = MUX_I2C12, 989 .div_id = NO_STM32_DIV, 990 .hw.init = CLK_HW_INIT_PARENTS("i2c1_k", i2c12_src, &clk_stm32_composite_ops, 991 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 992 }; 993 994 static struct clk_stm32_composite i2c2_k = { 995 .gate_id = GATE_I2C2, 996 .mux_id = MUX_I2C12, 997 .div_id = NO_STM32_DIV, 998 .hw.init = CLK_HW_INIT_PARENTS("i2c2_k", i2c12_src, &clk_stm32_composite_ops, 999 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1000 }; 1001 1002 static struct clk_stm32_composite lptim4_k = { 1003 .gate_id = GATE_LPTIM4, 1004 .mux_id = MUX_LPTIM45, 1005 .div_id = NO_STM32_DIV, 1006 .hw.init = CLK_HW_INIT_PARENTS("lptim4_k", lptim45_src, &clk_stm32_composite_ops, 1007 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1008 }; 1009 1010 static struct clk_stm32_composite lptim5_k = { 1011 .gate_id = GATE_LPTIM5, 1012 .mux_id = MUX_LPTIM45, 1013 .div_id = NO_STM32_DIV, 1014 .hw.init = CLK_HW_INIT_PARENTS("lptim5_k", lptim45_src, &clk_stm32_composite_ops, 1015 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1016 }; 1017 1018 static struct clk_stm32_composite usart3_k = { 1019 .gate_id = GATE_USART3, 1020 .mux_id = MUX_UART35, 1021 .div_id = NO_STM32_DIV, 1022 .hw.init = CLK_HW_INIT_PARENTS("usart3_k", usart34578_src, &clk_stm32_composite_ops, 1023 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1024 }; 1025 1026 static struct clk_stm32_composite uart5_k = { 1027 .gate_id = GATE_UART5, 1028 .mux_id = MUX_UART35, 1029 .div_id = NO_STM32_DIV, 1030 .hw.init = CLK_HW_INIT_PARENTS("uart5_k", usart34578_src, &clk_stm32_composite_ops, 1031 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1032 }; 1033 1034 static struct clk_stm32_composite uart7_k = { 1035 .gate_id = GATE_UART7, 1036 .mux_id = MUX_UART78, 1037 .div_id = NO_STM32_DIV, 1038 .hw.init = CLK_HW_INIT_PARENTS("uart7_k", usart34578_src, &clk_stm32_composite_ops, 1039 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1040 }; 1041 1042 static struct clk_stm32_composite uart8_k = { 1043 .gate_id = GATE_UART8, 1044 .mux_id = MUX_UART78, 1045 .div_id = NO_STM32_DIV, 1046 .hw.init = CLK_HW_INIT_PARENTS("uart8_k", usart34578_src, &clk_stm32_composite_ops, 1047 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1048 }; 1049 1050 static struct clk_stm32_composite sai1_k = { 1051 .gate_id = GATE_SAI1, 1052 .mux_id = MUX_SAI1, 1053 .div_id = NO_STM32_DIV, 1054 .hw.init = CLK_HW_INIT_PARENTS("sai1_k", sai1_src, &clk_stm32_composite_ops, 1055 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1056 }; 1057 1058 static struct clk_stm32_composite adfsdm_k = { 1059 .gate_id = GATE_ADFSDM, 1060 .mux_id = MUX_SAI1, 1061 .div_id = NO_STM32_DIV, 1062 .hw.init = CLK_HW_INIT_PARENTS("adfsdm_k", sai1_src, &clk_stm32_composite_ops, 1063 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1064 }; 1065 1066 static struct clk_stm32_composite sai2_k = { 1067 .gate_id = GATE_SAI2, 1068 .mux_id = MUX_SAI2, 1069 .div_id = NO_STM32_DIV, 1070 .hw.init = CLK_HW_INIT_PARENTS("sai2_k", sai2_src, &clk_stm32_composite_ops, 1071 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1072 }; 1073 1074 static struct clk_stm32_composite adc1_k = { 1075 .gate_id = GATE_ADC1, 1076 .mux_id = MUX_ADC1, 1077 .div_id = NO_STM32_DIV, 1078 .hw.init = CLK_HW_INIT_PARENTS("adc1_k", adc12_src, &clk_stm32_composite_ops, 1079 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1080 }; 1081 1082 static struct clk_stm32_composite adc2_k = { 1083 .gate_id = GATE_ADC2, 1084 .mux_id = MUX_ADC2, 1085 .div_id = NO_STM32_DIV, 1086 .hw.init = CLK_HW_INIT_PARENTS("adc2_k", adc12_src, &clk_stm32_composite_ops, 1087 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1088 }; 1089 1090 static struct clk_stm32_composite rng1_k = { 1091 .gate_id = GATE_RNG1, 1092 .mux_id = MUX_RNG1, 1093 .div_id = NO_STM32_DIV, 1094 .hw.init = CLK_HW_INIT_PARENTS("rng1_k", rng1_src, &clk_stm32_composite_ops, 1095 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1096 }; 1097 1098 static struct clk_stm32_composite usbphy_k = { 1099 .gate_id = GATE_USBPHY, 1100 .mux_id = MUX_USBPHY, 1101 .div_id = NO_STM32_DIV, 1102 .hw.init = CLK_HW_INIT_PARENTS("usbphy_k", usbphy_src, &clk_stm32_composite_ops, 1103 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1104 }; 1105 1106 static struct clk_stm32_composite stgen_k = { 1107 .gate_id = GATE_STGENC, 1108 .mux_id = MUX_STGEN, 1109 .div_id = NO_STM32_DIV, 1110 .hw.init = CLK_HW_INIT_PARENTS("stgen_k", stgen_src, &clk_stm32_composite_ops, 1111 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1112 }; 1113 1114 static struct clk_stm32_composite spdif_k = { 1115 .gate_id = GATE_SPDIF, 1116 .mux_id = MUX_SPDIF, 1117 .div_id = NO_STM32_DIV, 1118 .hw.init = CLK_HW_INIT_PARENTS("spdif_k", spdif_src, &clk_stm32_composite_ops, 1119 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1120 }; 1121 1122 static struct clk_stm32_composite spi1_k = { 1123 .gate_id = GATE_SPI1, 1124 .mux_id = MUX_SPI1, 1125 .div_id = NO_STM32_DIV, 1126 .hw.init = CLK_HW_INIT_PARENTS("spi1_k", spi123_src, &clk_stm32_composite_ops, 1127 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1128 }; 1129 1130 static struct clk_stm32_composite spi4_k = { 1131 .gate_id = GATE_SPI4, 1132 .mux_id = MUX_SPI4, 1133 .div_id = NO_STM32_DIV, 1134 .hw.init = CLK_HW_INIT_PARENTS("spi4_k", spi4_src, &clk_stm32_composite_ops, 1135 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1136 }; 1137 1138 static struct clk_stm32_composite spi5_k = { 1139 .gate_id = GATE_SPI5, 1140 .mux_id = MUX_SPI5, 1141 .div_id = NO_STM32_DIV, 1142 .hw.init = CLK_HW_INIT_PARENTS("spi5_k", spi5_src, &clk_stm32_composite_ops, 1143 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1144 }; 1145 1146 static struct clk_stm32_composite i2c3_k = { 1147 .gate_id = GATE_I2C3, 1148 .mux_id = MUX_I2C3, 1149 .div_id = NO_STM32_DIV, 1150 .hw.init = CLK_HW_INIT_PARENTS("i2c3_k", i2c345_src, &clk_stm32_composite_ops, 1151 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1152 }; 1153 1154 static struct clk_stm32_composite i2c4_k = { 1155 .gate_id = GATE_I2C4, 1156 .mux_id = MUX_I2C4, 1157 .div_id = NO_STM32_DIV, 1158 .hw.init = CLK_HW_INIT_PARENTS("i2c4_k", i2c345_src, &clk_stm32_composite_ops, 1159 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1160 }; 1161 1162 static struct clk_stm32_composite i2c5_k = { 1163 .gate_id = GATE_I2C5, 1164 .mux_id = MUX_I2C5, 1165 .div_id = NO_STM32_DIV, 1166 .hw.init = CLK_HW_INIT_PARENTS("i2c5_k", i2c345_src, &clk_stm32_composite_ops, 1167 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1168 }; 1169 1170 static struct clk_stm32_composite lptim1_k = { 1171 .gate_id = GATE_LPTIM1, 1172 .mux_id = MUX_LPTIM1, 1173 .div_id = NO_STM32_DIV, 1174 .hw.init = CLK_HW_INIT_PARENTS("lptim1_k", lptim1_src, &clk_stm32_composite_ops, 1175 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1176 }; 1177 1178 static struct clk_stm32_composite lptim2_k = { 1179 .gate_id = GATE_LPTIM2, 1180 .mux_id = MUX_LPTIM2, 1181 .div_id = NO_STM32_DIV, 1182 .hw.init = CLK_HW_INIT_PARENTS("lptim2_k", lptim23_src, &clk_stm32_composite_ops, 1183 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1184 }; 1185 1186 static struct clk_stm32_composite lptim3_k = { 1187 .gate_id = GATE_LPTIM3, 1188 .mux_id = MUX_LPTIM3, 1189 .div_id = NO_STM32_DIV, 1190 .hw.init = CLK_HW_INIT_PARENTS("lptim3_k", lptim23_src, &clk_stm32_composite_ops, 1191 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1192 }; 1193 1194 static struct clk_stm32_composite usart1_k = { 1195 .gate_id = GATE_USART1, 1196 .mux_id = MUX_UART1, 1197 .div_id = NO_STM32_DIV, 1198 .hw.init = CLK_HW_INIT_PARENTS("usart1_k", usart12_src, &clk_stm32_composite_ops, 1199 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1200 }; 1201 1202 static struct clk_stm32_composite usart2_k = { 1203 .gate_id = GATE_USART2, 1204 .mux_id = MUX_UART2, 1205 .div_id = NO_STM32_DIV, 1206 .hw.init = CLK_HW_INIT_PARENTS("usart2_k", usart12_src, &clk_stm32_composite_ops, 1207 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1208 }; 1209 1210 static struct clk_stm32_composite uart4_k = { 1211 .gate_id = GATE_UART4, 1212 .mux_id = MUX_UART4, 1213 .div_id = NO_STM32_DIV, 1214 .hw.init = CLK_HW_INIT_PARENTS("uart4_k", usart34578_src, &clk_stm32_composite_ops, 1215 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1216 }; 1217 1218 static struct clk_stm32_composite uart6_k = { 1219 .gate_id = GATE_USART6, 1220 .mux_id = MUX_UART6, 1221 .div_id = NO_STM32_DIV, 1222 .hw.init = CLK_HW_INIT_PARENTS("uart6_k", usart6_src, &clk_stm32_composite_ops, 1223 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1224 }; 1225 1226 static struct clk_stm32_composite fdcan_k = { 1227 .gate_id = GATE_FDCAN, 1228 .mux_id = MUX_FDCAN, 1229 .div_id = NO_STM32_DIV, 1230 .hw.init = CLK_HW_INIT_PARENTS("fdcan_k", fdcan_src, &clk_stm32_composite_ops, 1231 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1232 }; 1233 1234 static struct clk_stm32_composite dcmipp_k = { 1235 .gate_id = GATE_DCMIPP, 1236 .mux_id = MUX_DCMIPP, 1237 .div_id = NO_STM32_DIV, 1238 .hw.init = CLK_HW_INIT_PARENTS("dcmipp_k", dcmipp_src, &clk_stm32_composite_ops, 1239 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1240 }; 1241 1242 static struct clk_stm32_composite usbo_k = { 1243 .gate_id = GATE_USBO, 1244 .mux_id = MUX_USBO, 1245 .div_id = NO_STM32_DIV, 1246 .hw.init = CLK_HW_INIT_PARENTS("usbo_k", usbo_src, &clk_stm32_composite_ops, 1247 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1248 }; 1249 1250 static struct clk_stm32_composite saes_k = { 1251 .gate_id = GATE_SAES, 1252 .mux_id = MUX_SAES, 1253 .div_id = NO_STM32_DIV, 1254 .hw.init = CLK_HW_INIT_PARENTS("saes_k", saes_src, &clk_stm32_composite_ops, 1255 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1256 }; 1257 1258 static struct clk_stm32_gate dfsdm_k = { 1259 .gate_id = GATE_DFSDM, 1260 .hw.init = CLK_HW_INIT("dfsdm_k", "ck_mlahb", &clk_stm32_gate_ops, 0), 1261 }; 1262 1263 static struct clk_stm32_gate ltdc_px = { 1264 .gate_id = GATE_LTDC, 1265 .hw.init = CLK_HW_INIT("ltdc_px", "pll4_q", &clk_stm32_gate_ops, CLK_SET_RATE_PARENT), 1266 }; 1267 1268 static struct clk_stm32_mux ck_ker_eth1 = { 1269 .mux_id = MUX_ETH1, 1270 .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth1", eth12_src, &clk_stm32_mux_ops, 1271 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1272 }; 1273 1274 static struct clk_stm32_gate eth1ck_k = { 1275 .gate_id = GATE_ETH1CK, 1276 .hw.init = CLK_HW_INIT_HW("eth1ck_k", &ck_ker_eth1.hw, &clk_stm32_gate_ops, 0), 1277 }; 1278 1279 static struct clk_stm32_div eth1ptp_k = { 1280 .div_id = DIV_ETH1PTP, 1281 .hw.init = CLK_HW_INIT_HW("eth1ptp_k", &ck_ker_eth1.hw, &clk_stm32_divider_ops, 1282 CLK_SET_RATE_NO_REPARENT), 1283 }; 1284 1285 static struct clk_stm32_mux ck_ker_eth2 = { 1286 .mux_id = MUX_ETH2, 1287 .hw.init = CLK_HW_INIT_PARENTS("ck_ker_eth2", eth12_src, &clk_stm32_mux_ops, 1288 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT), 1289 }; 1290 1291 static struct clk_stm32_gate eth2ck_k = { 1292 .gate_id = GATE_ETH2CK, 1293 .hw.init = CLK_HW_INIT_HW("eth2ck_k", &ck_ker_eth2.hw, &clk_stm32_gate_ops, 0), 1294 }; 1295 1296 static struct clk_stm32_div eth2ptp_k = { 1297 .div_id = DIV_ETH2PTP, 1298 .hw.init = CLK_HW_INIT_HW("eth2ptp_k", &ck_ker_eth2.hw, &clk_stm32_divider_ops, 1299 CLK_SET_RATE_NO_REPARENT), 1300 }; 1301 1302 static struct clk_stm32_composite ck_mco1 = { 1303 .gate_id = GATE_MCO1, 1304 .mux_id = MUX_MCO1, 1305 .div_id = DIV_MCO1, 1306 .hw.init = CLK_HW_INIT_PARENTS("ck_mco1", mco1_src, &clk_stm32_composite_ops, 1307 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT | 1308 CLK_IGNORE_UNUSED), 1309 }; 1310 1311 static struct clk_stm32_composite ck_mco2 = { 1312 .gate_id = GATE_MCO2, 1313 .mux_id = MUX_MCO2, 1314 .div_id = DIV_MCO2, 1315 .hw.init = CLK_HW_INIT_PARENTS("ck_mco2", mco2_src, &clk_stm32_composite_ops, 1316 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT | 1317 CLK_IGNORE_UNUSED), 1318 }; 1319 1320 /* Debug clocks */ 1321 static struct clk_stm32_gate ck_sys_dbg = { 1322 .gate_id = GATE_DBGCK, 1323 .hw.init = CLK_HW_INIT("ck_sys_dbg", "ck_axi", &clk_stm32_gate_ops, CLK_IS_CRITICAL), 1324 }; 1325 1326 static struct clk_stm32_composite ck_trace = { 1327 .gate_id = GATE_TRACECK, 1328 .mux_id = NO_STM32_MUX, 1329 .div_id = DIV_TRACE, 1330 .hw.init = CLK_HW_INIT("ck_trace", "ck_axi", &clk_stm32_composite_ops, CLK_IGNORE_UNUSED), 1331 }; 1332 1333 static const struct clock_config stm32mp13_clock_cfg[] = { 1334 /* Timer clocks */ 1335 STM32_GATE_CFG(TIM2_K, tim2_k, SECF_NONE), 1336 STM32_GATE_CFG(TIM3_K, tim3_k, SECF_NONE), 1337 STM32_GATE_CFG(TIM4_K, tim4_k, SECF_NONE), 1338 STM32_GATE_CFG(TIM5_K, tim5_k, SECF_NONE), 1339 STM32_GATE_CFG(TIM6_K, tim6_k, SECF_NONE), 1340 STM32_GATE_CFG(TIM7_K, tim7_k, SECF_NONE), 1341 STM32_GATE_CFG(TIM1_K, tim1_k, SECF_NONE), 1342 STM32_GATE_CFG(TIM8_K, tim8_k, SECF_NONE), 1343 STM32_GATE_CFG(TIM12_K, tim12_k, SECF_TIM12), 1344 STM32_GATE_CFG(TIM13_K, tim13_k, SECF_TIM13), 1345 STM32_GATE_CFG(TIM14_K, tim14_k, SECF_TIM14), 1346 STM32_GATE_CFG(TIM15_K, tim15_k, SECF_TIM15), 1347 STM32_GATE_CFG(TIM16_K, tim16_k, SECF_TIM16), 1348 STM32_GATE_CFG(TIM17_K, tim17_k, SECF_TIM17), 1349 1350 /* Peripheral clocks */ 1351 STM32_GATE_CFG(SAI1, sai1, SECF_NONE), 1352 STM32_GATE_CFG(SAI2, sai2, SECF_NONE), 1353 STM32_GATE_CFG(SYSCFG, syscfg, SECF_NONE), 1354 STM32_GATE_CFG(VREF, vref, SECF_VREF), 1355 STM32_GATE_CFG(DTS, dts, SECF_NONE), 1356 STM32_GATE_CFG(PMBCTRL, pmbctrl, SECF_NONE), 1357 STM32_GATE_CFG(HDP, hdp, SECF_NONE), 1358 STM32_GATE_CFG(IWDG2, iwdg2, SECF_NONE), 1359 STM32_GATE_CFG(STGENRO, stgenro, SECF_STGENRO), 1360 STM32_GATE_CFG(TZPC, tzpc, SECF_TZC), 1361 STM32_GATE_CFG(IWDG1, iwdg1, SECF_IWDG1), 1362 STM32_GATE_CFG(BSEC, bsec, SECF_BSEC), 1363 STM32_GATE_CFG(DMA1, dma1, SECF_NONE), 1364 STM32_GATE_CFG(DMA2, dma2, SECF_NONE), 1365 STM32_GATE_CFG(DMAMUX1, dmamux1, SECF_NONE), 1366 STM32_GATE_CFG(DMA3, dma3, SECF_DMA3), 1367 STM32_GATE_CFG(DMAMUX2, dmamux2, SECF_DMAMUX2), 1368 STM32_GATE_CFG(ADC1, adc1, SECF_ADC1), 1369 STM32_GATE_CFG(ADC2, adc2, SECF_ADC2), 1370 STM32_GATE_CFG(GPIOA, gpioa, SECF_NONE), 1371 STM32_GATE_CFG(GPIOB, gpiob, SECF_NONE), 1372 STM32_GATE_CFG(GPIOC, gpioc, SECF_NONE), 1373 STM32_GATE_CFG(GPIOD, gpiod, SECF_NONE), 1374 STM32_GATE_CFG(GPIOE, gpioe, SECF_NONE), 1375 STM32_GATE_CFG(GPIOF, gpiof, SECF_NONE), 1376 STM32_GATE_CFG(GPIOG, gpiog, SECF_NONE), 1377 STM32_GATE_CFG(GPIOH, gpioh, SECF_NONE), 1378 STM32_GATE_CFG(GPIOI, gpioi, SECF_NONE), 1379 STM32_GATE_CFG(TSC, tsc, SECF_TZC), 1380 STM32_GATE_CFG(PKA, pka, SECF_PKA), 1381 STM32_GATE_CFG(CRYP1, cryp1, SECF_CRYP1), 1382 STM32_GATE_CFG(HASH1, hash1, SECF_HASH1), 1383 STM32_GATE_CFG(BKPSRAM, bkpsram, SECF_BKPSRAM), 1384 STM32_GATE_CFG(MDMA, mdma, SECF_NONE), 1385 STM32_GATE_CFG(ETH1TX, eth1tx, SECF_ETH1TX), 1386 STM32_GATE_CFG(ETH1RX, eth1rx, SECF_ETH1RX), 1387 STM32_GATE_CFG(ETH1MAC, eth1mac, SECF_ETH1MAC), 1388 STM32_GATE_CFG(ETH2TX, eth2tx, SECF_ETH2TX), 1389 STM32_GATE_CFG(ETH2RX, eth2rx, SECF_ETH2RX), 1390 STM32_GATE_CFG(ETH2MAC, eth2mac, SECF_ETH2MAC), 1391 STM32_GATE_CFG(CRC1, crc1, SECF_NONE), 1392 STM32_GATE_CFG(USBH, usbh, SECF_NONE), 1393 STM32_GATE_CFG(DDRPERFM, ddrperfm, SECF_NONE), 1394 STM32_GATE_CFG(ETH1STP, eth1stp, SECF_ETH1STP), 1395 STM32_GATE_CFG(ETH2STP, eth2stp, SECF_ETH2STP), 1396 1397 /* Kernel clocks */ 1398 STM32_COMPOSITE_CFG(SDMMC1_K, sdmmc1_k, SECF_SDMMC1), 1399 STM32_COMPOSITE_CFG(SDMMC2_K, sdmmc2_k, SECF_SDMMC2), 1400 STM32_COMPOSITE_CFG(FMC_K, fmc_k, SECF_FMC), 1401 STM32_COMPOSITE_CFG(QSPI_K, qspi_k, SECF_QSPI), 1402 STM32_COMPOSITE_CFG(SPI2_K, spi2_k, SECF_NONE), 1403 STM32_COMPOSITE_CFG(SPI3_K, spi3_k, SECF_NONE), 1404 STM32_COMPOSITE_CFG(I2C1_K, i2c1_k, SECF_NONE), 1405 STM32_COMPOSITE_CFG(I2C2_K, i2c2_k, SECF_NONE), 1406 STM32_COMPOSITE_CFG(LPTIM4_K, lptim4_k, SECF_NONE), 1407 STM32_COMPOSITE_CFG(LPTIM5_K, lptim5_k, SECF_NONE), 1408 STM32_COMPOSITE_CFG(USART3_K, usart3_k, SECF_NONE), 1409 STM32_COMPOSITE_CFG(UART5_K, uart5_k, SECF_NONE), 1410 STM32_COMPOSITE_CFG(UART7_K, uart7_k, SECF_NONE), 1411 STM32_COMPOSITE_CFG(UART8_K, uart8_k, SECF_NONE), 1412 STM32_COMPOSITE_CFG(SAI1_K, sai1_k, SECF_NONE), 1413 STM32_COMPOSITE_CFG(SAI2_K, sai2_k, SECF_NONE), 1414 STM32_COMPOSITE_CFG(ADFSDM_K, adfsdm_k, SECF_NONE), 1415 STM32_COMPOSITE_CFG(ADC1_K, adc1_k, SECF_ADC1), 1416 STM32_COMPOSITE_CFG(ADC2_K, adc2_k, SECF_ADC2), 1417 STM32_COMPOSITE_CFG(RNG1_K, rng1_k, SECF_RNG1), 1418 STM32_COMPOSITE_CFG(USBPHY_K, usbphy_k, SECF_USBPHY), 1419 STM32_COMPOSITE_CFG(STGEN_K, stgen_k, SECF_STGENC), 1420 STM32_COMPOSITE_CFG(SPDIF_K, spdif_k, SECF_NONE), 1421 STM32_COMPOSITE_CFG(SPI1_K, spi1_k, SECF_NONE), 1422 STM32_COMPOSITE_CFG(SPI4_K, spi4_k, SECF_SPI4), 1423 STM32_COMPOSITE_CFG(SPI5_K, spi5_k, SECF_SPI5), 1424 STM32_COMPOSITE_CFG(I2C3_K, i2c3_k, SECF_I2C3), 1425 STM32_COMPOSITE_CFG(I2C4_K, i2c4_k, SECF_I2C4), 1426 STM32_COMPOSITE_CFG(I2C5_K, i2c5_k, SECF_I2C5), 1427 STM32_COMPOSITE_CFG(LPTIM1_K, lptim1_k, SECF_NONE), 1428 STM32_COMPOSITE_CFG(LPTIM2_K, lptim2_k, SECF_LPTIM2), 1429 STM32_COMPOSITE_CFG(LPTIM3_K, lptim3_k, SECF_LPTIM3), 1430 STM32_COMPOSITE_CFG(USART1_K, usart1_k, SECF_USART1), 1431 STM32_COMPOSITE_CFG(USART2_K, usart2_k, SECF_USART2), 1432 STM32_COMPOSITE_CFG(UART4_K, uart4_k, SECF_NONE), 1433 STM32_COMPOSITE_CFG(USART6_K, uart6_k, SECF_NONE), 1434 STM32_COMPOSITE_CFG(FDCAN_K, fdcan_k, SECF_NONE), 1435 STM32_COMPOSITE_CFG(DCMIPP_K, dcmipp_k, SECF_DCMIPP), 1436 STM32_COMPOSITE_CFG(USBO_K, usbo_k, SECF_USBO), 1437 STM32_COMPOSITE_CFG(SAES_K, saes_k, SECF_SAES), 1438 STM32_GATE_CFG(DFSDM_K, dfsdm_k, SECF_NONE), 1439 STM32_GATE_CFG(LTDC_PX, ltdc_px, SECF_NONE), 1440 1441 STM32_MUX_CFG(NO_ID, ck_ker_eth1, SECF_ETH1CK), 1442 STM32_GATE_CFG(ETH1CK_K, eth1ck_k, SECF_ETH1CK), 1443 STM32_DIV_CFG(ETH1PTP_K, eth1ptp_k, SECF_ETH1CK), 1444 1445 STM32_MUX_CFG(NO_ID, ck_ker_eth2, SECF_ETH2CK), 1446 STM32_GATE_CFG(ETH2CK_K, eth2ck_k, SECF_ETH2CK), 1447 STM32_DIV_CFG(ETH2PTP_K, eth2ptp_k, SECF_ETH2CK), 1448 1449 STM32_GATE_CFG(CK_DBG, ck_sys_dbg, SECF_NONE), 1450 STM32_COMPOSITE_CFG(CK_TRACE, ck_trace, SECF_NONE), 1451 1452 STM32_COMPOSITE_CFG(CK_MCO1, ck_mco1, SECF_MCO1), 1453 STM32_COMPOSITE_CFG(CK_MCO2, ck_mco2, SECF_MCO2), 1454 }; 1455 1456 static int stm32mp13_clock_is_provided_by_secure(void __iomem *base, 1457 const struct clock_config *cfg) 1458 { 1459 int sec_id = cfg->sec_id; 1460 1461 if (sec_id != SECF_NONE) { 1462 const struct clk_stm32_securiy *secf; 1463 1464 secf = &stm32mp13_security[sec_id]; 1465 1466 return !!(readl(base + secf->offset) & BIT(secf->bit_idx)); 1467 } 1468 1469 return 0; 1470 } 1471 1472 static u16 stm32mp13_cpt_gate[GATE_NB]; 1473 1474 static struct clk_stm32_clock_data stm32mp13_clock_data = { 1475 .gate_cpt = stm32mp13_cpt_gate, 1476 .gates = stm32mp13_gates, 1477 .muxes = stm32mp13_muxes, 1478 .dividers = stm32mp13_dividers, 1479 }; 1480 1481 static const struct stm32_rcc_match_data stm32mp13_data = { 1482 .tab_clocks = stm32mp13_clock_cfg, 1483 .num_clocks = ARRAY_SIZE(stm32mp13_clock_cfg), 1484 .clock_data = &stm32mp13_clock_data, 1485 .check_security = &stm32mp13_clock_is_provided_by_secure, 1486 .maxbinding = STM32MP1_LAST_CLK, 1487 .clear_offset = RCC_CLR_OFFSET, 1488 }; 1489 1490 static const struct of_device_id stm32mp13_match_data[] = { 1491 { 1492 .compatible = "st,stm32mp13-rcc", 1493 .data = &stm32mp13_data, 1494 }, 1495 { } 1496 }; 1497 MODULE_DEVICE_TABLE(of, stm32mp13_match_data); 1498 1499 static int stm32mp1_rcc_init(struct device *dev) 1500 { 1501 void __iomem *rcc_base; 1502 int ret = -ENOMEM; 1503 1504 rcc_base = of_iomap(dev_of_node(dev), 0); 1505 if (!rcc_base) { 1506 dev_err(dev, "%pOFn: unable to map resource", dev_of_node(dev)); 1507 goto out; 1508 } 1509 1510 ret = stm32_rcc_init(dev, stm32mp13_match_data, rcc_base); 1511 out: 1512 if (ret) { 1513 if (rcc_base) 1514 iounmap(rcc_base); 1515 1516 of_node_put(dev_of_node(dev)); 1517 } 1518 1519 return ret; 1520 } 1521 1522 static int get_clock_deps(struct device *dev) 1523 { 1524 static const char * const clock_deps_name[] = { 1525 "hsi", "hse", "csi", "lsi", "lse", 1526 }; 1527 size_t deps_size = sizeof(struct clk *) * ARRAY_SIZE(clock_deps_name); 1528 struct clk **clk_deps; 1529 int i; 1530 1531 clk_deps = devm_kzalloc(dev, deps_size, GFP_KERNEL); 1532 if (!clk_deps) 1533 return -ENOMEM; 1534 1535 for (i = 0; i < ARRAY_SIZE(clock_deps_name); i++) { 1536 struct clk *clk = of_clk_get_by_name(dev_of_node(dev), 1537 clock_deps_name[i]); 1538 1539 if (IS_ERR(clk)) { 1540 if (PTR_ERR(clk) != -EINVAL && PTR_ERR(clk) != -ENOENT) 1541 return PTR_ERR(clk); 1542 } else { 1543 /* Device gets a reference count on the clock */ 1544 clk_deps[i] = devm_clk_get(dev, __clk_get_name(clk)); 1545 clk_put(clk); 1546 } 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int stm32mp1_rcc_clocks_probe(struct platform_device *pdev) 1553 { 1554 struct device *dev = &pdev->dev; 1555 int ret = get_clock_deps(dev); 1556 1557 if (!ret) 1558 ret = stm32mp1_rcc_init(dev); 1559 1560 return ret; 1561 } 1562 1563 static int stm32mp1_rcc_clocks_remove(struct platform_device *pdev) 1564 { 1565 struct device *dev = &pdev->dev; 1566 struct device_node *child, *np = dev_of_node(dev); 1567 1568 for_each_available_child_of_node(np, child) 1569 of_clk_del_provider(child); 1570 1571 return 0; 1572 } 1573 1574 static struct platform_driver stm32mp13_rcc_clocks_driver = { 1575 .driver = { 1576 .name = "stm32mp13_rcc", 1577 .of_match_table = stm32mp13_match_data, 1578 }, 1579 .probe = stm32mp1_rcc_clocks_probe, 1580 .remove = stm32mp1_rcc_clocks_remove, 1581 }; 1582 1583 static int __init stm32mp13_clocks_init(void) 1584 { 1585 return platform_driver_register(&stm32mp13_rcc_clocks_driver); 1586 } 1587 core_initcall(stm32mp13_clocks_init); 1588