1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4  * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/io.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 
17 #include "clk-stm32-core.h"
18 #include "reset-stm32.h"
19 
20 static DEFINE_SPINLOCK(rlock);
21 
22 static int stm32_rcc_clock_init(struct device *dev,
23 				const struct of_device_id *match,
24 				void __iomem *base)
25 {
26 	const struct stm32_rcc_match_data *data = match->data;
27 	struct clk_hw_onecell_data *clk_data = data->hw_clks;
28 	struct device_node *np = dev_of_node(dev);
29 	struct clk_hw **hws;
30 	int n, max_binding;
31 
32 	max_binding =  data->maxbinding;
33 
34 	clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, max_binding), GFP_KERNEL);
35 	if (!clk_data)
36 		return -ENOMEM;
37 
38 	clk_data->num = max_binding;
39 
40 	hws = clk_data->hws;
41 
42 	for (n = 0; n < max_binding; n++)
43 		hws[n] = ERR_PTR(-ENOENT);
44 
45 	for (n = 0; n < data->num_clocks; n++) {
46 		const struct clock_config *cfg_clock = &data->tab_clocks[n];
47 		struct clk_hw *hw = ERR_PTR(-ENOENT);
48 
49 		if (data->check_security &&
50 		    data->check_security(base, cfg_clock))
51 			continue;
52 
53 		if (cfg_clock->func)
54 			hw = (*cfg_clock->func)(dev, data, base, &rlock,
55 						cfg_clock);
56 
57 		if (IS_ERR(hw)) {
58 			dev_err(dev, "Can't register clk %d: %ld\n", n,
59 				PTR_ERR(hw));
60 			return PTR_ERR(hw);
61 		}
62 
63 		if (cfg_clock->id != NO_ID)
64 			hws[cfg_clock->id] = hw;
65 	}
66 
67 	return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
68 }
69 
70 int stm32_rcc_init(struct device *dev, const struct of_device_id *match_data,
71 		   void __iomem *base)
72 {
73 	const struct of_device_id *match;
74 	int err;
75 
76 	match = of_match_node(match_data, dev_of_node(dev));
77 	if (!match) {
78 		dev_err(dev, "match data not found\n");
79 		return -ENODEV;
80 	}
81 
82 	/* RCC Reset Configuration */
83 	err = stm32_rcc_reset_init(dev, match, base);
84 	if (err) {
85 		pr_err("stm32 reset failed to initialize\n");
86 		return err;
87 	}
88 
89 	/* RCC Clock Configuration */
90 	err = stm32_rcc_clock_init(dev, match, base);
91 	if (err) {
92 		pr_err("stm32 clock failed to initialize\n");
93 		return err;
94 	}
95 
96 	return 0;
97 }
98 
99 static u8 stm32_mux_get_parent(void __iomem *base,
100 			       struct clk_stm32_clock_data *data,
101 			       u16 mux_id)
102 {
103 	const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
104 	u32 mask = BIT(mux->width) - 1;
105 	u32 val;
106 
107 	val = readl(base + mux->offset) >> mux->shift;
108 	val &= mask;
109 
110 	return val;
111 }
112 
113 static int stm32_mux_set_parent(void __iomem *base,
114 				struct clk_stm32_clock_data *data,
115 				u16 mux_id, u8 index)
116 {
117 	const struct stm32_mux_cfg *mux = &data->muxes[mux_id];
118 
119 	u32 mask = BIT(mux->width) - 1;
120 	u32 reg = readl(base + mux->offset);
121 	u32 val = index << mux->shift;
122 
123 	reg &= ~(mask << mux->shift);
124 	reg |= val;
125 
126 	writel(reg, base + mux->offset);
127 
128 	return 0;
129 }
130 
131 static void stm32_gate_endisable(void __iomem *base,
132 				 struct clk_stm32_clock_data *data,
133 				 u16 gate_id, int enable)
134 {
135 	const struct stm32_gate_cfg *gate = &data->gates[gate_id];
136 	void __iomem *addr = base + gate->offset;
137 
138 	if (enable) {
139 		if (data->gate_cpt[gate_id]++ > 0)
140 			return;
141 
142 		if (gate->set_clr != 0)
143 			writel(BIT(gate->bit_idx), addr);
144 		else
145 			writel(readl(addr) | BIT(gate->bit_idx), addr);
146 	} else {
147 		if (--data->gate_cpt[gate_id] > 0)
148 			return;
149 
150 		if (gate->set_clr != 0)
151 			writel(BIT(gate->bit_idx), addr + gate->set_clr);
152 		else
153 			writel(readl(addr) & ~BIT(gate->bit_idx), addr);
154 	}
155 }
156 
157 static void stm32_gate_disable_unused(void __iomem *base,
158 				      struct clk_stm32_clock_data *data,
159 				      u16 gate_id)
160 {
161 	const struct stm32_gate_cfg *gate = &data->gates[gate_id];
162 	void __iomem *addr = base + gate->offset;
163 
164 	if (data->gate_cpt[gate_id] > 0)
165 		return;
166 
167 	if (gate->set_clr != 0)
168 		writel(BIT(gate->bit_idx), addr + gate->set_clr);
169 	else
170 		writel(readl(addr) & ~BIT(gate->bit_idx), addr);
171 }
172 
173 static int stm32_gate_is_enabled(void __iomem *base,
174 				 struct clk_stm32_clock_data *data,
175 				 u16 gate_id)
176 {
177 	const struct stm32_gate_cfg *gate = &data->gates[gate_id];
178 
179 	return (readl(base + gate->offset) & BIT(gate->bit_idx)) != 0;
180 }
181 
182 static unsigned int _get_table_div(const struct clk_div_table *table,
183 				   unsigned int val)
184 {
185 	const struct clk_div_table *clkt;
186 
187 	for (clkt = table; clkt->div; clkt++)
188 		if (clkt->val == val)
189 			return clkt->div;
190 	return 0;
191 }
192 
193 static unsigned int _get_div(const struct clk_div_table *table,
194 			     unsigned int val, unsigned long flags, u8 width)
195 {
196 	if (flags & CLK_DIVIDER_ONE_BASED)
197 		return val;
198 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
199 		return 1 << val;
200 	if (table)
201 		return _get_table_div(table, val);
202 	return val + 1;
203 }
204 
205 static unsigned long stm32_divider_get_rate(void __iomem *base,
206 					    struct clk_stm32_clock_data *data,
207 					    u16 div_id,
208 					    unsigned long parent_rate)
209 {
210 	const struct stm32_div_cfg *divider = &data->dividers[div_id];
211 	unsigned int val;
212 	unsigned int div;
213 
214 	val =  readl(base + divider->offset) >> divider->shift;
215 	val &= clk_div_mask(divider->width);
216 	div = _get_div(divider->table, val, divider->flags, divider->width);
217 
218 	if (!div) {
219 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
220 		     "%d: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
221 		     div_id);
222 		return parent_rate;
223 	}
224 
225 	return DIV_ROUND_UP_ULL((u64)parent_rate, div);
226 }
227 
228 static int stm32_divider_set_rate(void __iomem *base,
229 				  struct clk_stm32_clock_data *data,
230 				  u16 div_id, unsigned long rate,
231 				  unsigned long parent_rate)
232 {
233 	const struct stm32_div_cfg *divider = &data->dividers[div_id];
234 	int value;
235 	u32 val;
236 
237 	value = divider_get_val(rate, parent_rate, divider->table,
238 				divider->width, divider->flags);
239 	if (value < 0)
240 		return value;
241 
242 	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
243 		val = clk_div_mask(divider->width) << (divider->shift + 16);
244 	} else {
245 		val = readl(base + divider->offset);
246 		val &= ~(clk_div_mask(divider->width) << divider->shift);
247 	}
248 
249 	val |= (u32)value << divider->shift;
250 
251 	writel(val, base + divider->offset);
252 
253 	return 0;
254 }
255 
256 static u8 clk_stm32_mux_get_parent(struct clk_hw *hw)
257 {
258 	struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
259 
260 	return stm32_mux_get_parent(mux->base, mux->clock_data, mux->mux_id);
261 }
262 
263 static int clk_stm32_mux_set_parent(struct clk_hw *hw, u8 index)
264 {
265 	struct clk_stm32_mux *mux = to_clk_stm32_mux(hw);
266 	unsigned long flags = 0;
267 
268 	spin_lock_irqsave(mux->lock, flags);
269 
270 	stm32_mux_set_parent(mux->base, mux->clock_data, mux->mux_id, index);
271 
272 	spin_unlock_irqrestore(mux->lock, flags);
273 
274 	return 0;
275 }
276 
277 const struct clk_ops clk_stm32_mux_ops = {
278 	.determine_rate	= __clk_mux_determine_rate,
279 	.get_parent	= clk_stm32_mux_get_parent,
280 	.set_parent	= clk_stm32_mux_set_parent,
281 };
282 
283 static void clk_stm32_gate_endisable(struct clk_hw *hw, int enable)
284 {
285 	struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
286 	unsigned long flags = 0;
287 
288 	spin_lock_irqsave(gate->lock, flags);
289 
290 	stm32_gate_endisable(gate->base, gate->clock_data, gate->gate_id, enable);
291 
292 	spin_unlock_irqrestore(gate->lock, flags);
293 }
294 
295 static int clk_stm32_gate_enable(struct clk_hw *hw)
296 {
297 	clk_stm32_gate_endisable(hw, 1);
298 
299 	return 0;
300 }
301 
302 static void clk_stm32_gate_disable(struct clk_hw *hw)
303 {
304 	clk_stm32_gate_endisable(hw, 0);
305 }
306 
307 static int clk_stm32_gate_is_enabled(struct clk_hw *hw)
308 {
309 	struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
310 
311 	return stm32_gate_is_enabled(gate->base, gate->clock_data, gate->gate_id);
312 }
313 
314 static void clk_stm32_gate_disable_unused(struct clk_hw *hw)
315 {
316 	struct clk_stm32_gate *gate = to_clk_stm32_gate(hw);
317 	unsigned long flags = 0;
318 
319 	spin_lock_irqsave(gate->lock, flags);
320 
321 	stm32_gate_disable_unused(gate->base, gate->clock_data, gate->gate_id);
322 
323 	spin_unlock_irqrestore(gate->lock, flags);
324 }
325 
326 const struct clk_ops clk_stm32_gate_ops = {
327 	.enable		= clk_stm32_gate_enable,
328 	.disable	= clk_stm32_gate_disable,
329 	.is_enabled	= clk_stm32_gate_is_enabled,
330 	.disable_unused	= clk_stm32_gate_disable_unused,
331 };
332 
333 static int clk_stm32_divider_set_rate(struct clk_hw *hw, unsigned long rate,
334 				      unsigned long parent_rate)
335 {
336 	struct clk_stm32_div *div = to_clk_stm32_divider(hw);
337 	unsigned long flags = 0;
338 	int ret;
339 
340 	if (div->div_id == NO_STM32_DIV)
341 		return rate;
342 
343 	spin_lock_irqsave(div->lock, flags);
344 
345 	ret = stm32_divider_set_rate(div->base, div->clock_data, div->div_id, rate, parent_rate);
346 
347 	spin_unlock_irqrestore(div->lock, flags);
348 
349 	return ret;
350 }
351 
352 static long clk_stm32_divider_round_rate(struct clk_hw *hw, unsigned long rate,
353 					 unsigned long *prate)
354 {
355 	struct clk_stm32_div *div = to_clk_stm32_divider(hw);
356 	const struct stm32_div_cfg *divider;
357 
358 	if (div->div_id == NO_STM32_DIV)
359 		return rate;
360 
361 	divider = &div->clock_data->dividers[div->div_id];
362 
363 	/* if read only, just return current value */
364 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
365 		u32 val;
366 
367 		val =  readl(div->base + divider->offset) >> divider->shift;
368 		val &= clk_div_mask(divider->width);
369 
370 		return divider_ro_round_rate(hw, rate, prate, divider->table,
371 				divider->width, divider->flags,
372 				val);
373 	}
374 
375 	return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
376 					 rate, prate, divider->table,
377 					 divider->width, divider->flags);
378 }
379 
380 static unsigned long clk_stm32_divider_recalc_rate(struct clk_hw *hw,
381 						   unsigned long parent_rate)
382 {
383 	struct clk_stm32_div *div = to_clk_stm32_divider(hw);
384 
385 	if (div->div_id == NO_STM32_DIV)
386 		return parent_rate;
387 
388 	return stm32_divider_get_rate(div->base, div->clock_data, div->div_id, parent_rate);
389 }
390 
391 const struct clk_ops clk_stm32_divider_ops = {
392 	.recalc_rate	= clk_stm32_divider_recalc_rate,
393 	.round_rate	= clk_stm32_divider_round_rate,
394 	.set_rate	= clk_stm32_divider_set_rate,
395 };
396 
397 static int clk_stm32_composite_set_rate(struct clk_hw *hw, unsigned long rate,
398 					unsigned long parent_rate)
399 {
400 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
401 	unsigned long flags = 0;
402 	int ret;
403 
404 	if (composite->div_id == NO_STM32_DIV)
405 		return rate;
406 
407 	spin_lock_irqsave(composite->lock, flags);
408 
409 	ret = stm32_divider_set_rate(composite->base, composite->clock_data,
410 				     composite->div_id, rate, parent_rate);
411 
412 	spin_unlock_irqrestore(composite->lock, flags);
413 
414 	return ret;
415 }
416 
417 static unsigned long clk_stm32_composite_recalc_rate(struct clk_hw *hw,
418 						     unsigned long parent_rate)
419 {
420 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
421 
422 	if (composite->div_id == NO_STM32_DIV)
423 		return parent_rate;
424 
425 	return stm32_divider_get_rate(composite->base, composite->clock_data,
426 				      composite->div_id, parent_rate);
427 }
428 
429 static int clk_stm32_composite_determine_rate(struct clk_hw *hw,
430 					      struct clk_rate_request *req)
431 {
432 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
433 	const struct stm32_div_cfg *divider;
434 	unsigned long rate;
435 
436 	if (composite->div_id == NO_STM32_DIV)
437 		return 0;
438 
439 	divider = &composite->clock_data->dividers[composite->div_id];
440 
441 	/* if read only, just return current value */
442 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {
443 		u32 val;
444 
445 		val =  readl(composite->base + divider->offset) >> divider->shift;
446 		val &= clk_div_mask(divider->width);
447 
448 		rate = divider_ro_round_rate(hw, req->rate, &req->best_parent_rate,
449 					     divider->table, divider->width, divider->flags,
450 					     val);
451 		if (rate < 0)
452 			return rate;
453 
454 		req->rate = rate;
455 		return 0;
456 	}
457 
458 	rate = divider_round_rate_parent(hw, clk_hw_get_parent(hw),
459 					 req->rate, &req->best_parent_rate,
460 					 divider->table, divider->width, divider->flags);
461 	if (rate < 0)
462 		return rate;
463 
464 	req->rate = rate;
465 	return 0;
466 }
467 
468 static u8 clk_stm32_composite_get_parent(struct clk_hw *hw)
469 {
470 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
471 
472 	return stm32_mux_get_parent(composite->base, composite->clock_data, composite->mux_id);
473 }
474 
475 static int clk_stm32_composite_set_parent(struct clk_hw *hw, u8 index)
476 {
477 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
478 	unsigned long flags = 0;
479 
480 	spin_lock_irqsave(composite->lock, flags);
481 
482 	stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, index);
483 
484 	spin_unlock_irqrestore(composite->lock, flags);
485 
486 	if (composite->clock_data->is_multi_mux) {
487 		struct clk_hw *other_mux_hw = composite->clock_data->is_multi_mux(hw);
488 
489 		if (other_mux_hw) {
490 			struct clk_hw *hwp = clk_hw_get_parent_by_index(hw, index);
491 
492 			clk_hw_reparent(other_mux_hw, hwp);
493 		}
494 	}
495 
496 	return 0;
497 }
498 
499 static int clk_stm32_composite_is_enabled(struct clk_hw *hw)
500 {
501 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
502 
503 	if (composite->gate_id == NO_STM32_GATE)
504 		return (__clk_get_enable_count(hw->clk) > 0);
505 
506 	return stm32_gate_is_enabled(composite->base, composite->clock_data, composite->gate_id);
507 }
508 
509 #define MUX_SAFE_POSITION 0
510 
511 static int clk_stm32_has_safe_mux(struct clk_hw *hw)
512 {
513 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
514 	const struct stm32_mux_cfg *mux = &composite->clock_data->muxes[composite->mux_id];
515 
516 	return !!(mux->flags & MUX_SAFE);
517 }
518 
519 static void clk_stm32_set_safe_position_mux(struct clk_hw *hw)
520 {
521 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
522 
523 	if (!clk_stm32_composite_is_enabled(hw)) {
524 		unsigned long flags = 0;
525 
526 		if (composite->clock_data->is_multi_mux) {
527 			struct clk_hw *other_mux_hw = NULL;
528 
529 			other_mux_hw = composite->clock_data->is_multi_mux(hw);
530 
531 			if (!other_mux_hw || clk_stm32_composite_is_enabled(other_mux_hw))
532 				return;
533 		}
534 
535 		spin_lock_irqsave(composite->lock, flags);
536 
537 		stm32_mux_set_parent(composite->base, composite->clock_data,
538 				     composite->mux_id, MUX_SAFE_POSITION);
539 
540 		spin_unlock_irqrestore(composite->lock, flags);
541 	}
542 }
543 
544 static void clk_stm32_safe_restore_position_mux(struct clk_hw *hw)
545 {
546 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
547 	int sel = clk_hw_get_parent_index(hw);
548 	unsigned long flags = 0;
549 
550 	spin_lock_irqsave(composite->lock, flags);
551 
552 	stm32_mux_set_parent(composite->base, composite->clock_data, composite->mux_id, sel);
553 
554 	spin_unlock_irqrestore(composite->lock, flags);
555 }
556 
557 static void clk_stm32_composite_gate_endisable(struct clk_hw *hw, int enable)
558 {
559 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
560 	unsigned long flags = 0;
561 
562 	spin_lock_irqsave(composite->lock, flags);
563 
564 	stm32_gate_endisable(composite->base, composite->clock_data, composite->gate_id, enable);
565 
566 	spin_unlock_irqrestore(composite->lock, flags);
567 }
568 
569 static int clk_stm32_composite_gate_enable(struct clk_hw *hw)
570 {
571 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
572 
573 	if (composite->gate_id == NO_STM32_GATE)
574 		return 0;
575 
576 	clk_stm32_composite_gate_endisable(hw, 1);
577 
578 	if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
579 		clk_stm32_safe_restore_position_mux(hw);
580 
581 	return 0;
582 }
583 
584 static void clk_stm32_composite_gate_disable(struct clk_hw *hw)
585 {
586 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
587 
588 	if (composite->gate_id == NO_STM32_GATE)
589 		return;
590 
591 	clk_stm32_composite_gate_endisable(hw, 0);
592 
593 	if (composite->mux_id != NO_STM32_MUX && clk_stm32_has_safe_mux(hw))
594 		clk_stm32_set_safe_position_mux(hw);
595 }
596 
597 static void clk_stm32_composite_disable_unused(struct clk_hw *hw)
598 {
599 	struct clk_stm32_composite *composite = to_clk_stm32_composite(hw);
600 	unsigned long flags = 0;
601 
602 	if (composite->gate_id == NO_STM32_GATE)
603 		return;
604 
605 	spin_lock_irqsave(composite->lock, flags);
606 
607 	stm32_gate_disable_unused(composite->base, composite->clock_data, composite->gate_id);
608 
609 	spin_unlock_irqrestore(composite->lock, flags);
610 }
611 
612 const struct clk_ops clk_stm32_composite_ops = {
613 	.set_rate	= clk_stm32_composite_set_rate,
614 	.recalc_rate	= clk_stm32_composite_recalc_rate,
615 	.determine_rate	= clk_stm32_composite_determine_rate,
616 	.get_parent	= clk_stm32_composite_get_parent,
617 	.set_parent	= clk_stm32_composite_set_parent,
618 	.enable		= clk_stm32_composite_gate_enable,
619 	.disable	= clk_stm32_composite_gate_disable,
620 	.is_enabled	= clk_stm32_composite_is_enabled,
621 	.disable_unused	= clk_stm32_composite_disable_unused,
622 };
623 
624 struct clk_hw *clk_stm32_mux_register(struct device *dev,
625 				      const struct stm32_rcc_match_data *data,
626 				      void __iomem *base,
627 				      spinlock_t *lock,
628 				      const struct clock_config *cfg)
629 {
630 	struct clk_stm32_mux *mux = cfg->clock_cfg;
631 	struct clk_hw *hw = &mux->hw;
632 	int err;
633 
634 	mux->base = base;
635 	mux->lock = lock;
636 	mux->clock_data = data->clock_data;
637 
638 	err = clk_hw_register(dev, hw);
639 	if (err)
640 		return ERR_PTR(err);
641 
642 	return hw;
643 }
644 
645 struct clk_hw *clk_stm32_gate_register(struct device *dev,
646 				       const struct stm32_rcc_match_data *data,
647 				       void __iomem *base,
648 				       spinlock_t *lock,
649 				       const struct clock_config *cfg)
650 {
651 	struct clk_stm32_gate *gate = cfg->clock_cfg;
652 	struct clk_hw *hw = &gate->hw;
653 	int err;
654 
655 	gate->base = base;
656 	gate->lock = lock;
657 	gate->clock_data = data->clock_data;
658 
659 	err = clk_hw_register(dev, hw);
660 	if (err)
661 		return ERR_PTR(err);
662 
663 	return hw;
664 }
665 
666 struct clk_hw *clk_stm32_div_register(struct device *dev,
667 				      const struct stm32_rcc_match_data *data,
668 				      void __iomem *base,
669 				      spinlock_t *lock,
670 				      const struct clock_config *cfg)
671 {
672 	struct clk_stm32_div *div = cfg->clock_cfg;
673 	struct clk_hw *hw = &div->hw;
674 	int err;
675 
676 	div->base = base;
677 	div->lock = lock;
678 	div->clock_data = data->clock_data;
679 
680 	err = clk_hw_register(dev, hw);
681 	if (err)
682 		return ERR_PTR(err);
683 
684 	return hw;
685 }
686 
687 struct clk_hw *clk_stm32_composite_register(struct device *dev,
688 					    const struct stm32_rcc_match_data *data,
689 					    void __iomem *base,
690 					    spinlock_t *lock,
691 					    const struct clock_config *cfg)
692 {
693 	struct clk_stm32_composite *composite = cfg->clock_cfg;
694 	struct clk_hw *hw = &composite->hw;
695 	int err;
696 
697 	composite->base = base;
698 	composite->lock = lock;
699 	composite->clock_data = data->clock_data;
700 
701 	err = clk_hw_register(dev, hw);
702 	if (err)
703 		return ERR_PTR(err);
704 
705 	return hw;
706 }
707