1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * StarFive JH7110 System Clock Driver 4 * 5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk> 6 * Copyright (C) 2022 StarFive Technology Co., Ltd. 7 */ 8 9 #include <linux/auxiliary_bus.h> 10 #include <linux/clk-provider.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #include <soc/starfive/reset-starfive-jh71x0.h> 17 18 #include <dt-bindings/clock/starfive,jh7110-crg.h> 19 20 #include "clk-starfive-jh7110.h" 21 22 /* external clocks */ 23 #define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0) 24 #define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1) 25 #define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2) 26 #define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3) 27 #define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4) 28 #define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5) 29 #define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6) 30 #define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7) 31 #define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8) 32 #define JH7110_SYSCLK_PLL0_OUT (JH7110_SYSCLK_END + 9) 33 #define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10) 34 #define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11) 35 36 static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { 37 /* root */ 38 JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2, 39 JH7110_SYSCLK_OSC, 40 JH7110_SYSCLK_PLL0_OUT), 41 JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT), 42 JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE), 43 JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2, 44 JH7110_SYSCLK_PLL2_OUT, 45 JH7110_SYSCLK_PLL1_OUT), 46 JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2, 47 JH7110_SYSCLK_PLL0_OUT, 48 JH7110_SYSCLK_PLL2_OUT), 49 JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2, 50 JH7110_SYSCLK_OSC, 51 JH7110_SYSCLK_PLL2_OUT), 52 JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT), 53 JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT), 54 JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0), 55 JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), 56 JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), 57 JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB), 58 JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS), 59 JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT), 60 JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT), 61 JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT), 62 JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT), 63 JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT), 64 JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2, 65 JH7110_SYSCLK_MCLK_INNER, 66 JH7110_SYSCLK_MCLK_EXT), 67 JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER), 68 JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2, 69 JH7110_SYSCLK_PLL2_OUT, 70 JH7110_SYSCLK_PLL1_OUT), 71 JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X), 72 JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2), 73 JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2), 74 JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2), 75 /* cores */ 76 JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), 77 JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), 78 JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), 79 JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), 80 JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), 81 JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS), 82 JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC), 83 JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE), 84 JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE), 85 JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE), 86 JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE), 87 JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE), 88 JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS), 89 /* noc */ 90 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL, 91 JH7110_SYSCLK_CPU_BUS), 92 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL, 93 JH7110_SYSCLK_AXI_CFG0), 94 /* ddr */ 95 JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC), 96 JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2), 97 JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4), 98 JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4, 99 JH7110_SYSCLK_OSC_DIV2, 100 JH7110_SYSCLK_PLL1_DIV2, 101 JH7110_SYSCLK_PLL1_DIV4, 102 JH7110_SYSCLK_PLL1_DIV8), 103 JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS), 104 /* gpu */ 105 JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT), 106 JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE), 107 JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI), 108 JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS), 109 JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC), 110 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE), 111 /* isp */ 112 JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X), 113 JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI), 114 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL, 115 JH7110_SYSCLK_ISP_AXI), 116 /* hifi4 */ 117 JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT), 118 JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE), 119 /* axi_cfg1 */ 120 JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL, 121 JH7110_SYSCLK_ISP_AXI), 122 JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL, 123 JH7110_SYSCLK_AHB0), 124 /* vout */ 125 JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT), 126 JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT), 127 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI), 128 JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1), 129 JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI), 130 JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0, 131 JH7110_SYSCLK_MCLK), 132 JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2, 133 JH7110_SYSCLK_OSC), 134 /* jpegc */ 135 JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT), 136 JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI), 137 JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT), 138 JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS), 139 /* vdec */ 140 JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT), 141 JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI), 142 JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT), 143 JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT), 144 JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS), 145 JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI), 146 JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI), 147 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI), 148 /* venc */ 149 JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT), 150 JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI), 151 JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT), 152 JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT), 153 JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS), 154 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI), 155 /* axi_cfg0 */ 156 JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL, 157 JH7110_SYSCLK_AHB1), 158 JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL, 159 JH7110_SYSCLK_AXI_CFG0), 160 JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL, 161 JH7110_SYSCLK_HIFI4_AXI), 162 /* intmem */ 163 JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0), 164 /* qspi */ 165 JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1), 166 JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS), 167 JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT), 168 JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2, 169 JH7110_SYSCLK_OSC, 170 JH7110_SYSCLK_QSPI_REF_SRC), 171 /* sdio */ 172 JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0), 173 JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0), 174 JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), 175 JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), 176 /* stg */ 177 JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT), 178 JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL, 179 JH7110_SYSCLK_NOCSTG_BUS), 180 /* gmac1 */ 181 JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0), 182 JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB), 183 JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT), 184 JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT), 185 JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30, 186 JH7110_SYSCLK_GMAC1_RMII_REFIN), 187 JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), 188 JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2, 189 JH7110_SYSCLK_GMAC1_RGMII_RXIN, 190 JH7110_SYSCLK_GMAC1_RMII_RTX), 191 JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX), 192 JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", 193 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, 194 JH7110_SYSCLK_GMAC1_GTXCLK, 195 JH7110_SYSCLK_GMAC1_RMII_RTX), 196 JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX), 197 JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK), 198 /* gmac0 */ 199 JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT), 200 JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), 201 JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC), 202 JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK), 203 /* apb misc */ 204 JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS), 205 JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS), 206 JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS), 207 /* can0 */ 208 JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS), 209 JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC), 210 JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), 211 /* can1 */ 212 JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS), 213 JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC), 214 JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), 215 /* pwm */ 216 JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS), 217 /* wdt */ 218 JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS), 219 JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC), 220 /* timer */ 221 JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS), 222 JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC), 223 JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC), 224 JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC), 225 JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC), 226 /* temp sensor */ 227 JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS), 228 JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC), 229 /* spi */ 230 JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0), 231 JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0), 232 JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0), 233 JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS), 234 JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS), 235 JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS), 236 JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS), 237 /* i2c */ 238 JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0), 239 JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0), 240 JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0), 241 JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS), 242 JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS), 243 JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS), 244 JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS), 245 /* uart */ 246 JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0), 247 JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC), 248 JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0), 249 JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC), 250 JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0), 251 JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC), 252 JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0), 253 JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), 254 JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0), 255 JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), 256 JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0), 257 JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), 258 /* pwmdac */ 259 JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0), 260 JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT), 261 /* spdif */ 262 JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0), 263 JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK), 264 /* i2stx0 */ 265 JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0), 266 JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), 267 JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv", 268 JH7110_SYSCLK_I2STX0_BCLK_MST), 269 JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2, 270 JH7110_SYSCLK_I2STX0_BCLK_MST_INV, 271 JH7110_SYSCLK_I2STX0_BCLK_MST), 272 JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2, 273 JH7110_SYSCLK_I2STX0_BCLK_MST, 274 JH7110_SYSCLK_I2STX_BCLK_EXT), 275 JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK), 276 JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2, 277 JH7110_SYSCLK_I2STX0_LRCK_MST, 278 JH7110_SYSCLK_I2STX_LRCK_EXT), 279 /* i2stx1 */ 280 JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0), 281 JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), 282 JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv", 283 JH7110_SYSCLK_I2STX1_BCLK_MST), 284 JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2, 285 JH7110_SYSCLK_I2STX1_BCLK_MST_INV, 286 JH7110_SYSCLK_I2STX1_BCLK_MST), 287 JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2, 288 JH7110_SYSCLK_I2STX1_BCLK_MST, 289 JH7110_SYSCLK_I2STX_BCLK_EXT), 290 JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK), 291 JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2, 292 JH7110_SYSCLK_I2STX1_LRCK_MST, 293 JH7110_SYSCLK_I2STX_LRCK_EXT), 294 /* i2srx */ 295 JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0), 296 JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), 297 JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv", 298 JH7110_SYSCLK_I2SRX_BCLK_MST), 299 JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2, 300 JH7110_SYSCLK_I2SRX_BCLK_MST_INV, 301 JH7110_SYSCLK_I2SRX_BCLK_MST), 302 JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2, 303 JH7110_SYSCLK_I2SRX_BCLK_MST, 304 JH7110_SYSCLK_I2SRX_BCLK_EXT), 305 JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK), 306 JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2, 307 JH7110_SYSCLK_I2SRX_LRCK_MST, 308 JH7110_SYSCLK_I2SRX_LRCK_EXT), 309 /* pdm */ 310 JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK), 311 JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0), 312 /* tdm */ 313 JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0), 314 JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0), 315 JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK), 316 JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2, 317 JH7110_SYSCLK_TDM_INTERNAL, 318 JH7110_SYSCLK_TDM_EXT), 319 JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM), 320 /* jtag */ 321 JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4, 322 JH7110_SYSCLK_OSC), 323 }; 324 325 static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data) 326 { 327 struct jh71x0_clk_priv *priv = data; 328 unsigned int idx = clkspec->args[0]; 329 330 if (idx < JH7110_SYSCLK_END) 331 return &priv->reg[idx].hw; 332 333 return ERR_PTR(-EINVAL); 334 } 335 336 static void jh7110_reset_unregister_adev(void *_adev) 337 { 338 struct auxiliary_device *adev = _adev; 339 340 auxiliary_device_delete(adev); 341 auxiliary_device_uninit(adev); 342 } 343 344 static void jh7110_reset_adev_release(struct device *dev) 345 { 346 struct auxiliary_device *adev = to_auxiliary_dev(dev); 347 struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev); 348 349 kfree(rdev); 350 } 351 352 int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, 353 const char *adev_name, 354 u32 adev_id) 355 { 356 struct jh71x0_reset_adev *rdev; 357 struct auxiliary_device *adev; 358 int ret; 359 360 rdev = kzalloc(sizeof(*rdev), GFP_KERNEL); 361 if (!rdev) 362 return -ENOMEM; 363 364 rdev->base = priv->base; 365 366 adev = &rdev->adev; 367 adev->name = adev_name; 368 adev->dev.parent = priv->dev; 369 adev->dev.release = jh7110_reset_adev_release; 370 adev->id = adev_id; 371 372 ret = auxiliary_device_init(adev); 373 if (ret) 374 return ret; 375 376 ret = auxiliary_device_add(adev); 377 if (ret) { 378 auxiliary_device_uninit(adev); 379 return ret; 380 } 381 382 return devm_add_action_or_reset(priv->dev, 383 jh7110_reset_unregister_adev, adev); 384 } 385 EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); 386 387 static int __init jh7110_syscrg_probe(struct platform_device *pdev) 388 { 389 struct jh71x0_clk_priv *priv; 390 unsigned int idx; 391 int ret; 392 393 priv = devm_kzalloc(&pdev->dev, 394 struct_size(priv, reg, JH7110_SYSCLK_END), 395 GFP_KERNEL); 396 if (!priv) 397 return -ENOMEM; 398 399 spin_lock_init(&priv->rmw_lock); 400 priv->dev = &pdev->dev; 401 priv->base = devm_platform_ioremap_resource(pdev, 0); 402 if (IS_ERR(priv->base)) 403 return PTR_ERR(priv->base); 404 405 /* 406 * These PLL clocks are not actually fixed factor clocks and can be 407 * controlled by the syscon registers of JH7110. They will be dropped 408 * and registered in the PLL clock driver instead. 409 */ 410 /* 24MHz -> 1000.0MHz */ 411 priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out", 412 "osc", 0, 125, 3); 413 if (IS_ERR(priv->pll[0])) 414 return PTR_ERR(priv->pll[0]); 415 416 /* 24MHz -> 1066.0MHz */ 417 priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out", 418 "osc", 0, 533, 12); 419 if (IS_ERR(priv->pll[1])) 420 return PTR_ERR(priv->pll[1]); 421 422 /* 24MHz -> 1188.0MHz */ 423 priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out", 424 "osc", 0, 99, 2); 425 if (IS_ERR(priv->pll[2])) 426 return PTR_ERR(priv->pll[2]); 427 428 for (idx = 0; idx < JH7110_SYSCLK_END; idx++) { 429 u32 max = jh7110_sysclk_data[idx].max; 430 struct clk_parent_data parents[4] = {}; 431 struct clk_init_data init = { 432 .name = jh7110_sysclk_data[idx].name, 433 .ops = starfive_jh71x0_clk_ops(max), 434 .parent_data = parents, 435 .num_parents = 436 ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, 437 .flags = jh7110_sysclk_data[idx].flags, 438 }; 439 struct jh71x0_clk *clk = &priv->reg[idx]; 440 unsigned int i; 441 442 for (i = 0; i < init.num_parents; i++) { 443 unsigned int pidx = jh7110_sysclk_data[idx].parents[i]; 444 445 if (pidx < JH7110_SYSCLK_END) 446 parents[i].hw = &priv->reg[pidx].hw; 447 else if (pidx == JH7110_SYSCLK_OSC) 448 parents[i].fw_name = "osc"; 449 else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN) 450 parents[i].fw_name = "gmac1_rmii_refin"; 451 else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN) 452 parents[i].fw_name = "gmac1_rgmii_rxin"; 453 else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT) 454 parents[i].fw_name = "i2stx_bclk_ext"; 455 else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT) 456 parents[i].fw_name = "i2stx_lrck_ext"; 457 else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT) 458 parents[i].fw_name = "i2srx_bclk_ext"; 459 else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT) 460 parents[i].fw_name = "i2srx_lrck_ext"; 461 else if (pidx == JH7110_SYSCLK_TDM_EXT) 462 parents[i].fw_name = "tdm_ext"; 463 else if (pidx == JH7110_SYSCLK_MCLK_EXT) 464 parents[i].fw_name = "mclk_ext"; 465 else 466 parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT]; 467 } 468 469 clk->hw.init = &init; 470 clk->idx = idx; 471 clk->max_div = max & JH71X0_CLK_DIV_MASK; 472 473 ret = devm_clk_hw_register(&pdev->dev, &clk->hw); 474 if (ret) 475 return ret; 476 } 477 478 ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv); 479 if (ret) 480 return ret; 481 482 return jh7110_reset_controller_register(priv, "rst-sys", 0); 483 } 484 485 static const struct of_device_id jh7110_syscrg_match[] = { 486 { .compatible = "starfive,jh7110-syscrg" }, 487 { /* sentinel */ } 488 }; 489 490 static struct platform_driver jh7110_syscrg_driver = { 491 .driver = { 492 .name = "clk-starfive-jh7110-sys", 493 .of_match_table = jh7110_syscrg_match, 494 .suppress_bind_attrs = true, 495 }, 496 }; 497 builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe); 498