1 /* 2 * Copyright (C) 2014 STMicroelectronics R&D Ltd 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 */ 9 10 /* 11 * Authors: 12 * Stephen Gallimore <stephen.gallimore@st.com>, 13 * Pankaj Dev <pankaj.dev@st.com>. 14 */ 15 16 #include <linux/slab.h> 17 #include <linux/of_address.h> 18 #include <linux/clk.h> 19 #include <linux/clk-provider.h> 20 21 #include "clkgen.h" 22 23 /* 24 * Maximum input clock to the PLL before we divide it down by 2 25 * although in reality in actual systems this has never been seen to 26 * be used. 27 */ 28 #define QUADFS_NDIV_THRESHOLD 30000000 29 30 #define PLL_BW_GOODREF (0L) 31 #define PLL_BW_VBADREF (1L) 32 #define PLL_BW_BADREF (2L) 33 #define PLL_BW_VGOODREF (3L) 34 35 #define QUADFS_MAX_CHAN 4 36 37 struct stm_fs { 38 unsigned long ndiv; 39 unsigned long mdiv; 40 unsigned long pe; 41 unsigned long sdiv; 42 unsigned long nsdiv; 43 }; 44 45 static const struct stm_fs fs216c65_rtbl[] = { 46 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 312.5 Khz */ 47 { .mdiv = 0x17, .pe = 0x25ed, .sdiv = 0x1, .nsdiv = 0 }, /* 27 MHz */ 48 { .mdiv = 0x1a, .pe = 0x7b36, .sdiv = 0x2, .nsdiv = 1 }, /* 36.87 MHz */ 49 { .mdiv = 0x13, .pe = 0x0, .sdiv = 0x2, .nsdiv = 1 }, /* 48 MHz */ 50 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x1, .nsdiv = 1 }, /* 108 MHz */ 51 }; 52 53 static const struct stm_fs fs432c65_rtbl[] = { 54 { .mdiv = 0x1f, .pe = 0x0, .sdiv = 0x7, .nsdiv = 0 }, /* 625 Khz */ 55 { .mdiv = 0x13, .pe = 0x777c, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */ 56 { .mdiv = 0x19, .pe = 0x4d35, .sdiv = 0x2, .nsdiv = 0 }, /* 25.200 MHz */ 57 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */ 58 { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x2, .nsdiv = 0 }, /* 27.027 MHz */ 59 { .mdiv = 0x16, .pe = 0x3359, .sdiv = 0x2, .nsdiv = 0 }, /* 28.320 MHz */ 60 { .mdiv = 0x1f, .pe = 0x2083, .sdiv = 0x3, .nsdiv = 1 }, /* 30.240 MHz */ 61 { .mdiv = 0x1e, .pe = 0x430d, .sdiv = 0x3, .nsdiv = 1 }, /* 31.500 MHz */ 62 { .mdiv = 0x17, .pe = 0x0, .sdiv = 0x3, .nsdiv = 1 }, /* 40.000 MHz */ 63 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 0 }, /* 49.500 MHz */ 64 { .mdiv = 0x13, .pe = 0x6667, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */ 65 { .mdiv = 0x10, .pe = 0x1ee6, .sdiv = 0x3, .nsdiv = 1 }, /* 57.284 MHz */ 66 { .mdiv = 0x1d, .pe = 0x3b14, .sdiv = 0x2, .nsdiv = 1 }, /* 65.000 MHz */ 67 { .mdiv = 0x12, .pe = 0x7c65, .sdiv = 0x1, .nsdiv = 0 }, /* 71.000 MHz */ 68 { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x2, .nsdiv = 1 }, /* 74.176 MHz */ 69 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x2, .nsdiv = 1 }, /* 74.250 MHz */ 70 { .mdiv = 0x19, .pe = 0x3334, .sdiv = 0x2, .nsdiv = 1 }, /* 75.000 MHz */ 71 { .mdiv = 0x18, .pe = 0x5138, .sdiv = 0x2, .nsdiv = 1 }, /* 78.800 MHz */ 72 { .mdiv = 0x1d, .pe = 0x77d, .sdiv = 0x0, .nsdiv = 0 }, /* 85.500 MHz */ 73 { .mdiv = 0x1c, .pe = 0x13d5, .sdiv = 0x0, .nsdiv = 0 }, /* 88.750 MHz */ 74 { .mdiv = 0x11, .pe = 0x1c72, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */ 75 { .mdiv = 0x17, .pe = 0x28f5, .sdiv = 0x0, .nsdiv = 0 }, /* 108.108 MHz */ 76 { .mdiv = 0x10, .pe = 0x6e26, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */ 77 { .mdiv = 0x15, .pe = 0x3e63, .sdiv = 0x0, .nsdiv = 0 }, /* 119.000 MHz */ 78 { .mdiv = 0x1c, .pe = 0x471d, .sdiv = 0x1, .nsdiv = 1 }, /* 135.000 MHz */ 79 { .mdiv = 0x19, .pe = 0xecd, .sdiv = 0x1, .nsdiv = 1 }, /* 148.352 MHz */ 80 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x1, .nsdiv = 1 }, /* 148.500 MHz */ 81 { .mdiv = 0x19, .pe = 0x121a, .sdiv = 0x0, .nsdiv = 1 }, /* 297 MHz */ 82 }; 83 84 static const struct stm_fs fs660c32_rtbl[] = { 85 { .mdiv = 0x14, .pe = 0x376b, .sdiv = 0x4, .nsdiv = 1 }, /* 25.175 MHz */ 86 { .mdiv = 0x14, .pe = 0x30c3, .sdiv = 0x4, .nsdiv = 1 }, /* 25.200 MHz */ 87 { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x4, .nsdiv = 1 }, /* 27.000 MHz */ 88 { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x3, .nsdiv = 0 }, /* 27.027 MHz */ 89 { .mdiv = 0x0e, .pe = 0x4e1a, .sdiv = 0x4, .nsdiv = 1 }, /* 28.320 MHz */ 90 { .mdiv = 0x0b, .pe = 0x534d, .sdiv = 0x4, .nsdiv = 1 }, /* 30.240 MHz */ 91 { .mdiv = 0x17, .pe = 0x6fbf, .sdiv = 0x2, .nsdiv = 0 }, /* 31.500 MHz */ 92 { .mdiv = 0x01, .pe = 0x0, .sdiv = 0x4, .nsdiv = 1 }, /* 40.000 MHz */ 93 { .mdiv = 0x15, .pe = 0x2aab, .sdiv = 0x3, .nsdiv = 1 }, /* 49.500 MHz */ 94 { .mdiv = 0x14, .pe = 0x6666, .sdiv = 0x3, .nsdiv = 1 }, /* 50.000 MHz */ 95 { .mdiv = 0x1d, .pe = 0x395f, .sdiv = 0x1, .nsdiv = 0 }, /* 57.284 MHz */ 96 { .mdiv = 0x08, .pe = 0x4ec5, .sdiv = 0x3, .nsdiv = 1 }, /* 65.000 MHz */ 97 { .mdiv = 0x05, .pe = 0x1770, .sdiv = 0x3, .nsdiv = 1 }, /* 71.000 MHz */ 98 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x3, .nsdiv = 1 }, /* 74.176 MHz */ 99 { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x1, .nsdiv = 0 }, /* 74.250 MHz */ 100 { .mdiv = 0x0e, .pe = 0x7777, .sdiv = 0x1, .nsdiv = 0 }, /* 75.000 MHz */ 101 { .mdiv = 0x01, .pe = 0x4053, .sdiv = 0x3, .nsdiv = 1 }, /* 78.800 MHz */ 102 { .mdiv = 0x09, .pe = 0x15b5, .sdiv = 0x1, .nsdiv = 0 }, /* 85.500 MHz */ 103 { .mdiv = 0x1b, .pe = 0x3f19, .sdiv = 0x2, .nsdiv = 1 }, /* 88.750 MHz */ 104 { .mdiv = 0x10, .pe = 0x71c7, .sdiv = 0x2, .nsdiv = 1 }, /* 108.000 MHz */ 105 { .mdiv = 0x00, .pe = 0x47af, .sdiv = 0x1, .nsdiv = 0 }, /* 108.108 MHz */ 106 { .mdiv = 0x0c, .pe = 0x3118, .sdiv = 0x2, .nsdiv = 1 }, /* 118.963 MHz */ 107 { .mdiv = 0x0c, .pe = 0x2f54, .sdiv = 0x2, .nsdiv = 1 }, /* 119.000 MHz */ 108 { .mdiv = 0x07, .pe = 0xe39, .sdiv = 0x2, .nsdiv = 1 }, /* 135.000 MHz */ 109 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x2, .nsdiv = 1 }, /* 148.352 MHz */ 110 { .mdiv = 0x0f, .pe = 0x3426, .sdiv = 0x0, .nsdiv = 0 }, /* 148.500 MHz */ 111 { .mdiv = 0x03, .pe = 0x4ba7, .sdiv = 0x1, .nsdiv = 1 }, /* 296.704 MHz */ 112 { .mdiv = 0x03, .pe = 0x471c, .sdiv = 0x1, .nsdiv = 1 }, /* 297.000 MHz */ 113 { .mdiv = 0x00, .pe = 0x295f, .sdiv = 0x1, .nsdiv = 1 }, /* 326.700 MHz */ 114 { .mdiv = 0x1f, .pe = 0x3633, .sdiv = 0x0, .nsdiv = 1 }, /* 333.000 MHz */ 115 { .mdiv = 0x1c, .pe = 0x0, .sdiv = 0x0, .nsdiv = 1 }, /* 352.000 Mhz */ 116 }; 117 118 struct clkgen_quadfs_data { 119 bool reset_present; 120 bool bwfilter_present; 121 bool lockstatus_present; 122 bool powerup_polarity; 123 bool standby_polarity; 124 bool nsdiv_present; 125 bool nrst_present; 126 struct clkgen_field ndiv; 127 struct clkgen_field ref_bw; 128 struct clkgen_field nreset; 129 struct clkgen_field npda; 130 struct clkgen_field lock_status; 131 132 struct clkgen_field nrst[QUADFS_MAX_CHAN]; 133 struct clkgen_field nsb[QUADFS_MAX_CHAN]; 134 struct clkgen_field en[QUADFS_MAX_CHAN]; 135 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; 136 struct clkgen_field pe[QUADFS_MAX_CHAN]; 137 struct clkgen_field sdiv[QUADFS_MAX_CHAN]; 138 struct clkgen_field nsdiv[QUADFS_MAX_CHAN]; 139 140 const struct clk_ops *pll_ops; 141 const struct stm_fs *rtbl; 142 u8 rtbl_cnt; 143 int (*get_rate)(unsigned long , const struct stm_fs *, 144 unsigned long *); 145 }; 146 147 static const struct clk_ops st_quadfs_pll_c65_ops; 148 static const struct clk_ops st_quadfs_pll_c32_ops; 149 static const struct clk_ops st_quadfs_fs216c65_ops; 150 static const struct clk_ops st_quadfs_fs432c65_ops; 151 static const struct clk_ops st_quadfs_fs660c32_ops; 152 153 static int clk_fs216c65_get_rate(unsigned long, const struct stm_fs *, 154 unsigned long *); 155 static int clk_fs432c65_get_rate(unsigned long, const struct stm_fs *, 156 unsigned long *); 157 static int clk_fs660c32_dig_get_rate(unsigned long, const struct stm_fs *, 158 unsigned long *); 159 /* 160 * Values for all of the standalone instances of this clock 161 * generator found in STiH415 and STiH416 SYSCFG register banks. Note 162 * that the individual channel standby control bits (nsb) are in the 163 * first register along with the PLL control bits. 164 */ 165 static const struct clkgen_quadfs_data st_fs216c65_416 = { 166 /* 416 specific */ 167 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 168 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 169 CLKGEN_FIELD(0x0, 0x1, 11), 170 CLKGEN_FIELD(0x0, 0x1, 12), 171 CLKGEN_FIELD(0x0, 0x1, 13) }, 172 .nsdiv_present = true, 173 .nsdiv = { CLKGEN_FIELD(0x0, 0x1, 18), 174 CLKGEN_FIELD(0x0, 0x1, 19), 175 CLKGEN_FIELD(0x0, 0x1, 20), 176 CLKGEN_FIELD(0x0, 0x1, 21) }, 177 .mdiv = { CLKGEN_FIELD(0x4, 0x1f, 0), 178 CLKGEN_FIELD(0x14, 0x1f, 0), 179 CLKGEN_FIELD(0x24, 0x1f, 0), 180 CLKGEN_FIELD(0x34, 0x1f, 0) }, 181 .en = { CLKGEN_FIELD(0x10, 0x1, 0), 182 CLKGEN_FIELD(0x20, 0x1, 0), 183 CLKGEN_FIELD(0x30, 0x1, 0), 184 CLKGEN_FIELD(0x40, 0x1, 0) }, 185 .ndiv = CLKGEN_FIELD(0x0, 0x1, 15), 186 .bwfilter_present = true, 187 .ref_bw = CLKGEN_FIELD(0x0, 0x3, 16), 188 .pe = { CLKGEN_FIELD(0x8, 0xffff, 0), 189 CLKGEN_FIELD(0x18, 0xffff, 0), 190 CLKGEN_FIELD(0x28, 0xffff, 0), 191 CLKGEN_FIELD(0x38, 0xffff, 0) }, 192 .sdiv = { CLKGEN_FIELD(0xC, 0x7, 0), 193 CLKGEN_FIELD(0x1C, 0x7, 0), 194 CLKGEN_FIELD(0x2C, 0x7, 0), 195 CLKGEN_FIELD(0x3C, 0x7, 0) }, 196 .pll_ops = &st_quadfs_pll_c65_ops, 197 .rtbl = fs216c65_rtbl, 198 .rtbl_cnt = ARRAY_SIZE(fs216c65_rtbl), 199 .get_rate = clk_fs216c65_get_rate, 200 }; 201 202 static const struct clkgen_quadfs_data st_fs432c65_416 = { 203 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 204 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 205 CLKGEN_FIELD(0x0, 0x1, 11), 206 CLKGEN_FIELD(0x0, 0x1, 12), 207 CLKGEN_FIELD(0x0, 0x1, 13) }, 208 .nsdiv_present = true, 209 .nsdiv = { CLKGEN_FIELD(0x0, 0x1, 18), 210 CLKGEN_FIELD(0x0, 0x1, 19), 211 CLKGEN_FIELD(0x0, 0x1, 20), 212 CLKGEN_FIELD(0x0, 0x1, 21) }, 213 .mdiv = { CLKGEN_FIELD(0x4, 0x1f, 0), 214 CLKGEN_FIELD(0x14, 0x1f, 0), 215 CLKGEN_FIELD(0x24, 0x1f, 0), 216 CLKGEN_FIELD(0x34, 0x1f, 0) }, 217 .en = { CLKGEN_FIELD(0x10, 0x1, 0), 218 CLKGEN_FIELD(0x20, 0x1, 0), 219 CLKGEN_FIELD(0x30, 0x1, 0), 220 CLKGEN_FIELD(0x40, 0x1, 0) }, 221 .ndiv = CLKGEN_FIELD(0x0, 0x1, 15), 222 .bwfilter_present = true, 223 .ref_bw = CLKGEN_FIELD(0x0, 0x3, 16), 224 .pe = { CLKGEN_FIELD(0x8, 0xffff, 0), 225 CLKGEN_FIELD(0x18, 0xffff, 0), 226 CLKGEN_FIELD(0x28, 0xffff, 0), 227 CLKGEN_FIELD(0x38, 0xffff, 0) }, 228 .sdiv = { CLKGEN_FIELD(0xC, 0x7, 0), 229 CLKGEN_FIELD(0x1C, 0x7, 0), 230 CLKGEN_FIELD(0x2C, 0x7, 0), 231 CLKGEN_FIELD(0x3C, 0x7, 0) }, 232 .pll_ops = &st_quadfs_pll_c65_ops, 233 .rtbl = fs432c65_rtbl, 234 .rtbl_cnt = ARRAY_SIZE(fs432c65_rtbl), 235 .get_rate = clk_fs432c65_get_rate, 236 }; 237 238 static const struct clkgen_quadfs_data st_fs660c32_E_416 = { 239 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 240 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 241 CLKGEN_FIELD(0x0, 0x1, 11), 242 CLKGEN_FIELD(0x0, 0x1, 12), 243 CLKGEN_FIELD(0x0, 0x1, 13) }, 244 .nsdiv_present = true, 245 .nsdiv = { CLKGEN_FIELD(0x0, 0x1, 18), 246 CLKGEN_FIELD(0x0, 0x1, 19), 247 CLKGEN_FIELD(0x0, 0x1, 20), 248 CLKGEN_FIELD(0x0, 0x1, 21) }, 249 .mdiv = { CLKGEN_FIELD(0x4, 0x1f, 0), 250 CLKGEN_FIELD(0x14, 0x1f, 0), 251 CLKGEN_FIELD(0x24, 0x1f, 0), 252 CLKGEN_FIELD(0x34, 0x1f, 0) }, 253 .en = { CLKGEN_FIELD(0x10, 0x1, 0), 254 CLKGEN_FIELD(0x20, 0x1, 0), 255 CLKGEN_FIELD(0x30, 0x1, 0), 256 CLKGEN_FIELD(0x40, 0x1, 0) }, 257 .ndiv = CLKGEN_FIELD(0x0, 0x7, 15), 258 .pe = { CLKGEN_FIELD(0x8, 0x7fff, 0), 259 CLKGEN_FIELD(0x18, 0x7fff, 0), 260 CLKGEN_FIELD(0x28, 0x7fff, 0), 261 CLKGEN_FIELD(0x38, 0x7fff, 0) }, 262 .sdiv = { CLKGEN_FIELD(0xC, 0xf, 0), 263 CLKGEN_FIELD(0x1C, 0xf, 0), 264 CLKGEN_FIELD(0x2C, 0xf, 0), 265 CLKGEN_FIELD(0x3C, 0xf, 0) }, 266 .lockstatus_present = true, 267 .lock_status = CLKGEN_FIELD(0xAC, 0x1, 0), 268 .pll_ops = &st_quadfs_pll_c32_ops, 269 .rtbl = fs660c32_rtbl, 270 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl), 271 .get_rate = clk_fs660c32_dig_get_rate, 272 }; 273 274 static const struct clkgen_quadfs_data st_fs660c32_F_416 = { 275 .npda = CLKGEN_FIELD(0x0, 0x1, 14), 276 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10), 277 CLKGEN_FIELD(0x0, 0x1, 11), 278 CLKGEN_FIELD(0x0, 0x1, 12), 279 CLKGEN_FIELD(0x0, 0x1, 13) }, 280 .nsdiv_present = true, 281 .nsdiv = { CLKGEN_FIELD(0x0, 0x1, 18), 282 CLKGEN_FIELD(0x0, 0x1, 19), 283 CLKGEN_FIELD(0x0, 0x1, 20), 284 CLKGEN_FIELD(0x0, 0x1, 21) }, 285 .mdiv = { CLKGEN_FIELD(0x4, 0x1f, 0), 286 CLKGEN_FIELD(0x14, 0x1f, 0), 287 CLKGEN_FIELD(0x24, 0x1f, 0), 288 CLKGEN_FIELD(0x34, 0x1f, 0) }, 289 .en = { CLKGEN_FIELD(0x10, 0x1, 0), 290 CLKGEN_FIELD(0x20, 0x1, 0), 291 CLKGEN_FIELD(0x30, 0x1, 0), 292 CLKGEN_FIELD(0x40, 0x1, 0) }, 293 .ndiv = CLKGEN_FIELD(0x0, 0x7, 15), 294 .pe = { CLKGEN_FIELD(0x8, 0x7fff, 0), 295 CLKGEN_FIELD(0x18, 0x7fff, 0), 296 CLKGEN_FIELD(0x28, 0x7fff, 0), 297 CLKGEN_FIELD(0x38, 0x7fff, 0) }, 298 .sdiv = { CLKGEN_FIELD(0xC, 0xf, 0), 299 CLKGEN_FIELD(0x1C, 0xf, 0), 300 CLKGEN_FIELD(0x2C, 0xf, 0), 301 CLKGEN_FIELD(0x3C, 0xf, 0) }, 302 .lockstatus_present = true, 303 .lock_status = CLKGEN_FIELD(0xEC, 0x1, 0), 304 .pll_ops = &st_quadfs_pll_c32_ops, 305 .rtbl = fs660c32_rtbl, 306 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl), 307 .get_rate = clk_fs660c32_dig_get_rate, 308 }; 309 310 static const struct clkgen_quadfs_data st_fs660c32_C = { 311 .nrst_present = true, 312 .nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0), 313 CLKGEN_FIELD(0x2f0, 0x1, 1), 314 CLKGEN_FIELD(0x2f0, 0x1, 2), 315 CLKGEN_FIELD(0x2f0, 0x1, 3) }, 316 .npda = CLKGEN_FIELD(0x2f0, 0x1, 12), 317 .nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8), 318 CLKGEN_FIELD(0x2f0, 0x1, 9), 319 CLKGEN_FIELD(0x2f0, 0x1, 10), 320 CLKGEN_FIELD(0x2f0, 0x1, 11) }, 321 .nsdiv_present = true, 322 .nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24), 323 CLKGEN_FIELD(0x308, 0x1, 24), 324 CLKGEN_FIELD(0x30c, 0x1, 24), 325 CLKGEN_FIELD(0x310, 0x1, 24) }, 326 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15), 327 CLKGEN_FIELD(0x308, 0x1f, 15), 328 CLKGEN_FIELD(0x30c, 0x1f, 15), 329 CLKGEN_FIELD(0x310, 0x1f, 15) }, 330 .en = { CLKGEN_FIELD(0x2fc, 0x1, 0), 331 CLKGEN_FIELD(0x2fc, 0x1, 1), 332 CLKGEN_FIELD(0x2fc, 0x1, 2), 333 CLKGEN_FIELD(0x2fc, 0x1, 3) }, 334 .ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16), 335 .pe = { CLKGEN_FIELD(0x304, 0x7fff, 0), 336 CLKGEN_FIELD(0x308, 0x7fff, 0), 337 CLKGEN_FIELD(0x30c, 0x7fff, 0), 338 CLKGEN_FIELD(0x310, 0x7fff, 0) }, 339 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20), 340 CLKGEN_FIELD(0x308, 0xf, 20), 341 CLKGEN_FIELD(0x30c, 0xf, 20), 342 CLKGEN_FIELD(0x310, 0xf, 20) }, 343 .lockstatus_present = true, 344 .lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24), 345 .powerup_polarity = 1, 346 .standby_polarity = 1, 347 .pll_ops = &st_quadfs_pll_c32_ops, 348 .rtbl = fs660c32_rtbl, 349 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl), 350 .get_rate = clk_fs660c32_dig_get_rate, 351 }; 352 353 static const struct clkgen_quadfs_data st_fs660c32_D = { 354 .nrst_present = true, 355 .nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0), 356 CLKGEN_FIELD(0x2a0, 0x1, 1), 357 CLKGEN_FIELD(0x2a0, 0x1, 2), 358 CLKGEN_FIELD(0x2a0, 0x1, 3) }, 359 .ndiv = CLKGEN_FIELD(0x2a4, 0x7, 16), 360 .pe = { CLKGEN_FIELD(0x2b4, 0x7fff, 0), 361 CLKGEN_FIELD(0x2b8, 0x7fff, 0), 362 CLKGEN_FIELD(0x2bc, 0x7fff, 0), 363 CLKGEN_FIELD(0x2c0, 0x7fff, 0) }, 364 .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20), 365 CLKGEN_FIELD(0x2b8, 0xf, 20), 366 CLKGEN_FIELD(0x2bc, 0xf, 20), 367 CLKGEN_FIELD(0x2c0, 0xf, 20) }, 368 .npda = CLKGEN_FIELD(0x2a0, 0x1, 12), 369 .nsb = { CLKGEN_FIELD(0x2a0, 0x1, 8), 370 CLKGEN_FIELD(0x2a0, 0x1, 9), 371 CLKGEN_FIELD(0x2a0, 0x1, 10), 372 CLKGEN_FIELD(0x2a0, 0x1, 11) }, 373 .nsdiv_present = true, 374 .nsdiv = { CLKGEN_FIELD(0x2b4, 0x1, 24), 375 CLKGEN_FIELD(0x2b8, 0x1, 24), 376 CLKGEN_FIELD(0x2bc, 0x1, 24), 377 CLKGEN_FIELD(0x2c0, 0x1, 24) }, 378 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15), 379 CLKGEN_FIELD(0x2b8, 0x1f, 15), 380 CLKGEN_FIELD(0x2bc, 0x1f, 15), 381 CLKGEN_FIELD(0x2c0, 0x1f, 15) }, 382 .en = { CLKGEN_FIELD(0x2ac, 0x1, 0), 383 CLKGEN_FIELD(0x2ac, 0x1, 1), 384 CLKGEN_FIELD(0x2ac, 0x1, 2), 385 CLKGEN_FIELD(0x2ac, 0x1, 3) }, 386 .lockstatus_present = true, 387 .lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24), 388 .powerup_polarity = 1, 389 .standby_polarity = 1, 390 .pll_ops = &st_quadfs_pll_c32_ops, 391 .rtbl = fs660c32_rtbl, 392 .rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl), 393 .get_rate = clk_fs660c32_dig_get_rate,}; 394 395 /** 396 * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor 397 * 398 * Traits of this clock: 399 * prepare - clk_(un)prepare only ensures parent is (un)prepared 400 * enable - clk_enable and clk_disable are functional & control the Fsyn 401 * rate - inherits rate from parent. set_rate/round_rate/recalc_rate 402 * parent - fixed parent. No clk_set_parent support 403 */ 404 405 /** 406 * struct st_clk_quadfs_pll - A pll which outputs a fixed multiplier of 407 * its parent clock, found inside a type of 408 * ST quad channel frequency synthesizer block 409 * 410 * @hw: handle between common and hardware-specific interfaces. 411 * @ndiv: regmap field for the ndiv control. 412 * @regs_base: base address of the configuration registers. 413 * @lock: spinlock. 414 * 415 */ 416 struct st_clk_quadfs_pll { 417 struct clk_hw hw; 418 void __iomem *regs_base; 419 spinlock_t *lock; 420 struct clkgen_quadfs_data *data; 421 u32 ndiv; 422 }; 423 424 #define to_quadfs_pll(_hw) container_of(_hw, struct st_clk_quadfs_pll, hw) 425 426 static int quadfs_pll_enable(struct clk_hw *hw) 427 { 428 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); 429 unsigned long flags = 0, timeout = jiffies + msecs_to_jiffies(10); 430 431 if (pll->lock) 432 spin_lock_irqsave(pll->lock, flags); 433 434 /* 435 * Bring block out of reset if we have reset control. 436 */ 437 if (pll->data->reset_present) 438 CLKGEN_WRITE(pll, nreset, 1); 439 440 /* 441 * Use a fixed input clock noise bandwidth filter for the moment 442 */ 443 if (pll->data->bwfilter_present) 444 CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF); 445 446 447 CLKGEN_WRITE(pll, ndiv, pll->ndiv); 448 449 /* 450 * Power up the PLL 451 */ 452 CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity); 453 454 if (pll->lock) 455 spin_unlock_irqrestore(pll->lock, flags); 456 457 if (pll->data->lockstatus_present) 458 while (!CLKGEN_READ(pll, lock_status)) { 459 if (time_after(jiffies, timeout)) 460 return -ETIMEDOUT; 461 cpu_relax(); 462 } 463 464 return 0; 465 } 466 467 static void quadfs_pll_disable(struct clk_hw *hw) 468 { 469 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); 470 unsigned long flags = 0; 471 472 if (pll->lock) 473 spin_lock_irqsave(pll->lock, flags); 474 475 /* 476 * Powerdown the PLL and then put block into soft reset if we have 477 * reset control. 478 */ 479 CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity); 480 481 if (pll->data->reset_present) 482 CLKGEN_WRITE(pll, nreset, 0); 483 484 if (pll->lock) 485 spin_unlock_irqrestore(pll->lock, flags); 486 } 487 488 static int quadfs_pll_is_enabled(struct clk_hw *hw) 489 { 490 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); 491 u32 npda = CLKGEN_READ(pll, npda); 492 493 return pll->data->powerup_polarity ? !npda : !!npda; 494 } 495 496 static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs, 497 unsigned long *rate) 498 { 499 unsigned long nd = fs->ndiv + 16; /* ndiv value */ 500 501 *rate = input * nd; 502 503 return 0; 504 } 505 506 static unsigned long quadfs_pll_fs660c32_recalc_rate(struct clk_hw *hw, 507 unsigned long parent_rate) 508 { 509 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); 510 unsigned long rate = 0; 511 struct stm_fs params; 512 513 params.ndiv = CLKGEN_READ(pll, ndiv); 514 if (clk_fs660c32_vco_get_rate(parent_rate, ¶ms, &rate)) 515 pr_err("%s:%s error calculating rate\n", 516 clk_hw_get_name(hw), __func__); 517 518 pll->ndiv = params.ndiv; 519 520 return rate; 521 } 522 523 static int clk_fs660c32_vco_get_params(unsigned long input, 524 unsigned long output, struct stm_fs *fs) 525 { 526 /* Formula 527 VCO frequency = (fin x ndiv) / pdiv 528 ndiv = VCOfreq * pdiv / fin 529 */ 530 unsigned long pdiv = 1, n; 531 532 /* Output clock range: 384Mhz to 660Mhz */ 533 if (output < 384000000 || output > 660000000) 534 return -EINVAL; 535 536 if (input > 40000000) 537 /* This means that PDIV would be 2 instead of 1. 538 Not supported today. */ 539 return -EINVAL; 540 541 input /= 1000; 542 output /= 1000; 543 544 n = output * pdiv / input; 545 if (n < 16) 546 n = 16; 547 fs->ndiv = n - 16; /* Converting formula value to reg value */ 548 549 return 0; 550 } 551 552 static long quadfs_pll_fs660c32_round_rate(struct clk_hw *hw, 553 unsigned long rate, 554 unsigned long *prate) 555 { 556 struct stm_fs params; 557 558 if (clk_fs660c32_vco_get_params(*prate, rate, ¶ms)) 559 return rate; 560 561 clk_fs660c32_vco_get_rate(*prate, ¶ms, &rate); 562 563 pr_debug("%s: %s new rate %ld [ndiv=%u]\n", 564 __func__, clk_hw_get_name(hw), 565 rate, (unsigned int)params.ndiv); 566 567 return rate; 568 } 569 570 static int quadfs_pll_fs660c32_set_rate(struct clk_hw *hw, unsigned long rate, 571 unsigned long parent_rate) 572 { 573 struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw); 574 struct stm_fs params; 575 long hwrate = 0; 576 unsigned long flags = 0; 577 578 if (!rate || !parent_rate) 579 return -EINVAL; 580 581 if (!clk_fs660c32_vco_get_params(parent_rate, rate, ¶ms)) 582 clk_fs660c32_vco_get_rate(parent_rate, ¶ms, &hwrate); 583 584 pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n", 585 __func__, clk_hw_get_name(hw), 586 hwrate, (unsigned int)params.ndiv); 587 588 if (!hwrate) 589 return -EINVAL; 590 591 pll->ndiv = params.ndiv; 592 593 if (pll->lock) 594 spin_lock_irqsave(pll->lock, flags); 595 596 CLKGEN_WRITE(pll, ndiv, pll->ndiv); 597 598 if (pll->lock) 599 spin_unlock_irqrestore(pll->lock, flags); 600 601 return 0; 602 } 603 604 static const struct clk_ops st_quadfs_pll_c65_ops = { 605 .enable = quadfs_pll_enable, 606 .disable = quadfs_pll_disable, 607 .is_enabled = quadfs_pll_is_enabled, 608 }; 609 610 static const struct clk_ops st_quadfs_pll_c32_ops = { 611 .enable = quadfs_pll_enable, 612 .disable = quadfs_pll_disable, 613 .is_enabled = quadfs_pll_is_enabled, 614 .recalc_rate = quadfs_pll_fs660c32_recalc_rate, 615 .round_rate = quadfs_pll_fs660c32_round_rate, 616 .set_rate = quadfs_pll_fs660c32_set_rate, 617 }; 618 619 static struct clk * __init st_clk_register_quadfs_pll( 620 const char *name, const char *parent_name, 621 struct clkgen_quadfs_data *quadfs, void __iomem *reg, 622 spinlock_t *lock) 623 { 624 struct st_clk_quadfs_pll *pll; 625 struct clk *clk; 626 struct clk_init_data init; 627 628 /* 629 * Sanity check required pointers. 630 */ 631 if (WARN_ON(!name || !parent_name)) 632 return ERR_PTR(-EINVAL); 633 634 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 635 if (!pll) 636 return ERR_PTR(-ENOMEM); 637 638 init.name = name; 639 init.ops = quadfs->pll_ops; 640 init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE; 641 init.parent_names = &parent_name; 642 init.num_parents = 1; 643 644 pll->data = quadfs; 645 pll->regs_base = reg; 646 pll->lock = lock; 647 pll->hw.init = &init; 648 649 clk = clk_register(NULL, &pll->hw); 650 651 if (IS_ERR(clk)) 652 kfree(pll); 653 654 return clk; 655 } 656 657 /** 658 * DOC: A digital frequency synthesizer 659 * 660 * Traits of this clock: 661 * prepare - clk_(un)prepare only ensures parent is (un)prepared 662 * enable - clk_enable and clk_disable are functional 663 * rate - set rate is functional 664 * parent - fixed parent. No clk_set_parent support 665 */ 666 667 /** 668 * struct st_clk_quadfs_fsynth - One clock output from a four channel digital 669 * frequency synthesizer (fsynth) block. 670 * 671 * @hw: handle between common and hardware-specific interfaces 672 * 673 * @nsb: regmap field in the output control register for the digital 674 * standby of this fsynth channel. This control is active low so 675 * the channel is in standby when the control bit is cleared. 676 * 677 * @nsdiv: regmap field in the output control register for 678 * for the optional divide by 3 of this fsynth channel. This control 679 * is active low so the divide by 3 is active when the control bit is 680 * cleared and the divide is bypassed when the bit is set. 681 */ 682 struct st_clk_quadfs_fsynth { 683 struct clk_hw hw; 684 void __iomem *regs_base; 685 spinlock_t *lock; 686 struct clkgen_quadfs_data *data; 687 688 u32 chan; 689 /* 690 * Cached hardware values from set_rate so we can program the 691 * hardware in enable. There are two reasons for this: 692 * 693 * 1. The registers may not be writable until the parent has been 694 * enabled. 695 * 696 * 2. It restores the clock rate when a driver does an enable 697 * on PM restore, after a suspend to RAM has lost the hardware 698 * setup. 699 */ 700 u32 md; 701 u32 pe; 702 u32 sdiv; 703 u32 nsdiv; 704 }; 705 706 #define to_quadfs_fsynth(_hw) \ 707 container_of(_hw, struct st_clk_quadfs_fsynth, hw) 708 709 static void quadfs_fsynth_program_enable(struct st_clk_quadfs_fsynth *fs) 710 { 711 /* 712 * Pulse the program enable register lsb to make the hardware take 713 * notice of the new md/pe values with a glitchless transition. 714 */ 715 CLKGEN_WRITE(fs, en[fs->chan], 1); 716 CLKGEN_WRITE(fs, en[fs->chan], 0); 717 } 718 719 static void quadfs_fsynth_program_rate(struct st_clk_quadfs_fsynth *fs) 720 { 721 unsigned long flags = 0; 722 723 /* 724 * Ensure the md/pe parameters are ignored while we are 725 * reprogramming them so we can get a glitchless change 726 * when fine tuning the speed of a running clock. 727 */ 728 CLKGEN_WRITE(fs, en[fs->chan], 0); 729 730 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); 731 CLKGEN_WRITE(fs, pe[fs->chan], fs->pe); 732 CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv); 733 734 if (fs->lock) 735 spin_lock_irqsave(fs->lock, flags); 736 737 if (fs->data->nsdiv_present) 738 CLKGEN_WRITE(fs, nsdiv[fs->chan], fs->nsdiv); 739 740 if (fs->lock) 741 spin_unlock_irqrestore(fs->lock, flags); 742 } 743 744 static int quadfs_fsynth_enable(struct clk_hw *hw) 745 { 746 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 747 unsigned long flags = 0; 748 749 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); 750 751 quadfs_fsynth_program_rate(fs); 752 753 if (fs->lock) 754 spin_lock_irqsave(fs->lock, flags); 755 756 CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity); 757 758 if (fs->data->nrst_present) 759 CLKGEN_WRITE(fs, nrst[fs->chan], 0); 760 761 if (fs->lock) 762 spin_unlock_irqrestore(fs->lock, flags); 763 764 quadfs_fsynth_program_enable(fs); 765 766 return 0; 767 } 768 769 static void quadfs_fsynth_disable(struct clk_hw *hw) 770 { 771 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 772 unsigned long flags = 0; 773 774 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); 775 776 if (fs->lock) 777 spin_lock_irqsave(fs->lock, flags); 778 779 CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity); 780 781 if (fs->lock) 782 spin_unlock_irqrestore(fs->lock, flags); 783 } 784 785 static int quadfs_fsynth_is_enabled(struct clk_hw *hw) 786 { 787 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 788 u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]); 789 790 pr_debug("%s: %s enable bit = 0x%x\n", 791 __func__, clk_hw_get_name(hw), nsb); 792 793 return fs->data->standby_polarity ? !nsb : !!nsb; 794 } 795 796 #define P15 (uint64_t)(1 << 15) 797 798 static int clk_fs216c65_get_rate(unsigned long input, const struct stm_fs *fs, 799 unsigned long *rate) 800 { 801 uint64_t res; 802 unsigned long ns; 803 unsigned long nd = 8; /* ndiv stuck at 0 => val = 8 */ 804 unsigned long s; 805 long m; 806 807 m = fs->mdiv - 32; 808 s = 1 << (fs->sdiv + 1); 809 ns = (fs->nsdiv ? 1 : 3); 810 811 res = (uint64_t)(s * ns * P15 * (uint64_t)(m + 33)); 812 res = res - (s * ns * fs->pe); 813 *rate = div64_u64(P15 * nd * input * 32, res); 814 815 return 0; 816 } 817 818 static int clk_fs432c65_get_rate(unsigned long input, const struct stm_fs *fs, 819 unsigned long *rate) 820 { 821 uint64_t res; 822 unsigned long nd = 16; /* ndiv value; stuck at 0 (30Mhz input) */ 823 long m; 824 unsigned long sd; 825 unsigned long ns; 826 827 m = fs->mdiv - 32; 828 sd = 1 << (fs->sdiv + 1); 829 ns = (fs->nsdiv ? 1 : 3); 830 831 res = (uint64_t)(sd * ns * P15 * (uint64_t)(m + 33)); 832 res = res - (sd * ns * fs->pe); 833 *rate = div64_u64(P15 * nd * input * 32, res); 834 835 return 0; 836 } 837 838 #define P20 (uint64_t)(1 << 20) 839 840 static int clk_fs660c32_dig_get_rate(unsigned long input, 841 const struct stm_fs *fs, unsigned long *rate) 842 { 843 unsigned long s = (1 << fs->sdiv); 844 unsigned long ns; 845 uint64_t res; 846 847 /* 848 * 'nsdiv' is a register value ('BIN') which is translated 849 * to a decimal value according to following rules. 850 * 851 * nsdiv ns.dec 852 * 0 3 853 * 1 1 854 */ 855 ns = (fs->nsdiv == 1) ? 1 : 3; 856 857 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; 858 *rate = (unsigned long)div64_u64(input * P20 * 32, res); 859 860 return 0; 861 } 862 863 static int quadfs_fsynt_get_hw_value_for_recalc(struct st_clk_quadfs_fsynth *fs, 864 struct stm_fs *params) 865 { 866 /* 867 * Get the initial hardware values for recalc_rate 868 */ 869 params->mdiv = CLKGEN_READ(fs, mdiv[fs->chan]); 870 params->pe = CLKGEN_READ(fs, pe[fs->chan]); 871 params->sdiv = CLKGEN_READ(fs, sdiv[fs->chan]); 872 873 if (fs->data->nsdiv_present) 874 params->nsdiv = CLKGEN_READ(fs, nsdiv[fs->chan]); 875 else 876 params->nsdiv = 1; 877 878 /* 879 * If All are NULL then assume no clock rate is programmed. 880 */ 881 if (!params->mdiv && !params->pe && !params->sdiv) 882 return 1; 883 884 fs->md = params->mdiv; 885 fs->pe = params->pe; 886 fs->sdiv = params->sdiv; 887 fs->nsdiv = params->nsdiv; 888 889 return 0; 890 } 891 892 static long quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate, 893 unsigned long prate, struct stm_fs *params) 894 { 895 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 896 int (*clk_fs_get_rate)(unsigned long , 897 const struct stm_fs *, unsigned long *); 898 struct stm_fs prev_params; 899 unsigned long prev_rate, rate = 0; 900 unsigned long diff_rate, prev_diff_rate = ~0; 901 int index; 902 903 clk_fs_get_rate = fs->data->get_rate; 904 905 for (index = 0; index < fs->data->rtbl_cnt; index++) { 906 prev_rate = rate; 907 908 *params = fs->data->rtbl[index]; 909 prev_params = *params; 910 911 clk_fs_get_rate(prate, &fs->data->rtbl[index], &rate); 912 913 diff_rate = abs(drate - rate); 914 915 if (diff_rate > prev_diff_rate) { 916 rate = prev_rate; 917 *params = prev_params; 918 break; 919 } 920 921 prev_diff_rate = diff_rate; 922 923 if (drate == rate) 924 return rate; 925 } 926 927 928 if (index == fs->data->rtbl_cnt) 929 *params = prev_params; 930 931 return rate; 932 } 933 934 static unsigned long quadfs_recalc_rate(struct clk_hw *hw, 935 unsigned long parent_rate) 936 { 937 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 938 unsigned long rate = 0; 939 struct stm_fs params; 940 int (*clk_fs_get_rate)(unsigned long , 941 const struct stm_fs *, unsigned long *); 942 943 clk_fs_get_rate = fs->data->get_rate; 944 945 if (quadfs_fsynt_get_hw_value_for_recalc(fs, ¶ms)) 946 return 0; 947 948 if (clk_fs_get_rate(parent_rate, ¶ms, &rate)) { 949 pr_err("%s:%s error calculating rate\n", 950 clk_hw_get_name(hw), __func__); 951 } 952 953 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); 954 955 return rate; 956 } 957 958 static long quadfs_round_rate(struct clk_hw *hw, unsigned long rate, 959 unsigned long *prate) 960 { 961 struct stm_fs params; 962 963 rate = quadfs_find_best_rate(hw, rate, *prate, ¶ms); 964 965 pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n", 966 __func__, clk_hw_get_name(hw), 967 rate, (unsigned int)params.sdiv, (unsigned int)params.mdiv, 968 (unsigned int)params.pe, (unsigned int)params.nsdiv); 969 970 return rate; 971 } 972 973 974 static void quadfs_program_and_enable(struct st_clk_quadfs_fsynth *fs, 975 struct stm_fs *params) 976 { 977 fs->md = params->mdiv; 978 fs->pe = params->pe; 979 fs->sdiv = params->sdiv; 980 fs->nsdiv = params->nsdiv; 981 982 /* 983 * In some integrations you can only change the fsynth programming when 984 * the parent entity containing it is enabled. 985 */ 986 quadfs_fsynth_program_rate(fs); 987 quadfs_fsynth_program_enable(fs); 988 } 989 990 static int quadfs_set_rate(struct clk_hw *hw, unsigned long rate, 991 unsigned long parent_rate) 992 { 993 struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw); 994 struct stm_fs params; 995 long hwrate; 996 int uninitialized_var(i); 997 998 if (!rate || !parent_rate) 999 return -EINVAL; 1000 1001 memset(¶ms, 0, sizeof(struct stm_fs)); 1002 1003 hwrate = quadfs_find_best_rate(hw, rate, parent_rate, ¶ms); 1004 if (!hwrate) 1005 return -EINVAL; 1006 1007 quadfs_program_and_enable(fs, ¶ms); 1008 1009 return 0; 1010 } 1011 1012 1013 1014 static const struct clk_ops st_quadfs_ops = { 1015 .enable = quadfs_fsynth_enable, 1016 .disable = quadfs_fsynth_disable, 1017 .is_enabled = quadfs_fsynth_is_enabled, 1018 .round_rate = quadfs_round_rate, 1019 .set_rate = quadfs_set_rate, 1020 .recalc_rate = quadfs_recalc_rate, 1021 }; 1022 1023 static struct clk * __init st_clk_register_quadfs_fsynth( 1024 const char *name, const char *parent_name, 1025 struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan, 1026 spinlock_t *lock) 1027 { 1028 struct st_clk_quadfs_fsynth *fs; 1029 struct clk *clk; 1030 struct clk_init_data init; 1031 1032 /* 1033 * Sanity check required pointers, note that nsdiv3 is optional. 1034 */ 1035 if (WARN_ON(!name || !parent_name)) 1036 return ERR_PTR(-EINVAL); 1037 1038 fs = kzalloc(sizeof(*fs), GFP_KERNEL); 1039 if (!fs) 1040 return ERR_PTR(-ENOMEM); 1041 1042 init.name = name; 1043 init.ops = &st_quadfs_ops; 1044 init.flags = CLK_GET_RATE_NOCACHE | CLK_IS_BASIC; 1045 init.parent_names = &parent_name; 1046 init.num_parents = 1; 1047 1048 fs->data = quadfs; 1049 fs->regs_base = reg; 1050 fs->chan = chan; 1051 fs->lock = lock; 1052 fs->hw.init = &init; 1053 1054 clk = clk_register(NULL, &fs->hw); 1055 1056 if (IS_ERR(clk)) 1057 kfree(fs); 1058 1059 return clk; 1060 } 1061 1062 static const struct of_device_id quadfs_of_match[] = { 1063 { 1064 .compatible = "st,stih416-quadfs216", 1065 .data = &st_fs216c65_416 1066 }, 1067 { 1068 .compatible = "st,stih416-quadfs432", 1069 .data = &st_fs432c65_416 1070 }, 1071 { 1072 .compatible = "st,stih416-quadfs660-E", 1073 .data = &st_fs660c32_E_416 1074 }, 1075 { 1076 .compatible = "st,stih416-quadfs660-F", 1077 .data = &st_fs660c32_F_416 1078 }, 1079 { 1080 .compatible = "st,stih407-quadfs660-C", 1081 .data = &st_fs660c32_C 1082 }, 1083 { 1084 .compatible = "st,stih407-quadfs660-D", 1085 .data = &st_fs660c32_D 1086 }, 1087 {} 1088 }; 1089 1090 static void __init st_of_create_quadfs_fsynths( 1091 struct device_node *np, const char *pll_name, 1092 struct clkgen_quadfs_data *quadfs, void __iomem *reg, 1093 spinlock_t *lock) 1094 { 1095 struct clk_onecell_data *clk_data; 1096 int fschan; 1097 1098 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 1099 if (!clk_data) 1100 return; 1101 1102 clk_data->clk_num = QUADFS_MAX_CHAN; 1103 clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *), 1104 GFP_KERNEL); 1105 1106 if (!clk_data->clks) { 1107 kfree(clk_data); 1108 return; 1109 } 1110 1111 for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) { 1112 struct clk *clk; 1113 const char *clk_name; 1114 1115 if (of_property_read_string_index(np, "clock-output-names", 1116 fschan, &clk_name)) { 1117 break; 1118 } 1119 1120 /* 1121 * If we read an empty clock name then the channel is unused 1122 */ 1123 if (*clk_name == '\0') 1124 continue; 1125 1126 clk = st_clk_register_quadfs_fsynth(clk_name, pll_name, 1127 quadfs, reg, fschan, lock); 1128 1129 /* 1130 * If there was an error registering this clock output, clean 1131 * up and move on to the next one. 1132 */ 1133 if (!IS_ERR(clk)) { 1134 clk_data->clks[fschan] = clk; 1135 pr_debug("%s: parent %s rate %u\n", 1136 __clk_get_name(clk), 1137 __clk_get_name(clk_get_parent(clk)), 1138 (unsigned int)clk_get_rate(clk)); 1139 } 1140 } 1141 1142 of_clk_add_provider(np, of_clk_src_onecell_get, clk_data); 1143 } 1144 1145 static void __init st_of_quadfs_setup(struct device_node *np) 1146 { 1147 const struct of_device_id *match; 1148 struct clk *clk; 1149 const char *pll_name, *clk_parent_name; 1150 void __iomem *reg; 1151 spinlock_t *lock; 1152 1153 match = of_match_node(quadfs_of_match, np); 1154 if (WARN_ON(!match)) 1155 return; 1156 1157 reg = of_iomap(np, 0); 1158 if (!reg) 1159 return; 1160 1161 clk_parent_name = of_clk_get_parent_name(np, 0); 1162 if (!clk_parent_name) 1163 return; 1164 1165 pll_name = kasprintf(GFP_KERNEL, "%s.pll", np->name); 1166 if (!pll_name) 1167 return; 1168 1169 lock = kzalloc(sizeof(*lock), GFP_KERNEL); 1170 if (!lock) 1171 goto err_exit; 1172 1173 spin_lock_init(lock); 1174 1175 clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name, 1176 (struct clkgen_quadfs_data *) match->data, reg, lock); 1177 if (IS_ERR(clk)) 1178 goto err_exit; 1179 else 1180 pr_debug("%s: parent %s rate %u\n", 1181 __clk_get_name(clk), 1182 __clk_get_name(clk_get_parent(clk)), 1183 (unsigned int)clk_get_rate(clk)); 1184 1185 st_of_create_quadfs_fsynths(np, pll_name, 1186 (struct clkgen_quadfs_data *)match->data, 1187 reg, lock); 1188 1189 err_exit: 1190 kfree(pll_name); /* No longer need local copy of the PLL name */ 1191 } 1192 CLK_OF_DECLARE(quadfs, "st,quadfs", st_of_quadfs_setup); 1193