xref: /openbmc/linux/drivers/clk/st/clkgen-fsyn.c (revision b96fc2f3)
1 /*
2  * Copyright (C) 2014 STMicroelectronics R&D Ltd
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  */
9 
10 /*
11  * Authors:
12  * Stephen Gallimore <stephen.gallimore@st.com>,
13  * Pankaj Dev <pankaj.dev@st.com>.
14  */
15 
16 #include <linux/slab.h>
17 #include <linux/of_address.h>
18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
20 
21 #include "clkgen.h"
22 
23 /*
24  * Maximum input clock to the PLL before we divide it down by 2
25  * although in reality in actual systems this has never been seen to
26  * be used.
27  */
28 #define QUADFS_NDIV_THRESHOLD 30000000
29 
30 #define PLL_BW_GOODREF   (0L)
31 #define PLL_BW_VBADREF   (1L)
32 #define PLL_BW_BADREF    (2L)
33 #define PLL_BW_VGOODREF  (3L)
34 
35 #define QUADFS_MAX_CHAN 4
36 
37 struct stm_fs {
38 	unsigned long ndiv;
39 	unsigned long mdiv;
40 	unsigned long pe;
41 	unsigned long sdiv;
42 	unsigned long nsdiv;
43 };
44 
45 static const struct stm_fs fs216c65_rtbl[] = {
46 	{ .mdiv = 0x1f, .pe = 0x0,	.sdiv = 0x7,	.nsdiv = 0 },	/* 312.5 Khz */
47 	{ .mdiv = 0x17, .pe = 0x25ed,	.sdiv = 0x1,	.nsdiv = 0 },	/* 27    MHz */
48 	{ .mdiv = 0x1a, .pe = 0x7b36,	.sdiv = 0x2,	.nsdiv = 1 },	/* 36.87 MHz */
49 	{ .mdiv = 0x13, .pe = 0x0,	.sdiv = 0x2,	.nsdiv = 1 },	/* 48    MHz */
50 	{ .mdiv = 0x11, .pe = 0x1c72,	.sdiv = 0x1,	.nsdiv = 1 },	/* 108   MHz */
51 };
52 
53 static const struct stm_fs fs432c65_rtbl[] = {
54 	{ .mdiv = 0x1f, .pe = 0x0,	.sdiv = 0x7,	.nsdiv = 0 },	/* 625     Khz */
55 	{ .mdiv = 0x13, .pe = 0x777c,	.sdiv = 0x4,	.nsdiv = 1 },	/* 25.175  MHz */
56 	{ .mdiv = 0x19, .pe = 0x4d35,	.sdiv = 0x2,	.nsdiv = 0 },	/* 25.200  MHz */
57 	{ .mdiv = 0x11, .pe = 0x1c72,	.sdiv = 0x4,	.nsdiv = 1 },	/* 27.000  MHz */
58 	{ .mdiv = 0x17, .pe = 0x28f5,	.sdiv = 0x2,	.nsdiv = 0 },	/* 27.027  MHz */
59 	{ .mdiv = 0x16, .pe = 0x3359,	.sdiv = 0x2,	.nsdiv = 0 },	/* 28.320  MHz */
60 	{ .mdiv = 0x1f, .pe = 0x2083,	.sdiv = 0x3,	.nsdiv = 1 },	/* 30.240  MHz */
61 	{ .mdiv = 0x1e, .pe = 0x430d,	.sdiv = 0x3,	.nsdiv = 1 },	/* 31.500  MHz */
62 	{ .mdiv = 0x17, .pe = 0x0,	.sdiv = 0x3,	.nsdiv = 1 },	/* 40.000  MHz */
63 	{ .mdiv = 0x19, .pe = 0x121a,	.sdiv = 0x1,	.nsdiv = 0 },	/* 49.500  MHz */
64 	{ .mdiv = 0x13, .pe = 0x6667,	.sdiv = 0x3,	.nsdiv = 1 },	/* 50.000  MHz */
65 	{ .mdiv = 0x10, .pe = 0x1ee6,	.sdiv = 0x3,	.nsdiv = 1 },	/* 57.284  MHz */
66 	{ .mdiv = 0x1d, .pe = 0x3b14,	.sdiv = 0x2,	.nsdiv = 1 },	/* 65.000  MHz */
67 	{ .mdiv = 0x12, .pe = 0x7c65,	.sdiv = 0x1,	.nsdiv = 0 },	/* 71.000  MHz */
68 	{ .mdiv = 0x19, .pe = 0xecd,	.sdiv = 0x2,	.nsdiv = 1 },	/* 74.176  MHz */
69 	{ .mdiv = 0x19, .pe = 0x121a,	.sdiv = 0x2,	.nsdiv = 1 },	/* 74.250  MHz */
70 	{ .mdiv = 0x19, .pe = 0x3334,	.sdiv = 0x2,	.nsdiv = 1 },	/* 75.000  MHz */
71 	{ .mdiv = 0x18, .pe = 0x5138,	.sdiv = 0x2,	.nsdiv = 1 },	/* 78.800  MHz */
72 	{ .mdiv = 0x1d, .pe = 0x77d,	.sdiv = 0x0,	.nsdiv = 0 },	/* 85.500  MHz */
73 	{ .mdiv = 0x1c, .pe = 0x13d5,	.sdiv = 0x0,	.nsdiv = 0 },	/* 88.750  MHz */
74 	{ .mdiv = 0x11, .pe = 0x1c72,	.sdiv = 0x2,	.nsdiv = 1 },	/* 108.000 MHz */
75 	{ .mdiv = 0x17, .pe = 0x28f5,	.sdiv = 0x0,	.nsdiv = 0 },	/* 108.108 MHz */
76 	{ .mdiv = 0x10, .pe = 0x6e26,	.sdiv = 0x2,	.nsdiv = 1 },	/* 118.963 MHz */
77 	{ .mdiv = 0x15, .pe = 0x3e63,	.sdiv = 0x0,	.nsdiv = 0 },	/* 119.000 MHz */
78 	{ .mdiv = 0x1c, .pe = 0x471d,	.sdiv = 0x1,	.nsdiv = 1 },	/* 135.000 MHz */
79 	{ .mdiv = 0x19, .pe = 0xecd,	.sdiv = 0x1,	.nsdiv = 1 },	/* 148.352 MHz */
80 	{ .mdiv = 0x19, .pe = 0x121a,	.sdiv = 0x1,	.nsdiv = 1 },	/* 148.500 MHz */
81 	{ .mdiv = 0x19, .pe = 0x121a,	.sdiv = 0x0,	.nsdiv = 1 },	/* 297     MHz */
82 };
83 
84 static const struct stm_fs fs660c32_rtbl[] = {
85 	{ .mdiv = 0x14, .pe = 0x376b,	.sdiv = 0x4,	.nsdiv = 1 },	/* 25.175  MHz */
86 	{ .mdiv = 0x14, .pe = 0x30c3,	.sdiv = 0x4,	.nsdiv = 1 },	/* 25.200  MHz */
87 	{ .mdiv = 0x10, .pe = 0x71c7,	.sdiv = 0x4,	.nsdiv = 1 },	/* 27.000  MHz */
88 	{ .mdiv = 0x00, .pe = 0x47af,	.sdiv = 0x3,	.nsdiv = 0 },	/* 27.027  MHz */
89 	{ .mdiv = 0x0e, .pe = 0x4e1a,	.sdiv = 0x4,	.nsdiv = 1 },	/* 28.320  MHz */
90 	{ .mdiv = 0x0b, .pe = 0x534d,	.sdiv = 0x4,	.nsdiv = 1 },	/* 30.240  MHz */
91 	{ .mdiv = 0x17, .pe = 0x6fbf,	.sdiv = 0x2,	.nsdiv = 0 },	/* 31.500  MHz */
92 	{ .mdiv = 0x01, .pe = 0x0,	.sdiv = 0x4,	.nsdiv = 1 },	/* 40.000  MHz */
93 	{ .mdiv = 0x15, .pe = 0x2aab,	.sdiv = 0x3,	.nsdiv = 1 },	/* 49.500  MHz */
94 	{ .mdiv = 0x14, .pe = 0x6666,	.sdiv = 0x3,	.nsdiv = 1 },	/* 50.000  MHz */
95 	{ .mdiv = 0x1d, .pe = 0x395f,	.sdiv = 0x1,	.nsdiv = 0 },	/* 57.284  MHz */
96 	{ .mdiv = 0x08, .pe = 0x4ec5,	.sdiv = 0x3,	.nsdiv = 1 },	/* 65.000  MHz */
97 	{ .mdiv = 0x05, .pe = 0x1770,	.sdiv = 0x3,	.nsdiv = 1 },	/* 71.000  MHz */
98 	{ .mdiv = 0x03, .pe = 0x4ba7,	.sdiv = 0x3,	.nsdiv = 1 },	/* 74.176  MHz */
99 	{ .mdiv = 0x0f, .pe = 0x3426,	.sdiv = 0x1,	.nsdiv = 0 },	/* 74.250  MHz */
100 	{ .mdiv = 0x0e, .pe = 0x7777,	.sdiv = 0x1,	.nsdiv = 0 },	/* 75.000  MHz */
101 	{ .mdiv = 0x01, .pe = 0x4053,	.sdiv = 0x3,	.nsdiv = 1 },	/* 78.800  MHz */
102 	{ .mdiv = 0x09, .pe = 0x15b5,	.sdiv = 0x1,	.nsdiv = 0 },	/* 85.500  MHz */
103 	{ .mdiv = 0x1b, .pe = 0x3f19,	.sdiv = 0x2,	.nsdiv = 1 },	/* 88.750  MHz */
104 	{ .mdiv = 0x10, .pe = 0x71c7,	.sdiv = 0x2,	.nsdiv = 1 },	/* 108.000 MHz */
105 	{ .mdiv = 0x00, .pe = 0x47af,	.sdiv = 0x1,	.nsdiv = 0 },	/* 108.108 MHz */
106 	{ .mdiv = 0x0c, .pe = 0x3118,	.sdiv = 0x2,	.nsdiv = 1 },	/* 118.963 MHz */
107 	{ .mdiv = 0x0c, .pe = 0x2f54,	.sdiv = 0x2,	.nsdiv = 1 },	/* 119.000 MHz */
108 	{ .mdiv = 0x07, .pe = 0xe39,	.sdiv = 0x2,	.nsdiv = 1 },	/* 135.000 MHz */
109 	{ .mdiv = 0x03, .pe = 0x4ba7,	.sdiv = 0x2,	.nsdiv = 1 },	/* 148.352 MHz */
110 	{ .mdiv = 0x0f, .pe = 0x3426,	.sdiv = 0x0,	.nsdiv = 0 },	/* 148.500 MHz */
111 	{ .mdiv = 0x03, .pe = 0x4ba7,	.sdiv = 0x1,	.nsdiv = 1 },	/* 296.704 MHz */
112 	{ .mdiv = 0x03, .pe = 0x471c,	.sdiv = 0x1,	.nsdiv = 1 },	/* 297.000 MHz */
113 	{ .mdiv = 0x00, .pe = 0x295f,	.sdiv = 0x1,	.nsdiv = 1 },	/* 326.700 MHz */
114 	{ .mdiv = 0x1f, .pe = 0x3633,	.sdiv = 0x0,	.nsdiv = 1 },	/* 333.000 MHz */
115 	{ .mdiv = 0x1c, .pe = 0x0,	.sdiv = 0x0,	.nsdiv = 1 },	/* 352.000 Mhz */
116 };
117 
118 struct clkgen_quadfs_data {
119 	bool reset_present;
120 	bool bwfilter_present;
121 	bool lockstatus_present;
122 	bool powerup_polarity;
123 	bool standby_polarity;
124 	bool nsdiv_present;
125 	bool nrst_present;
126 	struct clkgen_field ndiv;
127 	struct clkgen_field ref_bw;
128 	struct clkgen_field nreset;
129 	struct clkgen_field npda;
130 	struct clkgen_field lock_status;
131 
132 	struct clkgen_field nrst[QUADFS_MAX_CHAN];
133 	struct clkgen_field nsb[QUADFS_MAX_CHAN];
134 	struct clkgen_field en[QUADFS_MAX_CHAN];
135 	struct clkgen_field mdiv[QUADFS_MAX_CHAN];
136 	struct clkgen_field pe[QUADFS_MAX_CHAN];
137 	struct clkgen_field sdiv[QUADFS_MAX_CHAN];
138 	struct clkgen_field nsdiv[QUADFS_MAX_CHAN];
139 
140 	const struct clk_ops *pll_ops;
141 	const struct stm_fs *rtbl;
142 	u8 rtbl_cnt;
143 	int  (*get_rate)(unsigned long , const struct stm_fs *,
144 			unsigned long *);
145 };
146 
147 static const struct clk_ops st_quadfs_pll_c65_ops;
148 static const struct clk_ops st_quadfs_pll_c32_ops;
149 static const struct clk_ops st_quadfs_fs216c65_ops;
150 static const struct clk_ops st_quadfs_fs432c65_ops;
151 static const struct clk_ops st_quadfs_fs660c32_ops;
152 
153 static int clk_fs216c65_get_rate(unsigned long, const struct stm_fs *,
154 		unsigned long *);
155 static int clk_fs432c65_get_rate(unsigned long, const struct stm_fs *,
156 		unsigned long *);
157 static int clk_fs660c32_dig_get_rate(unsigned long, const struct stm_fs *,
158 		unsigned long *);
159 /*
160  * Values for all of the standalone instances of this clock
161  * generator found in STiH415 and STiH416 SYSCFG register banks. Note
162  * that the individual channel standby control bits (nsb) are in the
163  * first register along with the PLL control bits.
164  */
165 static const struct clkgen_quadfs_data st_fs216c65_416 = {
166 	/* 416 specific */
167 	.npda	= CLKGEN_FIELD(0x0, 0x1, 14),
168 	.nsb	= { CLKGEN_FIELD(0x0, 0x1, 10),
169 		    CLKGEN_FIELD(0x0, 0x1, 11),
170 		    CLKGEN_FIELD(0x0, 0x1, 12),
171 		    CLKGEN_FIELD(0x0, 0x1, 13) },
172 	.nsdiv_present = true,
173 	.nsdiv	= { CLKGEN_FIELD(0x0, 0x1, 18),
174 		    CLKGEN_FIELD(0x0, 0x1, 19),
175 		    CLKGEN_FIELD(0x0, 0x1, 20),
176 		    CLKGEN_FIELD(0x0, 0x1, 21) },
177 	.mdiv	= { CLKGEN_FIELD(0x4, 0x1f, 0),
178 		    CLKGEN_FIELD(0x14, 0x1f, 0),
179 		    CLKGEN_FIELD(0x24, 0x1f, 0),
180 		    CLKGEN_FIELD(0x34, 0x1f, 0) },
181 	.en	= { CLKGEN_FIELD(0x10, 0x1, 0),
182 		    CLKGEN_FIELD(0x20, 0x1, 0),
183 		    CLKGEN_FIELD(0x30, 0x1, 0),
184 		    CLKGEN_FIELD(0x40, 0x1, 0) },
185 	.ndiv	= CLKGEN_FIELD(0x0, 0x1, 15),
186 	.bwfilter_present = true,
187 	.ref_bw = CLKGEN_FIELD(0x0, 0x3, 16),
188 	.pe	= { CLKGEN_FIELD(0x8, 0xffff, 0),
189 		    CLKGEN_FIELD(0x18, 0xffff, 0),
190 		    CLKGEN_FIELD(0x28, 0xffff, 0),
191 		    CLKGEN_FIELD(0x38, 0xffff, 0) },
192 	.sdiv	= { CLKGEN_FIELD(0xC, 0x7, 0),
193 		    CLKGEN_FIELD(0x1C, 0x7, 0),
194 		    CLKGEN_FIELD(0x2C, 0x7, 0),
195 		    CLKGEN_FIELD(0x3C, 0x7, 0) },
196 	.pll_ops	= &st_quadfs_pll_c65_ops,
197 	.rtbl		= fs216c65_rtbl,
198 	.rtbl_cnt	= ARRAY_SIZE(fs216c65_rtbl),
199 	.get_rate	= clk_fs216c65_get_rate,
200 };
201 
202 static const struct clkgen_quadfs_data st_fs432c65_416 = {
203 	.npda	= CLKGEN_FIELD(0x0, 0x1, 14),
204 	.nsb	= { CLKGEN_FIELD(0x0, 0x1, 10),
205 		    CLKGEN_FIELD(0x0, 0x1, 11),
206 		    CLKGEN_FIELD(0x0, 0x1, 12),
207 		    CLKGEN_FIELD(0x0, 0x1, 13) },
208 	.nsdiv_present = true,
209 	.nsdiv	= { CLKGEN_FIELD(0x0, 0x1, 18),
210 		   CLKGEN_FIELD(0x0, 0x1, 19),
211 		   CLKGEN_FIELD(0x0, 0x1, 20),
212 		   CLKGEN_FIELD(0x0, 0x1, 21) },
213 	.mdiv	= { CLKGEN_FIELD(0x4, 0x1f, 0),
214 		    CLKGEN_FIELD(0x14, 0x1f, 0),
215 		    CLKGEN_FIELD(0x24, 0x1f, 0),
216 		    CLKGEN_FIELD(0x34, 0x1f, 0) },
217 	.en	= { CLKGEN_FIELD(0x10, 0x1, 0),
218 		    CLKGEN_FIELD(0x20, 0x1, 0),
219 		    CLKGEN_FIELD(0x30, 0x1, 0),
220 		    CLKGEN_FIELD(0x40, 0x1, 0) },
221 	.ndiv	= CLKGEN_FIELD(0x0, 0x1, 15),
222 	.bwfilter_present = true,
223 	.ref_bw = CLKGEN_FIELD(0x0, 0x3, 16),
224 	.pe	= { CLKGEN_FIELD(0x8, 0xffff, 0),
225 		    CLKGEN_FIELD(0x18, 0xffff, 0),
226 		    CLKGEN_FIELD(0x28, 0xffff, 0),
227 		    CLKGEN_FIELD(0x38, 0xffff, 0) },
228 	.sdiv	= { CLKGEN_FIELD(0xC, 0x7, 0),
229 		    CLKGEN_FIELD(0x1C, 0x7, 0),
230 		    CLKGEN_FIELD(0x2C, 0x7, 0),
231 		    CLKGEN_FIELD(0x3C, 0x7, 0) },
232 	.pll_ops	= &st_quadfs_pll_c65_ops,
233 	.rtbl		= fs432c65_rtbl,
234 	.rtbl_cnt	= ARRAY_SIZE(fs432c65_rtbl),
235 	.get_rate	= clk_fs432c65_get_rate,
236 };
237 
238 static const struct clkgen_quadfs_data st_fs660c32_E_416 = {
239 	.npda	= CLKGEN_FIELD(0x0, 0x1, 14),
240 	.nsb	= { CLKGEN_FIELD(0x0, 0x1, 10),
241 		    CLKGEN_FIELD(0x0, 0x1, 11),
242 		    CLKGEN_FIELD(0x0, 0x1, 12),
243 		    CLKGEN_FIELD(0x0, 0x1, 13) },
244 	.nsdiv_present = true,
245 	.nsdiv	= { CLKGEN_FIELD(0x0, 0x1, 18),
246 		    CLKGEN_FIELD(0x0, 0x1, 19),
247 		    CLKGEN_FIELD(0x0, 0x1, 20),
248 		    CLKGEN_FIELD(0x0, 0x1, 21) },
249 	.mdiv	= { CLKGEN_FIELD(0x4, 0x1f, 0),
250 		    CLKGEN_FIELD(0x14, 0x1f, 0),
251 		    CLKGEN_FIELD(0x24, 0x1f, 0),
252 		    CLKGEN_FIELD(0x34, 0x1f, 0) },
253 	.en	= { CLKGEN_FIELD(0x10, 0x1, 0),
254 		    CLKGEN_FIELD(0x20, 0x1, 0),
255 		    CLKGEN_FIELD(0x30, 0x1, 0),
256 		    CLKGEN_FIELD(0x40, 0x1, 0) },
257 	.ndiv	= CLKGEN_FIELD(0x0, 0x7, 15),
258 	.pe	= { CLKGEN_FIELD(0x8, 0x7fff, 0),
259 		    CLKGEN_FIELD(0x18, 0x7fff, 0),
260 		    CLKGEN_FIELD(0x28, 0x7fff, 0),
261 		    CLKGEN_FIELD(0x38, 0x7fff, 0) },
262 	.sdiv	= { CLKGEN_FIELD(0xC, 0xf, 0),
263 		    CLKGEN_FIELD(0x1C, 0xf, 0),
264 		    CLKGEN_FIELD(0x2C, 0xf, 0),
265 		    CLKGEN_FIELD(0x3C, 0xf, 0) },
266 	.lockstatus_present = true,
267 	.lock_status = CLKGEN_FIELD(0xAC, 0x1, 0),
268 	.pll_ops	= &st_quadfs_pll_c32_ops,
269 	.rtbl		= fs660c32_rtbl,
270 	.rtbl_cnt	= ARRAY_SIZE(fs660c32_rtbl),
271 	.get_rate	= clk_fs660c32_dig_get_rate,
272 };
273 
274 static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
275 	.npda	= CLKGEN_FIELD(0x0, 0x1, 14),
276 	.nsb	= { CLKGEN_FIELD(0x0, 0x1, 10),
277 		    CLKGEN_FIELD(0x0, 0x1, 11),
278 		    CLKGEN_FIELD(0x0, 0x1, 12),
279 		    CLKGEN_FIELD(0x0, 0x1, 13) },
280 	.nsdiv_present = true,
281 	.nsdiv	= { CLKGEN_FIELD(0x0, 0x1, 18),
282 		    CLKGEN_FIELD(0x0, 0x1, 19),
283 		    CLKGEN_FIELD(0x0, 0x1, 20),
284 		    CLKGEN_FIELD(0x0, 0x1, 21) },
285 	.mdiv	= { CLKGEN_FIELD(0x4, 0x1f, 0),
286 		    CLKGEN_FIELD(0x14, 0x1f, 0),
287 		    CLKGEN_FIELD(0x24, 0x1f, 0),
288 		    CLKGEN_FIELD(0x34, 0x1f, 0) },
289 	.en	= { CLKGEN_FIELD(0x10, 0x1, 0),
290 		    CLKGEN_FIELD(0x20, 0x1, 0),
291 		    CLKGEN_FIELD(0x30, 0x1, 0),
292 		    CLKGEN_FIELD(0x40, 0x1, 0) },
293 	.ndiv	= CLKGEN_FIELD(0x0, 0x7, 15),
294 	.pe	= { CLKGEN_FIELD(0x8, 0x7fff, 0),
295 		    CLKGEN_FIELD(0x18, 0x7fff, 0),
296 		    CLKGEN_FIELD(0x28, 0x7fff, 0),
297 		    CLKGEN_FIELD(0x38, 0x7fff, 0) },
298 	.sdiv	= { CLKGEN_FIELD(0xC, 0xf, 0),
299 		    CLKGEN_FIELD(0x1C, 0xf, 0),
300 		    CLKGEN_FIELD(0x2C, 0xf, 0),
301 		    CLKGEN_FIELD(0x3C, 0xf, 0) },
302 	.lockstatus_present = true,
303 	.lock_status = CLKGEN_FIELD(0xEC, 0x1, 0),
304 	.pll_ops	= &st_quadfs_pll_c32_ops,
305 	.rtbl		= fs660c32_rtbl,
306 	.rtbl_cnt	= ARRAY_SIZE(fs660c32_rtbl),
307 	.get_rate	= clk_fs660c32_dig_get_rate,
308 };
309 
310 static const struct clkgen_quadfs_data st_fs660c32_C = {
311 	.nrst_present = true,
312 	.nrst	= { CLKGEN_FIELD(0x2f0, 0x1, 0),
313 		    CLKGEN_FIELD(0x2f0, 0x1, 1),
314 		    CLKGEN_FIELD(0x2f0, 0x1, 2),
315 		    CLKGEN_FIELD(0x2f0, 0x1, 3) },
316 	.npda	= CLKGEN_FIELD(0x2f0, 0x1, 12),
317 	.nsb	= { CLKGEN_FIELD(0x2f0, 0x1, 8),
318 		    CLKGEN_FIELD(0x2f0, 0x1, 9),
319 		    CLKGEN_FIELD(0x2f0, 0x1, 10),
320 		    CLKGEN_FIELD(0x2f0, 0x1, 11) },
321 	.nsdiv_present = true,
322 	.nsdiv	= { CLKGEN_FIELD(0x304, 0x1, 24),
323 		    CLKGEN_FIELD(0x308, 0x1, 24),
324 		    CLKGEN_FIELD(0x30c, 0x1, 24),
325 		    CLKGEN_FIELD(0x310, 0x1, 24) },
326 	.mdiv	= { CLKGEN_FIELD(0x304, 0x1f, 15),
327 		    CLKGEN_FIELD(0x308, 0x1f, 15),
328 		    CLKGEN_FIELD(0x30c, 0x1f, 15),
329 		    CLKGEN_FIELD(0x310, 0x1f, 15) },
330 	.en	= { CLKGEN_FIELD(0x2fc, 0x1, 0),
331 		    CLKGEN_FIELD(0x2fc, 0x1, 1),
332 		    CLKGEN_FIELD(0x2fc, 0x1, 2),
333 		    CLKGEN_FIELD(0x2fc, 0x1, 3) },
334 	.ndiv	= CLKGEN_FIELD(0x2f4, 0x7, 16),
335 	.pe	= { CLKGEN_FIELD(0x304, 0x7fff, 0),
336 		    CLKGEN_FIELD(0x308, 0x7fff, 0),
337 		    CLKGEN_FIELD(0x30c, 0x7fff, 0),
338 		    CLKGEN_FIELD(0x310, 0x7fff, 0) },
339 	.sdiv	= { CLKGEN_FIELD(0x304, 0xf, 20),
340 		    CLKGEN_FIELD(0x308, 0xf, 20),
341 		    CLKGEN_FIELD(0x30c, 0xf, 20),
342 		    CLKGEN_FIELD(0x310, 0xf, 20) },
343 	.lockstatus_present = true,
344 	.lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
345 	.powerup_polarity = 1,
346 	.standby_polarity = 1,
347 	.pll_ops	= &st_quadfs_pll_c32_ops,
348 	.rtbl		= fs660c32_rtbl,
349 	.rtbl_cnt	= ARRAY_SIZE(fs660c32_rtbl),
350 	.get_rate	= clk_fs660c32_dig_get_rate,
351 };
352 
353 static const struct clkgen_quadfs_data st_fs660c32_D = {
354 	.nrst_present = true,
355 	.nrst	= { CLKGEN_FIELD(0x2a0, 0x1, 0),
356 		    CLKGEN_FIELD(0x2a0, 0x1, 1),
357 		    CLKGEN_FIELD(0x2a0, 0x1, 2),
358 		    CLKGEN_FIELD(0x2a0, 0x1, 3) },
359 	.ndiv	= CLKGEN_FIELD(0x2a4, 0x7, 16),
360 	.pe	= { CLKGEN_FIELD(0x2b4, 0x7fff, 0),
361 		    CLKGEN_FIELD(0x2b8, 0x7fff, 0),
362 		    CLKGEN_FIELD(0x2bc, 0x7fff, 0),
363 		    CLKGEN_FIELD(0x2c0, 0x7fff, 0) },
364 	.sdiv	= { CLKGEN_FIELD(0x2b4, 0xf, 20),
365 		    CLKGEN_FIELD(0x2b8, 0xf, 20),
366 		    CLKGEN_FIELD(0x2bc, 0xf, 20),
367 		    CLKGEN_FIELD(0x2c0, 0xf, 20) },
368 	.npda	= CLKGEN_FIELD(0x2a0, 0x1, 12),
369 	.nsb	= { CLKGEN_FIELD(0x2a0, 0x1, 8),
370 		    CLKGEN_FIELD(0x2a0, 0x1, 9),
371 		    CLKGEN_FIELD(0x2a0, 0x1, 10),
372 		    CLKGEN_FIELD(0x2a0, 0x1, 11) },
373 	.nsdiv_present = true,
374 	.nsdiv	= { CLKGEN_FIELD(0x2b4, 0x1, 24),
375 		    CLKGEN_FIELD(0x2b8, 0x1, 24),
376 		    CLKGEN_FIELD(0x2bc, 0x1, 24),
377 		    CLKGEN_FIELD(0x2c0, 0x1, 24) },
378 	.mdiv	= { CLKGEN_FIELD(0x2b4, 0x1f, 15),
379 		    CLKGEN_FIELD(0x2b8, 0x1f, 15),
380 		    CLKGEN_FIELD(0x2bc, 0x1f, 15),
381 		    CLKGEN_FIELD(0x2c0, 0x1f, 15) },
382 	.en	= { CLKGEN_FIELD(0x2ac, 0x1, 0),
383 		    CLKGEN_FIELD(0x2ac, 0x1, 1),
384 		    CLKGEN_FIELD(0x2ac, 0x1, 2),
385 		    CLKGEN_FIELD(0x2ac, 0x1, 3) },
386 	.lockstatus_present = true,
387 	.lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
388 	.powerup_polarity = 1,
389 	.standby_polarity = 1,
390 	.pll_ops	= &st_quadfs_pll_c32_ops,
391 	.rtbl		= fs660c32_rtbl,
392 	.rtbl_cnt	= ARRAY_SIZE(fs660c32_rtbl),
393 	.get_rate	= clk_fs660c32_dig_get_rate,};
394 
395 /**
396  * DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
397  *
398  * Traits of this clock:
399  * prepare - clk_(un)prepare only ensures parent is (un)prepared
400  * enable - clk_enable and clk_disable are functional & control the Fsyn
401  * rate - inherits rate from parent. set_rate/round_rate/recalc_rate
402  * parent - fixed parent.  No clk_set_parent support
403  */
404 
405 /**
406  * struct st_clk_quadfs_pll - A pll which outputs a fixed multiplier of
407  *                                  its parent clock, found inside a type of
408  *                                  ST quad channel frequency synthesizer block
409  *
410  * @hw: handle between common and hardware-specific interfaces.
411  * @ndiv: regmap field for the ndiv control.
412  * @regs_base: base address of the configuration registers.
413  * @lock: spinlock.
414  *
415  */
416 struct st_clk_quadfs_pll {
417 	struct clk_hw	hw;
418 	void __iomem	*regs_base;
419 	spinlock_t	*lock;
420 	struct clkgen_quadfs_data *data;
421 	u32 ndiv;
422 };
423 
424 #define to_quadfs_pll(_hw) container_of(_hw, struct st_clk_quadfs_pll, hw)
425 
426 static int quadfs_pll_enable(struct clk_hw *hw)
427 {
428 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
429 	unsigned long flags = 0, timeout = jiffies + msecs_to_jiffies(10);
430 
431 	if (pll->lock)
432 		spin_lock_irqsave(pll->lock, flags);
433 
434 	/*
435 	 * Bring block out of reset if we have reset control.
436 	 */
437 	if (pll->data->reset_present)
438 		CLKGEN_WRITE(pll, nreset, 1);
439 
440 	/*
441 	 * Use a fixed input clock noise bandwidth filter for the moment
442 	 */
443 	if (pll->data->bwfilter_present)
444 		CLKGEN_WRITE(pll, ref_bw, PLL_BW_GOODREF);
445 
446 
447 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);
448 
449 	/*
450 	 * Power up the PLL
451 	 */
452 	CLKGEN_WRITE(pll, npda, !pll->data->powerup_polarity);
453 
454 	if (pll->lock)
455 		spin_unlock_irqrestore(pll->lock, flags);
456 
457 	if (pll->data->lockstatus_present)
458 		while (!CLKGEN_READ(pll, lock_status)) {
459 			if (time_after(jiffies, timeout))
460 				return -ETIMEDOUT;
461 			cpu_relax();
462 		}
463 
464 	return 0;
465 }
466 
467 static void quadfs_pll_disable(struct clk_hw *hw)
468 {
469 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
470 	unsigned long flags = 0;
471 
472 	if (pll->lock)
473 		spin_lock_irqsave(pll->lock, flags);
474 
475 	/*
476 	 * Powerdown the PLL and then put block into soft reset if we have
477 	 * reset control.
478 	 */
479 	CLKGEN_WRITE(pll, npda, pll->data->powerup_polarity);
480 
481 	if (pll->data->reset_present)
482 		CLKGEN_WRITE(pll, nreset, 0);
483 
484 	if (pll->lock)
485 		spin_unlock_irqrestore(pll->lock, flags);
486 }
487 
488 static int quadfs_pll_is_enabled(struct clk_hw *hw)
489 {
490 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
491 	u32 npda = CLKGEN_READ(pll, npda);
492 
493 	return pll->data->powerup_polarity ? !npda : !!npda;
494 }
495 
496 static int clk_fs660c32_vco_get_rate(unsigned long input, struct stm_fs *fs,
497 			   unsigned long *rate)
498 {
499 	unsigned long nd = fs->ndiv + 16; /* ndiv value */
500 
501 	*rate = input * nd;
502 
503 	return 0;
504 }
505 
506 static unsigned long quadfs_pll_fs660c32_recalc_rate(struct clk_hw *hw,
507 					unsigned long parent_rate)
508 {
509 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
510 	unsigned long rate = 0;
511 	struct stm_fs params;
512 
513 	params.ndiv = CLKGEN_READ(pll, ndiv);
514 	if (clk_fs660c32_vco_get_rate(parent_rate, &params, &rate))
515 		pr_err("%s:%s error calculating rate\n",
516 		       clk_hw_get_name(hw), __func__);
517 
518 	pll->ndiv = params.ndiv;
519 
520 	return rate;
521 }
522 
523 static int clk_fs660c32_vco_get_params(unsigned long input,
524 				unsigned long output, struct stm_fs *fs)
525 {
526 /* Formula
527    VCO frequency = (fin x ndiv) / pdiv
528    ndiv = VCOfreq * pdiv / fin
529    */
530 	unsigned long pdiv = 1, n;
531 
532 	/* Output clock range: 384Mhz to 660Mhz */
533 	if (output < 384000000 || output > 660000000)
534 		return -EINVAL;
535 
536 	if (input > 40000000)
537 		/* This means that PDIV would be 2 instead of 1.
538 		   Not supported today. */
539 		return -EINVAL;
540 
541 	input /= 1000;
542 	output /= 1000;
543 
544 	n = output * pdiv / input;
545 	if (n < 16)
546 		n = 16;
547 	fs->ndiv = n - 16; /* Converting formula value to reg value */
548 
549 	return 0;
550 }
551 
552 static long quadfs_pll_fs660c32_round_rate(struct clk_hw *hw, unsigned long rate
553 		, unsigned long *prate)
554 {
555 	struct stm_fs params;
556 
557 	if (!clk_fs660c32_vco_get_params(*prate, rate, &params))
558 		clk_fs660c32_vco_get_rate(*prate, &params, &rate);
559 
560 	pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n",
561 		 __func__, clk_hw_get_name(hw),
562 		 rate, (unsigned int)params.sdiv,
563 		 (unsigned int)params.mdiv,
564 		 (unsigned int)params.pe, (unsigned int)params.nsdiv);
565 
566 	return rate;
567 }
568 
569 static int quadfs_pll_fs660c32_set_rate(struct clk_hw *hw, unsigned long rate,
570 				unsigned long parent_rate)
571 {
572 	struct st_clk_quadfs_pll *pll = to_quadfs_pll(hw);
573 	struct stm_fs params;
574 	long hwrate = 0;
575 	unsigned long flags = 0;
576 
577 	if (!rate || !parent_rate)
578 		return -EINVAL;
579 
580 	if (!clk_fs660c32_vco_get_params(parent_rate, rate, &params))
581 		clk_fs660c32_vco_get_rate(parent_rate, &params, &hwrate);
582 
583 	pr_debug("%s: %s new rate %ld [ndiv=0x%x]\n",
584 		 __func__, clk_hw_get_name(hw),
585 		 hwrate, (unsigned int)params.ndiv);
586 
587 	if (!hwrate)
588 		return -EINVAL;
589 
590 	pll->ndiv = params.ndiv;
591 
592 	if (pll->lock)
593 		spin_lock_irqsave(pll->lock, flags);
594 
595 	CLKGEN_WRITE(pll, ndiv, pll->ndiv);
596 
597 	if (pll->lock)
598 		spin_unlock_irqrestore(pll->lock, flags);
599 
600 	return 0;
601 }
602 
603 static const struct clk_ops st_quadfs_pll_c65_ops = {
604 	.enable		= quadfs_pll_enable,
605 	.disable	= quadfs_pll_disable,
606 	.is_enabled	= quadfs_pll_is_enabled,
607 };
608 
609 static const struct clk_ops st_quadfs_pll_c32_ops = {
610 	.enable		= quadfs_pll_enable,
611 	.disable	= quadfs_pll_disable,
612 	.is_enabled	= quadfs_pll_is_enabled,
613 	.recalc_rate	= quadfs_pll_fs660c32_recalc_rate,
614 	.round_rate	= quadfs_pll_fs660c32_round_rate,
615 	.set_rate	= quadfs_pll_fs660c32_set_rate,
616 };
617 
618 static struct clk * __init st_clk_register_quadfs_pll(
619 		const char *name, const char *parent_name,
620 		struct clkgen_quadfs_data *quadfs, void __iomem *reg,
621 		spinlock_t *lock)
622 {
623 	struct st_clk_quadfs_pll *pll;
624 	struct clk *clk;
625 	struct clk_init_data init;
626 
627 	/*
628 	 * Sanity check required pointers.
629 	 */
630 	if (WARN_ON(!name || !parent_name))
631 		return ERR_PTR(-EINVAL);
632 
633 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
634 	if (!pll)
635 		return ERR_PTR(-ENOMEM);
636 
637 	init.name = name;
638 	init.ops = quadfs->pll_ops;
639 	init.flags = CLK_IS_BASIC | CLK_GET_RATE_NOCACHE;
640 	init.parent_names = &parent_name;
641 	init.num_parents = 1;
642 
643 	pll->data = quadfs;
644 	pll->regs_base = reg;
645 	pll->lock = lock;
646 	pll->hw.init = &init;
647 
648 	clk = clk_register(NULL, &pll->hw);
649 
650 	if (IS_ERR(clk))
651 		kfree(pll);
652 
653 	return clk;
654 }
655 
656 /**
657  * DOC: A digital frequency synthesizer
658  *
659  * Traits of this clock:
660  * prepare - clk_(un)prepare only ensures parent is (un)prepared
661  * enable - clk_enable and clk_disable are functional
662  * rate - set rate is functional
663  * parent - fixed parent.  No clk_set_parent support
664  */
665 
666 /**
667  * struct st_clk_quadfs_fsynth - One clock output from a four channel digital
668  *                                  frequency synthesizer (fsynth) block.
669  *
670  * @hw: handle between common and hardware-specific interfaces
671  *
672  * @nsb: regmap field in the output control register for the digital
673  *       standby of this fsynth channel. This control is active low so
674  *       the channel is in standby when the control bit is cleared.
675  *
676  * @nsdiv: regmap field in the output control register for
677  *          for the optional divide by 3 of this fsynth channel. This control
678  *          is active low so the divide by 3 is active when the control bit is
679  *          cleared and the divide is bypassed when the bit is set.
680  */
681 struct st_clk_quadfs_fsynth {
682 	struct clk_hw	hw;
683 	void __iomem	*regs_base;
684 	spinlock_t	*lock;
685 	struct clkgen_quadfs_data *data;
686 
687 	u32 chan;
688 	/*
689 	 * Cached hardware values from set_rate so we can program the
690 	 * hardware in enable. There are two reasons for this:
691 	 *
692 	 *  1. The registers may not be writable until the parent has been
693 	 *     enabled.
694 	 *
695 	 *  2. It restores the clock rate when a driver does an enable
696 	 *     on PM restore, after a suspend to RAM has lost the hardware
697 	 *     setup.
698 	 */
699 	u32 md;
700 	u32 pe;
701 	u32 sdiv;
702 	u32 nsdiv;
703 };
704 
705 #define to_quadfs_fsynth(_hw) \
706 	container_of(_hw, struct st_clk_quadfs_fsynth, hw)
707 
708 static void quadfs_fsynth_program_enable(struct st_clk_quadfs_fsynth *fs)
709 {
710 	/*
711 	 * Pulse the program enable register lsb to make the hardware take
712 	 * notice of the new md/pe values with a glitchless transition.
713 	 */
714 	CLKGEN_WRITE(fs, en[fs->chan], 1);
715 	CLKGEN_WRITE(fs, en[fs->chan], 0);
716 }
717 
718 static void quadfs_fsynth_program_rate(struct st_clk_quadfs_fsynth *fs)
719 {
720 	unsigned long flags = 0;
721 
722 	/*
723 	 * Ensure the md/pe parameters are ignored while we are
724 	 * reprogramming them so we can get a glitchless change
725 	 * when fine tuning the speed of a running clock.
726 	 */
727 	CLKGEN_WRITE(fs, en[fs->chan], 0);
728 
729 	CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md);
730 	CLKGEN_WRITE(fs, pe[fs->chan], fs->pe);
731 	CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv);
732 
733 	if (fs->lock)
734 		spin_lock_irqsave(fs->lock, flags);
735 
736 	if (fs->data->nsdiv_present)
737 		CLKGEN_WRITE(fs, nsdiv[fs->chan], fs->nsdiv);
738 
739 	if (fs->lock)
740 		spin_unlock_irqrestore(fs->lock, flags);
741 }
742 
743 static int quadfs_fsynth_enable(struct clk_hw *hw)
744 {
745 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
746 	unsigned long flags = 0;
747 
748 	pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw));
749 
750 	quadfs_fsynth_program_rate(fs);
751 
752 	if (fs->lock)
753 		spin_lock_irqsave(fs->lock, flags);
754 
755 	CLKGEN_WRITE(fs, nsb[fs->chan], !fs->data->standby_polarity);
756 
757 	if (fs->data->nrst_present)
758 		CLKGEN_WRITE(fs, nrst[fs->chan], 0);
759 
760 	if (fs->lock)
761 		spin_unlock_irqrestore(fs->lock, flags);
762 
763 	quadfs_fsynth_program_enable(fs);
764 
765 	return 0;
766 }
767 
768 static void quadfs_fsynth_disable(struct clk_hw *hw)
769 {
770 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
771 	unsigned long flags = 0;
772 
773 	pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw));
774 
775 	if (fs->lock)
776 		spin_lock_irqsave(fs->lock, flags);
777 
778 	CLKGEN_WRITE(fs, nsb[fs->chan], fs->data->standby_polarity);
779 
780 	if (fs->lock)
781 		spin_unlock_irqrestore(fs->lock, flags);
782 }
783 
784 static int quadfs_fsynth_is_enabled(struct clk_hw *hw)
785 {
786 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
787 	u32 nsb = CLKGEN_READ(fs, nsb[fs->chan]);
788 
789 	pr_debug("%s: %s enable bit = 0x%x\n",
790 		 __func__, clk_hw_get_name(hw), nsb);
791 
792 	return fs->data->standby_polarity ? !nsb : !!nsb;
793 }
794 
795 #define P15			(uint64_t)(1 << 15)
796 
797 static int clk_fs216c65_get_rate(unsigned long input, const struct stm_fs *fs,
798 		unsigned long *rate)
799 {
800 	uint64_t res;
801 	unsigned long ns;
802 	unsigned long nd = 8; /* ndiv stuck at 0 => val = 8 */
803 	unsigned long s;
804 	long m;
805 
806 	m = fs->mdiv - 32;
807 	s = 1 << (fs->sdiv + 1);
808 	ns = (fs->nsdiv ? 1 : 3);
809 
810 	res = (uint64_t)(s * ns * P15 * (uint64_t)(m + 33));
811 	res = res - (s * ns * fs->pe);
812 	*rate = div64_u64(P15 * nd * input * 32, res);
813 
814 	return 0;
815 }
816 
817 static int clk_fs432c65_get_rate(unsigned long input, const struct stm_fs *fs,
818 		unsigned long *rate)
819 {
820 	uint64_t res;
821 	unsigned long nd = 16; /* ndiv value; stuck at 0 (30Mhz input) */
822 	long m;
823 	unsigned long sd;
824 	unsigned long ns;
825 
826 	m = fs->mdiv - 32;
827 	sd = 1 << (fs->sdiv + 1);
828 	ns = (fs->nsdiv ? 1 : 3);
829 
830 	res = (uint64_t)(sd * ns * P15 * (uint64_t)(m + 33));
831 	res = res - (sd * ns * fs->pe);
832 	*rate = div64_u64(P15 * nd * input * 32, res);
833 
834 	return 0;
835 }
836 
837 #define P20		(uint64_t)(1 << 20)
838 
839 static int clk_fs660c32_dig_get_rate(unsigned long input,
840 				const struct stm_fs *fs, unsigned long *rate)
841 {
842 	unsigned long s = (1 << fs->sdiv);
843 	unsigned long ns;
844 	uint64_t res;
845 
846 	/*
847 	 * 'nsdiv' is a register value ('BIN') which is translated
848 	 * to a decimal value according to following rules.
849 	 *
850 	 *     nsdiv      ns.dec
851 	 *       0        3
852 	 *       1        1
853 	 */
854 	ns = (fs->nsdiv == 1) ? 1 : 3;
855 
856 	res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns;
857 	*rate = (unsigned long)div64_u64(input * P20 * 32, res);
858 
859 	return 0;
860 }
861 
862 static int quadfs_fsynt_get_hw_value_for_recalc(struct st_clk_quadfs_fsynth *fs,
863 		struct stm_fs *params)
864 {
865 	/*
866 	 * Get the initial hardware values for recalc_rate
867 	 */
868 	params->mdiv	= CLKGEN_READ(fs, mdiv[fs->chan]);
869 	params->pe	= CLKGEN_READ(fs, pe[fs->chan]);
870 	params->sdiv	= CLKGEN_READ(fs, sdiv[fs->chan]);
871 
872 	if (fs->data->nsdiv_present)
873 		params->nsdiv = CLKGEN_READ(fs, nsdiv[fs->chan]);
874 	else
875 		params->nsdiv = 1;
876 
877 	/*
878 	 * If All are NULL then assume no clock rate is programmed.
879 	 */
880 	if (!params->mdiv && !params->pe && !params->sdiv)
881 		return 1;
882 
883 	fs->md = params->mdiv;
884 	fs->pe = params->pe;
885 	fs->sdiv = params->sdiv;
886 	fs->nsdiv = params->nsdiv;
887 
888 	return 0;
889 }
890 
891 static long quadfs_find_best_rate(struct clk_hw *hw, unsigned long drate,
892 				unsigned long prate, struct stm_fs *params)
893 {
894 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
895 	int (*clk_fs_get_rate)(unsigned long ,
896 				const struct stm_fs *, unsigned long *);
897 	struct stm_fs prev_params;
898 	unsigned long prev_rate, rate = 0;
899 	unsigned long diff_rate, prev_diff_rate = ~0;
900 	int index;
901 
902 	clk_fs_get_rate = fs->data->get_rate;
903 
904 	for (index = 0; index < fs->data->rtbl_cnt; index++) {
905 		prev_rate = rate;
906 
907 		*params = fs->data->rtbl[index];
908 		prev_params = *params;
909 
910 		clk_fs_get_rate(prate, &fs->data->rtbl[index], &rate);
911 
912 		diff_rate = abs(drate - rate);
913 
914 		if (diff_rate > prev_diff_rate) {
915 			rate = prev_rate;
916 			*params = prev_params;
917 			break;
918 		}
919 
920 		prev_diff_rate = diff_rate;
921 
922 		if (drate == rate)
923 			return rate;
924 	}
925 
926 
927 	if (index == fs->data->rtbl_cnt)
928 		*params = prev_params;
929 
930 	return rate;
931 }
932 
933 static unsigned long quadfs_recalc_rate(struct clk_hw *hw,
934 		unsigned long parent_rate)
935 {
936 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
937 	unsigned long rate = 0;
938 	struct stm_fs params;
939 	int (*clk_fs_get_rate)(unsigned long ,
940 				const struct stm_fs *, unsigned long *);
941 
942 	clk_fs_get_rate = fs->data->get_rate;
943 
944 	if (quadfs_fsynt_get_hw_value_for_recalc(fs, &params))
945 		return 0;
946 
947 	if (clk_fs_get_rate(parent_rate, &params, &rate)) {
948 		pr_err("%s:%s error calculating rate\n",
949 		       clk_hw_get_name(hw), __func__);
950 	}
951 
952 	pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate);
953 
954 	return rate;
955 }
956 
957 static long quadfs_round_rate(struct clk_hw *hw, unsigned long rate,
958 				     unsigned long *prate)
959 {
960 	struct stm_fs params;
961 
962 	rate = quadfs_find_best_rate(hw, rate, *prate, &params);
963 
964 	pr_debug("%s: %s new rate %ld [sdiv=0x%x,md=0x%x,pe=0x%x,nsdiv3=%u]\n",
965 		 __func__, clk_hw_get_name(hw),
966 		 rate, (unsigned int)params.sdiv, (unsigned int)params.mdiv,
967 			 (unsigned int)params.pe, (unsigned int)params.nsdiv);
968 
969 	return rate;
970 }
971 
972 
973 static void quadfs_program_and_enable(struct st_clk_quadfs_fsynth *fs,
974 		struct stm_fs *params)
975 {
976 	fs->md = params->mdiv;
977 	fs->pe = params->pe;
978 	fs->sdiv = params->sdiv;
979 	fs->nsdiv = params->nsdiv;
980 
981 	/*
982 	 * In some integrations you can only change the fsynth programming when
983 	 * the parent entity containing it is enabled.
984 	 */
985 	quadfs_fsynth_program_rate(fs);
986 	quadfs_fsynth_program_enable(fs);
987 }
988 
989 static int quadfs_set_rate(struct clk_hw *hw, unsigned long rate,
990 				  unsigned long parent_rate)
991 {
992 	struct st_clk_quadfs_fsynth *fs = to_quadfs_fsynth(hw);
993 	struct stm_fs params;
994 	long hwrate;
995 	int uninitialized_var(i);
996 
997 	if (!rate || !parent_rate)
998 		return -EINVAL;
999 
1000 	memset(&params, 0, sizeof(struct stm_fs));
1001 
1002 	hwrate = quadfs_find_best_rate(hw, rate, parent_rate, &params);
1003 	if (!hwrate)
1004 		return -EINVAL;
1005 
1006 	quadfs_program_and_enable(fs, &params);
1007 
1008 	return 0;
1009 }
1010 
1011 
1012 
1013 static const struct clk_ops st_quadfs_ops = {
1014 	.enable		= quadfs_fsynth_enable,
1015 	.disable	= quadfs_fsynth_disable,
1016 	.is_enabled	= quadfs_fsynth_is_enabled,
1017 	.round_rate	= quadfs_round_rate,
1018 	.set_rate	= quadfs_set_rate,
1019 	.recalc_rate	= quadfs_recalc_rate,
1020 };
1021 
1022 static struct clk * __init st_clk_register_quadfs_fsynth(
1023 		const char *name, const char *parent_name,
1024 		struct clkgen_quadfs_data *quadfs, void __iomem *reg, u32 chan,
1025 		spinlock_t *lock)
1026 {
1027 	struct st_clk_quadfs_fsynth *fs;
1028 	struct clk *clk;
1029 	struct clk_init_data init;
1030 
1031 	/*
1032 	 * Sanity check required pointers, note that nsdiv3 is optional.
1033 	 */
1034 	if (WARN_ON(!name || !parent_name))
1035 		return ERR_PTR(-EINVAL);
1036 
1037 	fs = kzalloc(sizeof(*fs), GFP_KERNEL);
1038 	if (!fs)
1039 		return ERR_PTR(-ENOMEM);
1040 
1041 	init.name = name;
1042 	init.ops = &st_quadfs_ops;
1043 	init.flags = CLK_GET_RATE_NOCACHE | CLK_IS_BASIC;
1044 	init.parent_names = &parent_name;
1045 	init.num_parents = 1;
1046 
1047 	fs->data = quadfs;
1048 	fs->regs_base = reg;
1049 	fs->chan = chan;
1050 	fs->lock = lock;
1051 	fs->hw.init = &init;
1052 
1053 	clk = clk_register(NULL, &fs->hw);
1054 
1055 	if (IS_ERR(clk))
1056 		kfree(fs);
1057 
1058 	return clk;
1059 }
1060 
1061 static const struct of_device_id quadfs_of_match[] = {
1062 	{
1063 		.compatible = "st,stih416-quadfs216",
1064 		.data = &st_fs216c65_416
1065 	},
1066 	{
1067 		.compatible = "st,stih416-quadfs432",
1068 		.data = &st_fs432c65_416
1069 	},
1070 	{
1071 		.compatible = "st,stih416-quadfs660-E",
1072 		.data = &st_fs660c32_E_416
1073 	},
1074 	{
1075 		.compatible = "st,stih416-quadfs660-F",
1076 		.data = &st_fs660c32_F_416
1077 	},
1078 	{
1079 		.compatible = "st,stih407-quadfs660-C",
1080 		.data = &st_fs660c32_C
1081 	},
1082 	{
1083 		.compatible = "st,stih407-quadfs660-D",
1084 		.data = &st_fs660c32_D
1085 	},
1086 	{}
1087 };
1088 
1089 static void __init st_of_create_quadfs_fsynths(
1090 		struct device_node *np, const char *pll_name,
1091 		struct clkgen_quadfs_data *quadfs, void __iomem *reg,
1092 		spinlock_t *lock)
1093 {
1094 	struct clk_onecell_data *clk_data;
1095 	int fschan;
1096 
1097 	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
1098 	if (!clk_data)
1099 		return;
1100 
1101 	clk_data->clk_num = QUADFS_MAX_CHAN;
1102 	clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *),
1103 				 GFP_KERNEL);
1104 
1105 	if (!clk_data->clks) {
1106 		kfree(clk_data);
1107 		return;
1108 	}
1109 
1110 	for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) {
1111 		struct clk *clk;
1112 		const char *clk_name;
1113 
1114 		if (of_property_read_string_index(np, "clock-output-names",
1115 						  fschan, &clk_name)) {
1116 			break;
1117 		}
1118 
1119 		/*
1120 		 * If we read an empty clock name then the channel is unused
1121 		 */
1122 		if (*clk_name == '\0')
1123 			continue;
1124 
1125 		clk = st_clk_register_quadfs_fsynth(clk_name, pll_name,
1126 				quadfs, reg, fschan, lock);
1127 
1128 		/*
1129 		 * If there was an error registering this clock output, clean
1130 		 * up and move on to the next one.
1131 		 */
1132 		if (!IS_ERR(clk)) {
1133 			clk_data->clks[fschan] = clk;
1134 			pr_debug("%s: parent %s rate %u\n",
1135 				__clk_get_name(clk),
1136 				__clk_get_name(clk_get_parent(clk)),
1137 				(unsigned int)clk_get_rate(clk));
1138 		}
1139 	}
1140 
1141 	of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
1142 }
1143 
1144 static void __init st_of_quadfs_setup(struct device_node *np)
1145 {
1146 	const struct of_device_id *match;
1147 	struct clk *clk;
1148 	const char *pll_name, *clk_parent_name;
1149 	void __iomem *reg;
1150 	spinlock_t *lock;
1151 
1152 	match = of_match_node(quadfs_of_match, np);
1153 	if (WARN_ON(!match))
1154 		return;
1155 
1156 	reg = of_iomap(np, 0);
1157 	if (!reg)
1158 		return;
1159 
1160 	clk_parent_name = of_clk_get_parent_name(np, 0);
1161 	if (!clk_parent_name)
1162 		return;
1163 
1164 	pll_name = kasprintf(GFP_KERNEL, "%s.pll", np->name);
1165 	if (!pll_name)
1166 		return;
1167 
1168 	lock = kzalloc(sizeof(*lock), GFP_KERNEL);
1169 	if (!lock)
1170 		goto err_exit;
1171 
1172 	spin_lock_init(lock);
1173 
1174 	clk = st_clk_register_quadfs_pll(pll_name, clk_parent_name,
1175 			(struct clkgen_quadfs_data *) match->data, reg, lock);
1176 	if (IS_ERR(clk))
1177 		goto err_exit;
1178 	else
1179 		pr_debug("%s: parent %s rate %u\n",
1180 			__clk_get_name(clk),
1181 			__clk_get_name(clk_get_parent(clk)),
1182 			(unsigned int)clk_get_rate(clk));
1183 
1184 	st_of_create_quadfs_fsynths(np, pll_name,
1185 				    (struct clkgen_quadfs_data *)match->data,
1186 				    reg, lock);
1187 
1188 err_exit:
1189 	kfree(pll_name); /* No longer need local copy of the PLL name */
1190 }
1191 CLK_OF_DECLARE(quadfs, "st,quadfs", st_of_quadfs_setup);
1192