1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Spreatrum SC9860 clock driver 4 // 5 // Copyright (C) 2017 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com> 7 8 #include <linux/clk-provider.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 16 #include <dt-bindings/clock/sprd,sc9860-clk.h> 17 18 #include "common.h" 19 #include "composite.h" 20 #include "div.h" 21 #include "gate.h" 22 #include "mux.h" 23 #include "pll.h" 24 25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m", 26 6, 1, 0); 27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m", 28 13, 1, 0); 29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m", 30 26, 1, 0); 31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m", 32 104, 1, 0); 33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m", 34 1, 1, 0); 35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m", 36 1, 1, 0); 37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m", 38 4, 1, 0); 39 static CLK_FIXED_FACTOR(fac_rco_4m, "rco-4m", "ext-rc0-100m", 40 25, 1, 0); 41 static CLK_FIXED_FACTOR(fac_rco_2m, "rco-2m", "ext-rc0-100m", 42 50, 1, 0); 43 static CLK_FIXED_FACTOR(fac_3k2, "fac-3k2", "ext-32k", 44 10, 1, 0); 45 static CLK_FIXED_FACTOR(fac_1k, "fac-1k", "ext-32k", 46 32, 1, 0); 47 48 static SPRD_SC_GATE_CLK(mpll0_gate, "mpll0-gate", "ext-26m", 0xb0, 49 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 50 static SPRD_SC_GATE_CLK(mpll1_gate, "mpll1-gate", "ext-26m", 0xb0, 51 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 52 static SPRD_SC_GATE_CLK(dpll0_gate, "dpll0-gate", "ext-26m", 0xb4, 53 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 54 static SPRD_SC_GATE_CLK(dpll1_gate, "dpll1-gate", "ext-26m", 0xb4, 55 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 56 static SPRD_SC_GATE_CLK(ltepll0_gate, "ltepll0-gate", "ext-26m", 0xb8, 57 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 58 static SPRD_SC_GATE_CLK(twpll_gate, "twpll-gate", "ext-26m", 0xbc, 59 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 60 static SPRD_SC_GATE_CLK(ltepll1_gate, "ltepll1-gate", "ext-26m", 0x10c, 61 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 62 static SPRD_SC_GATE_CLK(rpll0_gate, "rpll0-gate", "ext-26m", 0x16c, 63 0x1000, BIT(2), 0, 0); 64 static SPRD_SC_GATE_CLK(rpll1_gate, "rpll1-gate", "ext-26m", 0x16c, 65 0x1000, BIT(18), 0, 0); 66 static SPRD_SC_GATE_CLK(cppll_gate, "cppll-gate", "ext-26m", 0x2b4, 67 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 68 static SPRD_SC_GATE_CLK(gpll_gate, "gpll-gate", "ext-26m", 0x32c, 69 0x1000, BIT(0), CLK_IGNORE_UNUSED, CLK_GATE_SET_TO_DISABLE); 70 71 static struct sprd_clk_common *sc9860_pmu_gate_clks[] = { 72 /* address base is 0x402b0000 */ 73 &mpll0_gate.common, 74 &mpll1_gate.common, 75 &dpll0_gate.common, 76 &dpll1_gate.common, 77 <epll0_gate.common, 78 &twpll_gate.common, 79 <epll1_gate.common, 80 &rpll0_gate.common, 81 &rpll1_gate.common, 82 &cppll_gate.common, 83 &gpll_gate.common, 84 }; 85 86 static struct clk_hw_onecell_data sc9860_pmu_gate_hws = { 87 .hws = { 88 [CLK_FAC_4M] = &fac_4m.hw, 89 [CLK_FAC_2M] = &fac_2m.hw, 90 [CLK_FAC_1M] = &fac_1m.hw, 91 [CLK_FAC_250K] = &fac_250k.hw, 92 [CLK_FAC_RPLL0_26M] = &fac_rpll0_26m.hw, 93 [CLK_FAC_RPLL1_26M] = &fac_rpll1_26m.hw, 94 [CLK_FAC_RCO25M] = &fac_rco_25m.hw, 95 [CLK_FAC_RCO4M] = &fac_rco_4m.hw, 96 [CLK_FAC_RCO2M] = &fac_rco_2m.hw, 97 [CLK_FAC_3K2] = &fac_3k2.hw, 98 [CLK_FAC_1K] = &fac_1k.hw, 99 [CLK_MPLL0_GATE] = &mpll0_gate.common.hw, 100 [CLK_MPLL1_GATE] = &mpll1_gate.common.hw, 101 [CLK_DPLL0_GATE] = &dpll0_gate.common.hw, 102 [CLK_DPLL1_GATE] = &dpll1_gate.common.hw, 103 [CLK_LTEPLL0_GATE] = <epll0_gate.common.hw, 104 [CLK_TWPLL_GATE] = &twpll_gate.common.hw, 105 [CLK_LTEPLL1_GATE] = <epll1_gate.common.hw, 106 [CLK_RPLL0_GATE] = &rpll0_gate.common.hw, 107 [CLK_RPLL1_GATE] = &rpll1_gate.common.hw, 108 [CLK_CPPLL_GATE] = &cppll_gate.common.hw, 109 [CLK_GPLL_GATE] = &gpll_gate.common.hw, 110 }, 111 .num = CLK_PMU_GATE_NUM, 112 }; 113 114 static const struct sprd_clk_desc sc9860_pmu_gate_desc = { 115 .clk_clks = sc9860_pmu_gate_clks, 116 .num_clk_clks = ARRAY_SIZE(sc9860_pmu_gate_clks), 117 .hw_clks = &sc9860_pmu_gate_hws, 118 }; 119 120 /* GPLL/LPLL/DPLL/RPLL/CPLL */ 121 static const u64 itable1[4] = {3, 780000000, 988000000, 1196000000}; 122 123 /* TWPLL/MPLL0/MPLL1 */ 124 static const u64 itable2[4] = {3, 1638000000, 2080000000, 2600000000UL}; 125 126 static const struct clk_bit_field f_mpll0[PLL_FACT_MAX] = { 127 { .shift = 20, .width = 1 }, /* lock_done */ 128 { .shift = 19, .width = 1 }, /* div_s */ 129 { .shift = 18, .width = 1 }, /* mod_en */ 130 { .shift = 17, .width = 1 }, /* sdm_en */ 131 { .shift = 0, .width = 0 }, /* refin */ 132 { .shift = 11, .width = 2 }, /* ibias */ 133 { .shift = 0, .width = 7 }, /* n */ 134 { .shift = 57, .width = 7 }, /* nint */ 135 { .shift = 32, .width = 23}, /* kint */ 136 { .shift = 0, .width = 0 }, /* prediv */ 137 { .shift = 56, .width = 1 }, /* postdiv */ 138 }; 139 static SPRD_PLL_WITH_ITABLE_K_FVCO(mpll0_clk, "mpll0", "mpll0-gate", 0x24, 140 2, itable2, f_mpll0, 200, 141 1000, 1000, 1, 1300000000); 142 143 static const struct clk_bit_field f_mpll1[PLL_FACT_MAX] = { 144 { .shift = 20, .width = 1 }, /* lock_done */ 145 { .shift = 19, .width = 1 }, /* div_s */ 146 { .shift = 18, .width = 1 }, /* mod_en */ 147 { .shift = 17, .width = 1 }, /* sdm_en */ 148 { .shift = 0, .width = 0 }, /* refin */ 149 { .shift = 11, .width = 2 }, /* ibias */ 150 { .shift = 0, .width = 7 }, /* n */ 151 { .shift = 57, .width = 7 }, /* nint */ 152 { .shift = 32, .width = 23}, /* kint */ 153 { .shift = 56, .width = 1 }, /* prediv */ 154 { .shift = 0, .width = 0 }, /* postdiv */ 155 }; 156 static SPRD_PLL_WITH_ITABLE_1K(mpll1_clk, "mpll1", "mpll1-gate", 0x2c, 157 2, itable2, f_mpll1, 200); 158 159 static const struct clk_bit_field f_dpll[PLL_FACT_MAX] = { 160 { .shift = 16, .width = 1 }, /* lock_done */ 161 { .shift = 15, .width = 1 }, /* div_s */ 162 { .shift = 14, .width = 1 }, /* mod_en */ 163 { .shift = 13, .width = 1 }, /* sdm_en */ 164 { .shift = 0, .width = 0 }, /* refin */ 165 { .shift = 8, .width = 2 }, /* ibias */ 166 { .shift = 0, .width = 7 }, /* n */ 167 { .shift = 57, .width = 7 }, /* nint */ 168 { .shift = 32, .width = 23}, /* kint */ 169 { .shift = 0, .width = 0 }, /* prediv */ 170 { .shift = 0, .width = 0 }, /* postdiv */ 171 }; 172 static SPRD_PLL_WITH_ITABLE_1K(dpll0_clk, "dpll0", "dpll0-gate", 0x34, 173 2, itable1, f_dpll, 200); 174 175 static SPRD_PLL_WITH_ITABLE_1K(dpll1_clk, "dpll1", "dpll1-gate", 0x3c, 176 2, itable1, f_dpll, 200); 177 178 static const struct clk_bit_field f_rpll[PLL_FACT_MAX] = { 179 { .shift = 0, .width = 1 }, /* lock_done */ 180 { .shift = 3, .width = 1 }, /* div_s */ 181 { .shift = 80, .width = 1 }, /* mod_en */ 182 { .shift = 81, .width = 1 }, /* sdm_en */ 183 { .shift = 0, .width = 0 }, /* refin */ 184 { .shift = 14, .width = 2 }, /* ibias */ 185 { .shift = 16, .width = 7 }, /* n */ 186 { .shift = 4, .width = 7 }, /* nint */ 187 { .shift = 32, .width = 23}, /* kint */ 188 { .shift = 0, .width = 0 }, /* prediv */ 189 { .shift = 0, .width = 0 }, /* postdiv */ 190 }; 191 static SPRD_PLL_WITH_ITABLE_1K(rpll0_clk, "rpll0", "rpll0-gate", 0x44, 192 3, itable1, f_rpll, 200); 193 194 static SPRD_PLL_WITH_ITABLE_1K(rpll1_clk, "rpll1", "rpll1-gate", 0x50, 195 3, itable1, f_rpll, 200); 196 197 static const struct clk_bit_field f_twpll[PLL_FACT_MAX] = { 198 { .shift = 21, .width = 1 }, /* lock_done */ 199 { .shift = 20, .width = 1 }, /* div_s */ 200 { .shift = 19, .width = 1 }, /* mod_en */ 201 { .shift = 18, .width = 1 }, /* sdm_en */ 202 { .shift = 0, .width = 0 }, /* refin */ 203 { .shift = 13, .width = 2 }, /* ibias */ 204 { .shift = 0, .width = 7 }, /* n */ 205 { .shift = 57, .width = 7 }, /* nint */ 206 { .shift = 32, .width = 23}, /* kint */ 207 { .shift = 0, .width = 0 }, /* prediv */ 208 { .shift = 0, .width = 0 }, /* postdiv */ 209 }; 210 static SPRD_PLL_WITH_ITABLE_1K(twpll_clk, "twpll", "twpll-gate", 0x5c, 211 2, itable2, f_twpll, 200); 212 213 static const struct clk_bit_field f_ltepll[PLL_FACT_MAX] = { 214 { .shift = 31, .width = 1 }, /* lock_done */ 215 { .shift = 27, .width = 1 }, /* div_s */ 216 { .shift = 26, .width = 1 }, /* mod_en */ 217 { .shift = 25, .width = 1 }, /* sdm_en */ 218 { .shift = 0, .width = 0 }, /* refin */ 219 { .shift = 20, .width = 2 }, /* ibias */ 220 { .shift = 0, .width = 7 }, /* n */ 221 { .shift = 57, .width = 7 }, /* nint */ 222 { .shift = 32, .width = 23}, /* kint */ 223 { .shift = 0, .width = 0 }, /* prediv */ 224 { .shift = 0, .width = 0 }, /* postdiv */ 225 }; 226 static SPRD_PLL_WITH_ITABLE_1K(ltepll0_clk, "ltepll0", "ltepll0-gate", 227 0x64, 2, itable1, 228 f_ltepll, 200); 229 static SPRD_PLL_WITH_ITABLE_1K(ltepll1_clk, "ltepll1", "ltepll1-gate", 230 0x6c, 2, itable1, 231 f_ltepll, 200); 232 233 static const struct clk_bit_field f_gpll[PLL_FACT_MAX] = { 234 { .shift = 18, .width = 1 }, /* lock_done */ 235 { .shift = 15, .width = 1 }, /* div_s */ 236 { .shift = 14, .width = 1 }, /* mod_en */ 237 { .shift = 13, .width = 1 }, /* sdm_en */ 238 { .shift = 0, .width = 0 }, /* refin */ 239 { .shift = 8, .width = 2 }, /* ibias */ 240 { .shift = 0, .width = 7 }, /* n */ 241 { .shift = 57, .width = 7 }, /* nint */ 242 { .shift = 32, .width = 23}, /* kint */ 243 { .shift = 0, .width = 0 }, /* prediv */ 244 { .shift = 17, .width = 1 }, /* postdiv */ 245 }; 246 static SPRD_PLL_WITH_ITABLE_K_FVCO(gpll_clk, "gpll", "gpll-gate", 0x9c, 247 2, itable1, f_gpll, 200, 248 1000, 1000, 1, 600000000); 249 250 static const struct clk_bit_field f_cppll[PLL_FACT_MAX] = { 251 { .shift = 17, .width = 1 }, /* lock_done */ 252 { .shift = 15, .width = 1 }, /* div_s */ 253 { .shift = 14, .width = 1 }, /* mod_en */ 254 { .shift = 13, .width = 1 }, /* sdm_en */ 255 { .shift = 0, .width = 0 }, /* refin */ 256 { .shift = 8, .width = 2 }, /* ibias */ 257 { .shift = 0, .width = 7 }, /* n */ 258 { .shift = 57, .width = 7 }, /* nint */ 259 { .shift = 32, .width = 23}, /* kint */ 260 { .shift = 0, .width = 0 }, /* prediv */ 261 { .shift = 0, .width = 0 }, /* postdiv */ 262 }; 263 static SPRD_PLL_WITH_ITABLE_1K(cppll_clk, "cppll", "cppll-gate", 0xc4, 264 2, itable1, f_cppll, 200); 265 266 static CLK_FIXED_FACTOR(gpll_42m5, "gpll-42m5", "gpll", 20, 1, 0); 267 static CLK_FIXED_FACTOR(twpll_768m, "twpll-768m", "twpll", 2, 1, 0); 268 static CLK_FIXED_FACTOR(twpll_384m, "twpll-384m", "twpll", 4, 1, 0); 269 static CLK_FIXED_FACTOR(twpll_192m, "twpll-192m", "twpll", 8, 1, 0); 270 static CLK_FIXED_FACTOR(twpll_96m, "twpll-96m", "twpll", 16, 1, 0); 271 static CLK_FIXED_FACTOR(twpll_48m, "twpll-48m", "twpll", 32, 1, 0); 272 static CLK_FIXED_FACTOR(twpll_24m, "twpll-24m", "twpll", 64, 1, 0); 273 static CLK_FIXED_FACTOR(twpll_12m, "twpll-12m", "twpll", 128, 1, 0); 274 static CLK_FIXED_FACTOR(twpll_512m, "twpll-512m", "twpll", 3, 1, 0); 275 static CLK_FIXED_FACTOR(twpll_256m, "twpll-256m", "twpll", 6, 1, 0); 276 static CLK_FIXED_FACTOR(twpll_128m, "twpll-128m", "twpll", 12, 1, 0); 277 static CLK_FIXED_FACTOR(twpll_64m, "twpll-64m", "twpll", 24, 1, 0); 278 static CLK_FIXED_FACTOR(twpll_307m2, "twpll-307m2", "twpll", 5, 1, 0); 279 static CLK_FIXED_FACTOR(twpll_153m6, "twpll-153m6", "twpll", 10, 1, 0); 280 static CLK_FIXED_FACTOR(twpll_76m8, "twpll-76m8", "twpll", 20, 1, 0); 281 static CLK_FIXED_FACTOR(twpll_51m2, "twpll-51m2", "twpll", 30, 1, 0); 282 static CLK_FIXED_FACTOR(twpll_38m4, "twpll-38m4", "twpll", 40, 1, 0); 283 static CLK_FIXED_FACTOR(twpll_19m2, "twpll-19m2", "twpll", 80, 1, 0); 284 static CLK_FIXED_FACTOR(l0_614m4, "l0-614m4", "ltepll0", 2, 1, 0); 285 static CLK_FIXED_FACTOR(l0_409m6, "l0-409m6", "ltepll0", 3, 1, 0); 286 static CLK_FIXED_FACTOR(l0_38m, "l0-38m", "ltepll0", 32, 1, 0); 287 static CLK_FIXED_FACTOR(l1_38m, "l1-38m", "ltepll1", 32, 1, 0); 288 static CLK_FIXED_FACTOR(rpll0_192m, "rpll0-192m", "rpll0", 6, 1, 0); 289 static CLK_FIXED_FACTOR(rpll0_96m, "rpll0-96m", "rpll0", 12, 1, 0); 290 static CLK_FIXED_FACTOR(rpll0_48m, "rpll0-48m", "rpll0", 24, 1, 0); 291 static CLK_FIXED_FACTOR(rpll1_468m, "rpll1-468m", "rpll1", 2, 1, 0); 292 static CLK_FIXED_FACTOR(rpll1_192m, "rpll1-192m", "rpll1", 6, 1, 0); 293 static CLK_FIXED_FACTOR(rpll1_96m, "rpll1-96m", "rpll1", 12, 1, 0); 294 static CLK_FIXED_FACTOR(rpll1_64m, "rpll1-64m", "rpll1", 18, 1, 0); 295 static CLK_FIXED_FACTOR(rpll1_48m, "rpll1-48m", "rpll1", 24, 1, 0); 296 static CLK_FIXED_FACTOR(dpll0_50m, "dpll0-50m", "dpll0", 16, 1, 0); 297 static CLK_FIXED_FACTOR(dpll1_50m, "dpll1-50m", "dpll1", 16, 1, 0); 298 static CLK_FIXED_FACTOR(cppll_50m, "cppll-50m", "cppll", 18, 1, 0); 299 static CLK_FIXED_FACTOR(m0_39m, "m0-39m", "mpll0", 32, 1, 0); 300 static CLK_FIXED_FACTOR(m1_63m, "m1-63m", "mpll1", 32, 1, 0); 301 302 static struct sprd_clk_common *sc9860_pll_clks[] = { 303 /* address base is 0x40400000 */ 304 &mpll0_clk.common, 305 &mpll1_clk.common, 306 &dpll0_clk.common, 307 &dpll1_clk.common, 308 &rpll0_clk.common, 309 &rpll1_clk.common, 310 &twpll_clk.common, 311 <epll0_clk.common, 312 <epll1_clk.common, 313 &gpll_clk.common, 314 &cppll_clk.common, 315 }; 316 317 static struct clk_hw_onecell_data sc9860_pll_hws = { 318 .hws = { 319 [CLK_MPLL0] = &mpll0_clk.common.hw, 320 [CLK_MPLL1] = &mpll1_clk.common.hw, 321 [CLK_DPLL0] = &dpll0_clk.common.hw, 322 [CLK_DPLL1] = &dpll1_clk.common.hw, 323 [CLK_RPLL0] = &rpll0_clk.common.hw, 324 [CLK_RPLL1] = &rpll1_clk.common.hw, 325 [CLK_TWPLL] = &twpll_clk.common.hw, 326 [CLK_LTEPLL0] = <epll0_clk.common.hw, 327 [CLK_LTEPLL1] = <epll1_clk.common.hw, 328 [CLK_GPLL] = &gpll_clk.common.hw, 329 [CLK_CPPLL] = &cppll_clk.common.hw, 330 [CLK_GPLL_42M5] = &gpll_42m5.hw, 331 [CLK_TWPLL_768M] = &twpll_768m.hw, 332 [CLK_TWPLL_384M] = &twpll_384m.hw, 333 [CLK_TWPLL_192M] = &twpll_192m.hw, 334 [CLK_TWPLL_96M] = &twpll_96m.hw, 335 [CLK_TWPLL_48M] = &twpll_48m.hw, 336 [CLK_TWPLL_24M] = &twpll_24m.hw, 337 [CLK_TWPLL_12M] = &twpll_12m.hw, 338 [CLK_TWPLL_512M] = &twpll_512m.hw, 339 [CLK_TWPLL_256M] = &twpll_256m.hw, 340 [CLK_TWPLL_128M] = &twpll_128m.hw, 341 [CLK_TWPLL_64M] = &twpll_64m.hw, 342 [CLK_TWPLL_307M2] = &twpll_307m2.hw, 343 [CLK_TWPLL_153M6] = &twpll_153m6.hw, 344 [CLK_TWPLL_76M8] = &twpll_76m8.hw, 345 [CLK_TWPLL_51M2] = &twpll_51m2.hw, 346 [CLK_TWPLL_38M4] = &twpll_38m4.hw, 347 [CLK_TWPLL_19M2] = &twpll_19m2.hw, 348 [CLK_L0_614M4] = &l0_614m4.hw, 349 [CLK_L0_409M6] = &l0_409m6.hw, 350 [CLK_L0_38M] = &l0_38m.hw, 351 [CLK_L1_38M] = &l1_38m.hw, 352 [CLK_RPLL0_192M] = &rpll0_192m.hw, 353 [CLK_RPLL0_96M] = &rpll0_96m.hw, 354 [CLK_RPLL0_48M] = &rpll0_48m.hw, 355 [CLK_RPLL1_468M] = &rpll1_468m.hw, 356 [CLK_RPLL1_192M] = &rpll1_192m.hw, 357 [CLK_RPLL1_96M] = &rpll1_96m.hw, 358 [CLK_RPLL1_64M] = &rpll1_64m.hw, 359 [CLK_RPLL1_48M] = &rpll1_48m.hw, 360 [CLK_DPLL0_50M] = &dpll0_50m.hw, 361 [CLK_DPLL1_50M] = &dpll1_50m.hw, 362 [CLK_CPPLL_50M] = &cppll_50m.hw, 363 [CLK_M0_39M] = &m0_39m.hw, 364 [CLK_M1_63M] = &m1_63m.hw, 365 }, 366 .num = CLK_PLL_NUM, 367 }; 368 369 static const struct sprd_clk_desc sc9860_pll_desc = { 370 .clk_clks = sc9860_pll_clks, 371 .num_clk_clks = ARRAY_SIZE(sc9860_pll_clks), 372 .hw_clks = &sc9860_pll_hws, 373 }; 374 375 #define SC9860_MUX_FLAG \ 376 (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT) 377 378 static const char * const ap_apb_parents[] = { "ext-26m", "twpll-64m", 379 "twpll-96m", "twpll-128m" }; 380 static SPRD_MUX_CLK(ap_apb, "ap-apb", ap_apb_parents, 381 0x20, 0, 1, SC9860_MUX_FLAG); 382 383 static const char * const ap_apb_usb3[] = { "ext-32k", "twpll-24m" }; 384 static SPRD_MUX_CLK(ap_usb3, "ap-usb3", ap_apb_usb3, 385 0x2c, 0, 1, SC9860_MUX_FLAG); 386 387 static const char * const uart_parents[] = { "ext-26m", "twpll-48m", 388 "twpll-51m2", "twpll-96m" }; 389 static SPRD_COMP_CLK(uart0_clk, "uart0", uart_parents, 0x30, 390 0, 2, 8, 3, 0); 391 static SPRD_COMP_CLK(uart1_clk, "uart1", uart_parents, 0x34, 392 0, 2, 8, 3, 0); 393 static SPRD_COMP_CLK(uart2_clk, "uart2", uart_parents, 0x38, 394 0, 2, 8, 3, 0); 395 static SPRD_COMP_CLK(uart3_clk, "uart3", uart_parents, 0x3c, 396 0, 2, 8, 3, 0); 397 static SPRD_COMP_CLK(uart4_clk, "uart4", uart_parents, 0x40, 398 0, 2, 8, 3, 0); 399 400 static const char * const i2c_parents[] = { "ext-26m", "twpll-48m", 401 "twpll-51m2", "twpll-153m6" }; 402 static SPRD_COMP_CLK(i2c0_clk, "i2c0", i2c_parents, 0x44, 403 0, 2, 8, 3, 0); 404 static SPRD_COMP_CLK(i2c1_clk, "i2c1", i2c_parents, 0x48, 405 0, 2, 8, 3, 0); 406 static SPRD_COMP_CLK(i2c2_clk, "i2c2", i2c_parents, 0x4c, 407 0, 2, 8, 3, 0); 408 static SPRD_COMP_CLK(i2c3_clk, "i2c3", i2c_parents, 0x50, 409 0, 2, 8, 3, 0); 410 static SPRD_COMP_CLK(i2c4_clk, "i2c4", i2c_parents, 0x54, 411 0, 2, 8, 3, 0); 412 static SPRD_COMP_CLK(i2c5_clk, "i2c5", i2c_parents, 0x58, 413 0, 2, 8, 3, 0); 414 415 static const char * const spi_parents[] = { "ext-26m", "twpll-128m", 416 "twpll-153m6", "twpll-192m" }; 417 static SPRD_COMP_CLK(spi0_clk, "spi0", spi_parents, 0x5c, 418 0, 2, 8, 3, 0); 419 static SPRD_COMP_CLK(spi1_clk, "spi1", spi_parents, 0x60, 420 0, 2, 8, 3, 0); 421 static SPRD_COMP_CLK(spi2_clk, "spi2", spi_parents, 0x64, 422 0, 2, 8, 3, 0); 423 static SPRD_COMP_CLK(spi3_clk, "spi3", spi_parents, 0x68, 424 0, 2, 8, 3, 0); 425 426 static const char * const iis_parents[] = { "ext-26m", 427 "twpll-128m", 428 "twpll-153m6" }; 429 static SPRD_COMP_CLK(iis0_clk, "iis0", iis_parents, 0x6c, 430 0, 2, 8, 6, 0); 431 static SPRD_COMP_CLK(iis1_clk, "iis1", iis_parents, 0x70, 432 0, 2, 8, 6, 0); 433 static SPRD_COMP_CLK(iis2_clk, "iis2", iis_parents, 0x74, 434 0, 2, 8, 6, 0); 435 static SPRD_COMP_CLK(iis3_clk, "iis3", iis_parents, 0x78, 436 0, 2, 8, 6, 0); 437 438 static struct sprd_clk_common *sc9860_ap_clks[] = { 439 /* address base is 0x20000000 */ 440 &ap_apb.common, 441 &ap_usb3.common, 442 &uart0_clk.common, 443 &uart1_clk.common, 444 &uart2_clk.common, 445 &uart3_clk.common, 446 &uart4_clk.common, 447 &i2c0_clk.common, 448 &i2c1_clk.common, 449 &i2c2_clk.common, 450 &i2c3_clk.common, 451 &i2c4_clk.common, 452 &i2c5_clk.common, 453 &spi0_clk.common, 454 &spi1_clk.common, 455 &spi2_clk.common, 456 &spi3_clk.common, 457 &iis0_clk.common, 458 &iis1_clk.common, 459 &iis2_clk.common, 460 &iis3_clk.common, 461 }; 462 463 static struct clk_hw_onecell_data sc9860_ap_clk_hws = { 464 .hws = { 465 [CLK_AP_APB] = &ap_apb.common.hw, 466 [CLK_AP_USB3] = &ap_usb3.common.hw, 467 [CLK_UART0] = &uart0_clk.common.hw, 468 [CLK_UART1] = &uart1_clk.common.hw, 469 [CLK_UART2] = &uart2_clk.common.hw, 470 [CLK_UART3] = &uart3_clk.common.hw, 471 [CLK_UART4] = &uart4_clk.common.hw, 472 [CLK_I2C0] = &i2c0_clk.common.hw, 473 [CLK_I2C1] = &i2c1_clk.common.hw, 474 [CLK_I2C2] = &i2c2_clk.common.hw, 475 [CLK_I2C3] = &i2c3_clk.common.hw, 476 [CLK_I2C4] = &i2c4_clk.common.hw, 477 [CLK_I2C5] = &i2c5_clk.common.hw, 478 [CLK_SPI0] = &spi0_clk.common.hw, 479 [CLK_SPI1] = &spi1_clk.common.hw, 480 [CLK_SPI2] = &spi2_clk.common.hw, 481 [CLK_SPI3] = &spi3_clk.common.hw, 482 [CLK_IIS0] = &iis0_clk.common.hw, 483 [CLK_IIS1] = &iis1_clk.common.hw, 484 [CLK_IIS2] = &iis2_clk.common.hw, 485 [CLK_IIS3] = &iis3_clk.common.hw, 486 }, 487 .num = CLK_AP_CLK_NUM, 488 }; 489 490 static const struct sprd_clk_desc sc9860_ap_clk_desc = { 491 .clk_clks = sc9860_ap_clks, 492 .num_clk_clks = ARRAY_SIZE(sc9860_ap_clks), 493 .hw_clks = &sc9860_ap_clk_hws, 494 }; 495 496 static const char * const aon_apb_parents[] = { "rco-25m", "ext-26m", 497 "ext-rco-100m", "twpll-96m", 498 "twpll-128m", 499 "twpll-153m6" }; 500 static SPRD_COMP_CLK(aon_apb, "aon-apb", aon_apb_parents, 0x230, 501 0, 3, 8, 2, 0); 502 503 static const char * const aux_parents[] = { "ext-32k", "rpll0-26m", 504 "rpll1-26m", "ext-26m", 505 "cppll-50m", "rco-25m", 506 "dpll0-50m", "dpll1-50m", 507 "gpll-42m5", "twpll-48m", 508 "m0-39m", "m1-63m", 509 "l0-38m", "l1-38m" }; 510 511 static SPRD_COMP_CLK(aux0_clk, "aux0", aux_parents, 0x238, 512 0, 5, 8, 4, 0); 513 static SPRD_COMP_CLK(aux1_clk, "aux1", aux_parents, 0x23c, 514 0, 5, 8, 4, 0); 515 static SPRD_COMP_CLK(aux2_clk, "aux2", aux_parents, 0x240, 516 0, 5, 8, 4, 0); 517 static SPRD_COMP_CLK(probe_clk, "probe", aux_parents, 0x244, 518 0, 5, 8, 4, 0); 519 520 static const char * const sp_ahb_parents[] = { "rco-4m", "ext-26m", 521 "ext-rco-100m", "twpll-96m", 522 "twpll-128m", 523 "twpll-153m6" }; 524 static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0, 525 0, 3, 8, 2, 0); 526 527 static const char * const cci_parents[] = { "ext-26m", "twpll-384m", 528 "l0-614m4", "twpll-768m" }; 529 static SPRD_COMP_CLK(cci_clk, "cci", cci_parents, 0x300, 530 0, 2, 8, 2, 0); 531 static SPRD_COMP_CLK(gic_clk, "gic", cci_parents, 0x304, 532 0, 2, 8, 2, 0); 533 static SPRD_COMP_CLK(cssys_clk, "cssys", cci_parents, 0x310, 534 0, 2, 8, 2, 0); 535 536 static const char * const sdio_2x_parents[] = { "fac-1m", "ext-26m", 537 "twpll-307m2", "twpll-384m", 538 "l0-409m6" }; 539 static SPRD_COMP_CLK(sdio0_2x, "sdio0-2x", sdio_2x_parents, 0x328, 540 0, 3, 8, 4, 0); 541 static SPRD_COMP_CLK(sdio1_2x, "sdio1-2x", sdio_2x_parents, 0x330, 542 0, 3, 8, 4, 0); 543 static SPRD_COMP_CLK(sdio2_2x, "sdio2-2x", sdio_2x_parents, 0x338, 544 0, 3, 8, 4, 0); 545 static SPRD_COMP_CLK(emmc_2x, "emmc-2x", sdio_2x_parents, 0x340, 546 0, 3, 8, 4, 0); 547 548 static SPRD_DIV_CLK(sdio0_1x, "sdio0-1x", "sdio0-2x", 0x32c, 549 8, 1, 0); 550 static SPRD_DIV_CLK(sdio1_1x, "sdio1-1x", "sdio1-2x", 0x334, 551 8, 1, 0); 552 static SPRD_DIV_CLK(sdio2_1x, "sdio2-1x", "sdio2-2x", 0x33c, 553 8, 1, 0); 554 static SPRD_DIV_CLK(emmc_1x, "emmc-1x", "emmc-2x", 0x344, 555 8, 1, 0); 556 557 static const char * const adi_parents[] = { "rco-4m", "ext-26m", 558 "rco-25m", "twpll-38m4", 559 "twpll-51m2" }; 560 static SPRD_MUX_CLK(adi_clk, "adi", adi_parents, 0x234, 561 0, 3, SC9860_MUX_FLAG); 562 563 static const char * const pwm_parents[] = { "ext-32k", "ext-26m", 564 "rco-4m", "rco-25m", 565 "twpll-48m" }; 566 static SPRD_MUX_CLK(pwm0_clk, "pwm0", pwm_parents, 0x248, 567 0, 3, SC9860_MUX_FLAG); 568 static SPRD_MUX_CLK(pwm1_clk, "pwm1", pwm_parents, 0x24c, 569 0, 3, SC9860_MUX_FLAG); 570 static SPRD_MUX_CLK(pwm2_clk, "pwm2", pwm_parents, 0x250, 571 0, 3, SC9860_MUX_FLAG); 572 static SPRD_MUX_CLK(pwm3_clk, "pwm3", pwm_parents, 0x254, 573 0, 3, SC9860_MUX_FLAG); 574 575 static const char * const efuse_parents[] = { "rco-25m", "ext-26m" }; 576 static SPRD_MUX_CLK(efuse_clk, "efuse", efuse_parents, 0x258, 577 0, 1, SC9860_MUX_FLAG); 578 579 static const char * const cm3_uart_parents[] = { "rco-4m", "ext-26m", 580 "rco-100m", "twpll-48m", 581 "twpll-51m2", "twpll-96m", 582 "twpll-128m" }; 583 static SPRD_MUX_CLK(cm3_uart0, "cm3-uart0", cm3_uart_parents, 0x25c, 584 0, 3, SC9860_MUX_FLAG); 585 static SPRD_MUX_CLK(cm3_uart1, "cm3-uart1", cm3_uart_parents, 0x260, 586 0, 3, SC9860_MUX_FLAG); 587 588 static const char * const thm_parents[] = { "ext-32k", "fac-250k" }; 589 static SPRD_MUX_CLK(thm_clk, "thm", thm_parents, 0x270, 590 0, 1, SC9860_MUX_FLAG); 591 592 static const char * const cm3_i2c_parents[] = { "rco-4m", 593 "ext-26m", 594 "rco-100m", 595 "twpll-48m", 596 "twpll-51m2", 597 "twpll-153m6" }; 598 static SPRD_MUX_CLK(cm3_i2c0, "cm3-i2c0", cm3_i2c_parents, 0x274, 599 0, 3, SC9860_MUX_FLAG); 600 static SPRD_MUX_CLK(cm3_i2c1, "cm3-i2c1", cm3_i2c_parents, 0x278, 601 0, 3, SC9860_MUX_FLAG); 602 static SPRD_MUX_CLK(aon_i2c, "aon-i2c", cm3_i2c_parents, 0x280, 603 0, 3, SC9860_MUX_FLAG); 604 605 static const char * const cm4_spi_parents[] = { "ext-26m", "twpll-96m", 606 "rco-100m", "twpll-128m", 607 "twpll-153m6", "twpll-192m" }; 608 static SPRD_MUX_CLK(cm4_spi, "cm4-spi", cm4_spi_parents, 0x27c, 609 0, 3, SC9860_MUX_FLAG); 610 611 static SPRD_MUX_CLK(avs_clk, "avs", uart_parents, 0x284, 612 0, 2, SC9860_MUX_FLAG); 613 614 static const char * const ca53_dap_parents[] = { "ext-26m", "rco-4m", 615 "rco-100m", "twpll-76m8", 616 "twpll-128m", "twpll-153m6" }; 617 static SPRD_MUX_CLK(ca53_dap, "ca53-dap", ca53_dap_parents, 0x288, 618 0, 3, SC9860_MUX_FLAG); 619 620 static const char * const ca53_ts_parents[] = { "ext-32k", "ext-26m", 621 "clk-twpll-128m", 622 "clk-twpll-153m6" }; 623 static SPRD_MUX_CLK(ca53_ts, "ca53-ts", ca53_ts_parents, 0x290, 624 0, 2, SC9860_MUX_FLAG); 625 626 static const char * const djtag_tck_parents[] = { "rco-4m", "ext-26m" }; 627 static SPRD_MUX_CLK(djtag_tck, "djtag-tck", djtag_tck_parents, 0x2c8, 628 0, 1, SC9860_MUX_FLAG); 629 630 static const char * const pmu_parents[] = { "ext-32k", "rco-4m", "clk-4m" }; 631 static SPRD_MUX_CLK(pmu_clk, "pmu", pmu_parents, 0x2e0, 632 0, 2, SC9860_MUX_FLAG); 633 634 static const char * const pmu_26m_parents[] = { "rco-25m", "ext-26m" }; 635 static SPRD_MUX_CLK(pmu_26m, "pmu-26m", pmu_26m_parents, 0x2e4, 636 0, 1, SC9860_MUX_FLAG); 637 638 static const char * const debounce_parents[] = { "ext-32k", "rco-4m", 639 "rco-25m", "ext-26m" }; 640 static SPRD_MUX_CLK(debounce_clk, "debounce", debounce_parents, 0x2e8, 641 0, 2, SC9860_MUX_FLAG); 642 643 static const char * const otg2_ref_parents[] = { "twpll-12m", "twpll-24m" }; 644 static SPRD_MUX_CLK(otg2_ref, "otg2-ref", otg2_ref_parents, 0x2f4, 645 0, 1, SC9860_MUX_FLAG); 646 647 static const char * const usb3_ref_parents[] = { "twpll-24m", "twpll-19m2", 648 "twpll-48m" }; 649 static SPRD_MUX_CLK(usb3_ref, "usb3-ref", usb3_ref_parents, 0x2f8, 650 0, 2, SC9860_MUX_FLAG); 651 652 static const char * const ap_axi_parents[] = { "ext-26m", "twpll-76m8", 653 "twpll-128m", "twpll-256m" }; 654 static SPRD_MUX_CLK(ap_axi, "ap-axi", ap_axi_parents, 0x324, 655 0, 2, SC9860_MUX_FLAG); 656 657 static struct sprd_clk_common *sc9860_aon_prediv[] = { 658 /* address base is 0x402d0000 */ 659 &aon_apb.common, 660 &aux0_clk.common, 661 &aux1_clk.common, 662 &aux2_clk.common, 663 &probe_clk.common, 664 &sp_ahb.common, 665 &cci_clk.common, 666 &gic_clk.common, 667 &cssys_clk.common, 668 &sdio0_2x.common, 669 &sdio1_2x.common, 670 &sdio2_2x.common, 671 &emmc_2x.common, 672 &sdio0_1x.common, 673 &sdio1_1x.common, 674 &sdio2_1x.common, 675 &emmc_1x.common, 676 &adi_clk.common, 677 &pwm0_clk.common, 678 &pwm1_clk.common, 679 &pwm2_clk.common, 680 &pwm3_clk.common, 681 &efuse_clk.common, 682 &cm3_uart0.common, 683 &cm3_uart1.common, 684 &thm_clk.common, 685 &cm3_i2c0.common, 686 &cm3_i2c1.common, 687 &cm4_spi.common, 688 &aon_i2c.common, 689 &avs_clk.common, 690 &ca53_dap.common, 691 &ca53_ts.common, 692 &djtag_tck.common, 693 &pmu_clk.common, 694 &pmu_26m.common, 695 &debounce_clk.common, 696 &otg2_ref.common, 697 &usb3_ref.common, 698 &ap_axi.common, 699 }; 700 701 static struct clk_hw_onecell_data sc9860_aon_prediv_hws = { 702 .hws = { 703 [CLK_AON_APB] = &aon_apb.common.hw, 704 [CLK_AUX0] = &aux0_clk.common.hw, 705 [CLK_AUX1] = &aux1_clk.common.hw, 706 [CLK_AUX2] = &aux2_clk.common.hw, 707 [CLK_PROBE] = &probe_clk.common.hw, 708 [CLK_SP_AHB] = &sp_ahb.common.hw, 709 [CLK_CCI] = &cci_clk.common.hw, 710 [CLK_GIC] = &gic_clk.common.hw, 711 [CLK_CSSYS] = &cssys_clk.common.hw, 712 [CLK_SDIO0_2X] = &sdio0_2x.common.hw, 713 [CLK_SDIO1_2X] = &sdio1_2x.common.hw, 714 [CLK_SDIO2_2X] = &sdio2_2x.common.hw, 715 [CLK_EMMC_2X] = &emmc_2x.common.hw, 716 [CLK_SDIO0_1X] = &sdio0_1x.common.hw, 717 [CLK_SDIO1_1X] = &sdio1_1x.common.hw, 718 [CLK_SDIO2_1X] = &sdio2_1x.common.hw, 719 [CLK_EMMC_1X] = &emmc_1x.common.hw, 720 [CLK_ADI] = &adi_clk.common.hw, 721 [CLK_PWM0] = &pwm0_clk.common.hw, 722 [CLK_PWM1] = &pwm1_clk.common.hw, 723 [CLK_PWM2] = &pwm2_clk.common.hw, 724 [CLK_PWM3] = &pwm3_clk.common.hw, 725 [CLK_EFUSE] = &efuse_clk.common.hw, 726 [CLK_CM3_UART0] = &cm3_uart0.common.hw, 727 [CLK_CM3_UART1] = &cm3_uart1.common.hw, 728 [CLK_THM] = &thm_clk.common.hw, 729 [CLK_CM3_I2C0] = &cm3_i2c0.common.hw, 730 [CLK_CM3_I2C1] = &cm3_i2c1.common.hw, 731 [CLK_CM4_SPI] = &cm4_spi.common.hw, 732 [CLK_AON_I2C] = &aon_i2c.common.hw, 733 [CLK_AVS] = &avs_clk.common.hw, 734 [CLK_CA53_DAP] = &ca53_dap.common.hw, 735 [CLK_CA53_TS] = &ca53_ts.common.hw, 736 [CLK_DJTAG_TCK] = &djtag_tck.common.hw, 737 [CLK_PMU] = &pmu_clk.common.hw, 738 [CLK_PMU_26M] = &pmu_26m.common.hw, 739 [CLK_DEBOUNCE] = &debounce_clk.common.hw, 740 [CLK_OTG2_REF] = &otg2_ref.common.hw, 741 [CLK_USB3_REF] = &usb3_ref.common.hw, 742 [CLK_AP_AXI] = &ap_axi.common.hw, 743 }, 744 .num = CLK_AON_PREDIV_NUM, 745 }; 746 747 static const struct sprd_clk_desc sc9860_aon_prediv_desc = { 748 .clk_clks = sc9860_aon_prediv, 749 .num_clk_clks = ARRAY_SIZE(sc9860_aon_prediv), 750 .hw_clks = &sc9860_aon_prediv_hws, 751 }; 752 753 static SPRD_SC_GATE_CLK(usb3_eb, "usb3-eb", "ap-axi", 0x0, 754 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 755 static SPRD_SC_GATE_CLK(usb3_suspend, "usb3-suspend", "ap-axi", 0x0, 756 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); 757 static SPRD_SC_GATE_CLK(usb3_ref_eb, "usb3-ref-eb", "ap-axi", 0x0, 758 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); 759 static SPRD_SC_GATE_CLK(dma_eb, "dma-eb", "ap-axi", 0x0, 760 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); 761 static SPRD_SC_GATE_CLK(sdio0_eb, "sdio0-eb", "ap-axi", 0x0, 762 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); 763 static SPRD_SC_GATE_CLK(sdio1_eb, "sdio1-eb", "ap-axi", 0x0, 764 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 765 static SPRD_SC_GATE_CLK(sdio2_eb, "sdio2-eb", "ap-axi", 0x0, 766 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 767 static SPRD_SC_GATE_CLK(emmc_eb, "emmc-eb", "ap-axi", 0x0, 768 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 769 static SPRD_SC_GATE_CLK(rom_eb, "rom-eb", "ap-axi", 0x0, 770 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 771 static SPRD_SC_GATE_CLK(busmon_eb, "busmon-eb", "ap-axi", 0x0, 772 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); 773 static SPRD_SC_GATE_CLK(cc63s_eb, "cc63s-eb", "ap-axi", 0x0, 774 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); 775 static SPRD_SC_GATE_CLK(cc63p_eb, "cc63p-eb", "ap-axi", 0x0, 776 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); 777 static SPRD_SC_GATE_CLK(ce0_eb, "ce0-eb", "ap-axi", 0x0, 778 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); 779 static SPRD_SC_GATE_CLK(ce1_eb, "ce1-eb", "ap-axi", 0x0, 780 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); 781 782 static struct sprd_clk_common *sc9860_apahb_gate[] = { 783 /* address base is 0x20210000 */ 784 &usb3_eb.common, 785 &usb3_suspend.common, 786 &usb3_ref_eb.common, 787 &dma_eb.common, 788 &sdio0_eb.common, 789 &sdio1_eb.common, 790 &sdio2_eb.common, 791 &emmc_eb.common, 792 &rom_eb.common, 793 &busmon_eb.common, 794 &cc63s_eb.common, 795 &cc63p_eb.common, 796 &ce0_eb.common, 797 &ce1_eb.common, 798 }; 799 800 static struct clk_hw_onecell_data sc9860_apahb_gate_hws = { 801 .hws = { 802 [CLK_USB3_EB] = &usb3_eb.common.hw, 803 [CLK_USB3_SUSPEND_EB] = &usb3_suspend.common.hw, 804 [CLK_USB3_REF_EB] = &usb3_ref_eb.common.hw, 805 [CLK_DMA_EB] = &dma_eb.common.hw, 806 [CLK_SDIO0_EB] = &sdio0_eb.common.hw, 807 [CLK_SDIO1_EB] = &sdio1_eb.common.hw, 808 [CLK_SDIO2_EB] = &sdio2_eb.common.hw, 809 [CLK_EMMC_EB] = &emmc_eb.common.hw, 810 [CLK_ROM_EB] = &rom_eb.common.hw, 811 [CLK_BUSMON_EB] = &busmon_eb.common.hw, 812 [CLK_CC63S_EB] = &cc63s_eb.common.hw, 813 [CLK_CC63P_EB] = &cc63p_eb.common.hw, 814 [CLK_CE0_EB] = &ce0_eb.common.hw, 815 [CLK_CE1_EB] = &ce1_eb.common.hw, 816 }, 817 .num = CLK_APAHB_GATE_NUM, 818 }; 819 820 static const struct sprd_clk_desc sc9860_apahb_gate_desc = { 821 .clk_clks = sc9860_apahb_gate, 822 .num_clk_clks = ARRAY_SIZE(sc9860_apahb_gate), 823 .hw_clks = &sc9860_apahb_gate_hws, 824 }; 825 826 static SPRD_SC_GATE_CLK(avs_lit_eb, "avs-lit-eb", "aon-apb", 0x0, 827 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); 828 static SPRD_SC_GATE_CLK(avs_big_eb, "avs-big-eb", "aon-apb", 0x0, 829 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 830 static SPRD_SC_GATE_CLK(ap_intc5_eb, "ap-intc5-eb", "aon-apb", 0x0, 831 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 832 static SPRD_SC_GATE_CLK(gpio_eb, "gpio-eb", "aon-apb", 0x0, 833 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); 834 static SPRD_SC_GATE_CLK(pwm0_eb, "pwm0-eb", "aon-apb", 0x0, 835 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); 836 static SPRD_SC_GATE_CLK(pwm1_eb, "pwm1-eb", "aon-apb", 0x0, 837 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); 838 static SPRD_SC_GATE_CLK(pwm2_eb, "pwm2-eb", "aon-apb", 0x0, 839 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); 840 static SPRD_SC_GATE_CLK(pwm3_eb, "pwm3-eb", "aon-apb", 0x0, 841 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); 842 static SPRD_SC_GATE_CLK(kpd_eb, "kpd-eb", "aon-apb", 0x0, 843 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 844 static SPRD_SC_GATE_CLK(aon_sys_eb, "aon-sys-eb", "aon-apb", 0x0, 845 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 846 static SPRD_SC_GATE_CLK(ap_sys_eb, "ap-sys-eb", "aon-apb", 0x0, 847 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 848 static SPRD_SC_GATE_CLK(aon_tmr_eb, "aon-tmr-eb", "aon-apb", 0x0, 849 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); 850 static SPRD_SC_GATE_CLK(ap_tmr0_eb, "ap-tmr0-eb", "aon-apb", 0x0, 851 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 852 static SPRD_SC_GATE_CLK(efuse_eb, "efuse-eb", "aon-apb", 0x0, 853 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); 854 static SPRD_SC_GATE_CLK(eic_eb, "eic-eb", "aon-apb", 0x0, 855 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 856 static SPRD_SC_GATE_CLK(pub1_reg_eb, "pub1-reg-eb", "aon-apb", 0x0, 857 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 858 static SPRD_SC_GATE_CLK(adi_eb, "adi-eb", "aon-apb", 0x0, 859 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 860 static SPRD_SC_GATE_CLK(ap_intc0_eb, "ap-intc0-eb", "aon-apb", 0x0, 861 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 862 static SPRD_SC_GATE_CLK(ap_intc1_eb, "ap-intc1-eb", "aon-apb", 0x0, 863 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 864 static SPRD_SC_GATE_CLK(ap_intc2_eb, "ap-intc2-eb", "aon-apb", 0x0, 865 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); 866 static SPRD_SC_GATE_CLK(ap_intc3_eb, "ap-intc3-eb", "aon-apb", 0x0, 867 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); 868 static SPRD_SC_GATE_CLK(ap_intc4_eb, "ap-intc4-eb", "aon-apb", 0x0, 869 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); 870 static SPRD_SC_GATE_CLK(splk_eb, "splk-eb", "aon-apb", 0x0, 871 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); 872 static SPRD_SC_GATE_CLK(mspi_eb, "mspi-eb", "aon-apb", 0x0, 873 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); 874 static SPRD_SC_GATE_CLK(pub0_reg_eb, "pub0-reg-eb", "aon-apb", 0x0, 875 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); 876 static SPRD_SC_GATE_CLK(pin_eb, "pin-eb", "aon-apb", 0x0, 877 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); 878 static SPRD_SC_GATE_CLK(aon_ckg_eb, "aon-ckg-eb", "aon-apb", 0x0, 879 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0); 880 static SPRD_SC_GATE_CLK(gpu_eb, "gpu-eb", "aon-apb", 0x0, 881 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); 882 static SPRD_SC_GATE_CLK(apcpu_ts0_eb, "apcpu-ts0-eb", "aon-apb", 0x0, 883 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0); 884 static SPRD_SC_GATE_CLK(apcpu_ts1_eb, "apcpu-ts1-eb", "aon-apb", 0x0, 885 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0); 886 static SPRD_SC_GATE_CLK(dap_eb, "dap-eb", "aon-apb", 0x0, 887 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0); 888 static SPRD_SC_GATE_CLK(i2c_eb, "i2c-eb", "aon-apb", 0x0, 889 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0); 890 static SPRD_SC_GATE_CLK(pmu_eb, "pmu-eb", "aon-apb", 0x4, 891 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); 892 static SPRD_SC_GATE_CLK(thm_eb, "thm-eb", "aon-apb", 0x4, 893 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 894 static SPRD_SC_GATE_CLK(aux0_eb, "aux0-eb", "aon-apb", 0x4, 895 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 896 static SPRD_SC_GATE_CLK(aux1_eb, "aux1-eb", "aon-apb", 0x4, 897 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); 898 static SPRD_SC_GATE_CLK(aux2_eb, "aux2-eb", "aon-apb", 0x4, 899 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); 900 static SPRD_SC_GATE_CLK(probe_eb, "probe-eb", "aon-apb", 0x4, 901 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); 902 static SPRD_SC_GATE_CLK(gpu0_avs_eb, "gpu0-avs-eb", "aon-apb", 0x4, 903 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); 904 static SPRD_SC_GATE_CLK(gpu1_avs_eb, "gpu1-avs-eb", "aon-apb", 0x4, 905 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); 906 static SPRD_SC_GATE_CLK(apcpu_wdg_eb, "apcpu-wdg-eb", "aon-apb", 0x4, 907 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 908 static SPRD_SC_GATE_CLK(ap_tmr1_eb, "ap-tmr1-eb", "aon-apb", 0x4, 909 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 910 static SPRD_SC_GATE_CLK(ap_tmr2_eb, "ap-tmr2-eb", "aon-apb", 0x4, 911 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 912 static SPRD_SC_GATE_CLK(disp_emc_eb, "disp-emc-eb", "aon-apb", 0x4, 913 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); 914 static SPRD_SC_GATE_CLK(zip_emc_eb, "zip-emc-eb", "aon-apb", 0x4, 915 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 916 static SPRD_SC_GATE_CLK(gsp_emc_eb, "gsp-emc-eb", "aon-apb", 0x4, 917 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); 918 static SPRD_SC_GATE_CLK(osc_aon_eb, "osc-aon-eb", "aon-apb", 0x4, 919 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 920 static SPRD_SC_GATE_CLK(lvds_trx_eb, "lvds-trx-eb", "aon-apb", 0x4, 921 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 922 static SPRD_SC_GATE_CLK(lvds_tcxo_eb, "lvds-tcxo-eb", "aon-apb", 0x4, 923 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 924 static SPRD_SC_GATE_CLK(mdar_eb, "mdar-eb", "aon-apb", 0x4, 925 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 926 static SPRD_SC_GATE_CLK(rtc4m0_cal_eb, "rtc4m0-cal-eb", "aon-apb", 0x4, 927 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 928 static SPRD_SC_GATE_CLK(rct100m_cal_eb, "rct100m-cal-eb", "aon-apb", 0x4, 929 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); 930 static SPRD_SC_GATE_CLK(djtag_eb, "djtag-eb", "aon-apb", 0x4, 931 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); 932 static SPRD_SC_GATE_CLK(mbox_eb, "mbox-eb", "aon-apb", 0x4, 933 0x1000, BIT(21), CLK_IGNORE_UNUSED, 0); 934 static SPRD_SC_GATE_CLK(aon_dma_eb, "aon-dma-eb", "aon-apb", 0x4, 935 0x1000, BIT(22), CLK_IGNORE_UNUSED, 0); 936 static SPRD_SC_GATE_CLK(dbg_emc_eb, "dbg-emc-eb", "aon-apb", 0x4, 937 0x1000, BIT(23), CLK_IGNORE_UNUSED, 0); 938 static SPRD_SC_GATE_CLK(lvds_pll_div_en, "lvds-pll-div-en", "aon-apb", 0x4, 939 0x1000, BIT(24), CLK_IGNORE_UNUSED, 0); 940 static SPRD_SC_GATE_CLK(def_eb, "def-eb", "aon-apb", 0x4, 941 0x1000, BIT(25), CLK_IGNORE_UNUSED, 0); 942 static SPRD_SC_GATE_CLK(aon_apb_rsv0, "aon-apb-rsv0", "aon-apb", 0x4, 943 0x1000, BIT(26), CLK_IGNORE_UNUSED, 0); 944 static SPRD_SC_GATE_CLK(orp_jtag_eb, "orp-jtag-eb", "aon-apb", 0x4, 945 0x1000, BIT(27), CLK_IGNORE_UNUSED, 0); 946 static SPRD_SC_GATE_CLK(vsp_eb, "vsp-eb", "aon-apb", 0x4, 947 0x1000, BIT(28), CLK_IGNORE_UNUSED, 0); 948 static SPRD_SC_GATE_CLK(cam_eb, "cam-eb", "aon-apb", 0x4, 949 0x1000, BIT(29), CLK_IGNORE_UNUSED, 0); 950 static SPRD_SC_GATE_CLK(disp_eb, "disp-eb", "aon-apb", 0x4, 951 0x1000, BIT(30), CLK_IGNORE_UNUSED, 0); 952 static SPRD_SC_GATE_CLK(dbg_axi_if_eb, "dbg-axi-if-eb", "aon-apb", 0x4, 953 0x1000, BIT(31), CLK_IGNORE_UNUSED, 0); 954 static SPRD_SC_GATE_CLK(sdio0_2x_en, "sdio0-2x-en", "aon-apb", 0x13c, 955 0x1000, BIT(2), 0, 0); 956 static SPRD_SC_GATE_CLK(sdio1_2x_en, "sdio1-2x-en", "aon-apb", 0x13c, 957 0x1000, BIT(4), 0, 0); 958 static SPRD_SC_GATE_CLK(sdio2_2x_en, "sdio2-2x-en", "aon-apb", 0x13c, 959 0x1000, BIT(6), 0, 0); 960 static SPRD_SC_GATE_CLK(emmc_2x_en, "emmc-2x-en", "aon-apb", 0x13c, 961 0x1000, BIT(9), 0, 0); 962 963 static struct sprd_clk_common *sc9860_aon_gate[] = { 964 /* address base is 0x402e0000 */ 965 &avs_lit_eb.common, 966 &avs_big_eb.common, 967 &ap_intc5_eb.common, 968 &gpio_eb.common, 969 &pwm0_eb.common, 970 &pwm1_eb.common, 971 &pwm2_eb.common, 972 &pwm3_eb.common, 973 &kpd_eb.common, 974 &aon_sys_eb.common, 975 &ap_sys_eb.common, 976 &aon_tmr_eb.common, 977 &ap_tmr0_eb.common, 978 &efuse_eb.common, 979 &eic_eb.common, 980 &pub1_reg_eb.common, 981 &adi_eb.common, 982 &ap_intc0_eb.common, 983 &ap_intc1_eb.common, 984 &ap_intc2_eb.common, 985 &ap_intc3_eb.common, 986 &ap_intc4_eb.common, 987 &splk_eb.common, 988 &mspi_eb.common, 989 &pub0_reg_eb.common, 990 &pin_eb.common, 991 &aon_ckg_eb.common, 992 &gpu_eb.common, 993 &apcpu_ts0_eb.common, 994 &apcpu_ts1_eb.common, 995 &dap_eb.common, 996 &i2c_eb.common, 997 &pmu_eb.common, 998 &thm_eb.common, 999 &aux0_eb.common, 1000 &aux1_eb.common, 1001 &aux2_eb.common, 1002 &probe_eb.common, 1003 &gpu0_avs_eb.common, 1004 &gpu1_avs_eb.common, 1005 &apcpu_wdg_eb.common, 1006 &ap_tmr1_eb.common, 1007 &ap_tmr2_eb.common, 1008 &disp_emc_eb.common, 1009 &zip_emc_eb.common, 1010 &gsp_emc_eb.common, 1011 &osc_aon_eb.common, 1012 &lvds_trx_eb.common, 1013 &lvds_tcxo_eb.common, 1014 &mdar_eb.common, 1015 &rtc4m0_cal_eb.common, 1016 &rct100m_cal_eb.common, 1017 &djtag_eb.common, 1018 &mbox_eb.common, 1019 &aon_dma_eb.common, 1020 &dbg_emc_eb.common, 1021 &lvds_pll_div_en.common, 1022 &def_eb.common, 1023 &aon_apb_rsv0.common, 1024 &orp_jtag_eb.common, 1025 &vsp_eb.common, 1026 &cam_eb.common, 1027 &disp_eb.common, 1028 &dbg_axi_if_eb.common, 1029 &sdio0_2x_en.common, 1030 &sdio1_2x_en.common, 1031 &sdio2_2x_en.common, 1032 &emmc_2x_en.common, 1033 }; 1034 1035 static struct clk_hw_onecell_data sc9860_aon_gate_hws = { 1036 .hws = { 1037 [CLK_AVS_LIT_EB] = &avs_lit_eb.common.hw, 1038 [CLK_AVS_BIG_EB] = &avs_big_eb.common.hw, 1039 [CLK_AP_INTC5_EB] = &ap_intc5_eb.common.hw, 1040 [CLK_GPIO_EB] = &gpio_eb.common.hw, 1041 [CLK_PWM0_EB] = &pwm0_eb.common.hw, 1042 [CLK_PWM1_EB] = &pwm1_eb.common.hw, 1043 [CLK_PWM2_EB] = &pwm2_eb.common.hw, 1044 [CLK_PWM3_EB] = &pwm3_eb.common.hw, 1045 [CLK_KPD_EB] = &kpd_eb.common.hw, 1046 [CLK_AON_SYS_EB] = &aon_sys_eb.common.hw, 1047 [CLK_AP_SYS_EB] = &ap_sys_eb.common.hw, 1048 [CLK_AON_TMR_EB] = &aon_tmr_eb.common.hw, 1049 [CLK_AP_TMR0_EB] = &ap_tmr0_eb.common.hw, 1050 [CLK_EFUSE_EB] = &efuse_eb.common.hw, 1051 [CLK_EIC_EB] = &eic_eb.common.hw, 1052 [CLK_PUB1_REG_EB] = &pub1_reg_eb.common.hw, 1053 [CLK_ADI_EB] = &adi_eb.common.hw, 1054 [CLK_AP_INTC0_EB] = &ap_intc0_eb.common.hw, 1055 [CLK_AP_INTC1_EB] = &ap_intc1_eb.common.hw, 1056 [CLK_AP_INTC2_EB] = &ap_intc2_eb.common.hw, 1057 [CLK_AP_INTC3_EB] = &ap_intc3_eb.common.hw, 1058 [CLK_AP_INTC4_EB] = &ap_intc4_eb.common.hw, 1059 [CLK_SPLK_EB] = &splk_eb.common.hw, 1060 [CLK_MSPI_EB] = &mspi_eb.common.hw, 1061 [CLK_PUB0_REG_EB] = &pub0_reg_eb.common.hw, 1062 [CLK_PIN_EB] = &pin_eb.common.hw, 1063 [CLK_AON_CKG_EB] = &aon_ckg_eb.common.hw, 1064 [CLK_GPU_EB] = &gpu_eb.common.hw, 1065 [CLK_APCPU_TS0_EB] = &apcpu_ts0_eb.common.hw, 1066 [CLK_APCPU_TS1_EB] = &apcpu_ts1_eb.common.hw, 1067 [CLK_DAP_EB] = &dap_eb.common.hw, 1068 [CLK_I2C_EB] = &i2c_eb.common.hw, 1069 [CLK_PMU_EB] = &pmu_eb.common.hw, 1070 [CLK_THM_EB] = &thm_eb.common.hw, 1071 [CLK_AUX0_EB] = &aux0_eb.common.hw, 1072 [CLK_AUX1_EB] = &aux1_eb.common.hw, 1073 [CLK_AUX2_EB] = &aux2_eb.common.hw, 1074 [CLK_PROBE_EB] = &probe_eb.common.hw, 1075 [CLK_GPU0_AVS_EB] = &gpu0_avs_eb.common.hw, 1076 [CLK_GPU1_AVS_EB] = &gpu1_avs_eb.common.hw, 1077 [CLK_APCPU_WDG_EB] = &apcpu_wdg_eb.common.hw, 1078 [CLK_AP_TMR1_EB] = &ap_tmr1_eb.common.hw, 1079 [CLK_AP_TMR2_EB] = &ap_tmr2_eb.common.hw, 1080 [CLK_DISP_EMC_EB] = &disp_emc_eb.common.hw, 1081 [CLK_ZIP_EMC_EB] = &zip_emc_eb.common.hw, 1082 [CLK_GSP_EMC_EB] = &gsp_emc_eb.common.hw, 1083 [CLK_OSC_AON_EB] = &osc_aon_eb.common.hw, 1084 [CLK_LVDS_TRX_EB] = &lvds_trx_eb.common.hw, 1085 [CLK_LVDS_TCXO_EB] = &lvds_tcxo_eb.common.hw, 1086 [CLK_MDAR_EB] = &mdar_eb.common.hw, 1087 [CLK_RTC4M0_CAL_EB] = &rtc4m0_cal_eb.common.hw, 1088 [CLK_RCT100M_CAL_EB] = &rct100m_cal_eb.common.hw, 1089 [CLK_DJTAG_EB] = &djtag_eb.common.hw, 1090 [CLK_MBOX_EB] = &mbox_eb.common.hw, 1091 [CLK_AON_DMA_EB] = &aon_dma_eb.common.hw, 1092 [CLK_DBG_EMC_EB] = &dbg_emc_eb.common.hw, 1093 [CLK_LVDS_PLL_DIV_EN] = &lvds_pll_div_en.common.hw, 1094 [CLK_DEF_EB] = &def_eb.common.hw, 1095 [CLK_AON_APB_RSV0] = &aon_apb_rsv0.common.hw, 1096 [CLK_ORP_JTAG_EB] = &orp_jtag_eb.common.hw, 1097 [CLK_VSP_EB] = &vsp_eb.common.hw, 1098 [CLK_CAM_EB] = &cam_eb.common.hw, 1099 [CLK_DISP_EB] = &disp_eb.common.hw, 1100 [CLK_DBG_AXI_IF_EB] = &dbg_axi_if_eb.common.hw, 1101 [CLK_SDIO0_2X_EN] = &sdio0_2x_en.common.hw, 1102 [CLK_SDIO1_2X_EN] = &sdio1_2x_en.common.hw, 1103 [CLK_SDIO2_2X_EN] = &sdio2_2x_en.common.hw, 1104 [CLK_EMMC_2X_EN] = &emmc_2x_en.common.hw, 1105 }, 1106 .num = CLK_AON_GATE_NUM, 1107 }; 1108 1109 static const struct sprd_clk_desc sc9860_aon_gate_desc = { 1110 .clk_clks = sc9860_aon_gate, 1111 .num_clk_clks = ARRAY_SIZE(sc9860_aon_gate), 1112 .hw_clks = &sc9860_aon_gate_hws, 1113 }; 1114 1115 static const u8 mcu_table[] = { 0, 1, 2, 3, 4, 8 }; 1116 static const char * const lit_mcu_parents[] = { "ext-26m", "twpll-512m", 1117 "twpll-768m", "ltepll0", 1118 "twpll", "mpll0" }; 1119 static SPRD_COMP_CLK_TABLE(lit_mcu, "lit-mcu", lit_mcu_parents, 0x20, 1120 mcu_table, 0, 4, 4, 3, 0); 1121 1122 static const char * const big_mcu_parents[] = { "ext-26m", "twpll-512m", 1123 "twpll-768m", "ltepll0", 1124 "twpll", "mpll1" }; 1125 static SPRD_COMP_CLK_TABLE(big_mcu, "big-mcu", big_mcu_parents, 0x24, 1126 mcu_table, 0, 4, 4, 3, 0); 1127 1128 static struct sprd_clk_common *sc9860_aonsecure_clk[] = { 1129 /* address base is 0x40880000 */ 1130 &lit_mcu.common, 1131 &big_mcu.common, 1132 }; 1133 1134 static struct clk_hw_onecell_data sc9860_aonsecure_clk_hws = { 1135 .hws = { 1136 [CLK_LIT_MCU] = &lit_mcu.common.hw, 1137 [CLK_BIG_MCU] = &big_mcu.common.hw, 1138 }, 1139 .num = CLK_AONSECURE_NUM, 1140 }; 1141 1142 static const struct sprd_clk_desc sc9860_aonsecure_clk_desc = { 1143 .clk_clks = sc9860_aonsecure_clk, 1144 .num_clk_clks = ARRAY_SIZE(sc9860_aonsecure_clk), 1145 .hw_clks = &sc9860_aonsecure_clk_hws, 1146 }; 1147 1148 static SPRD_SC_GATE_CLK(agcp_iis0_eb, "agcp-iis0-eb", "aon-apb", 1149 0x0, 0x100, BIT(0), 0, 0); 1150 static SPRD_SC_GATE_CLK(agcp_iis1_eb, "agcp-iis1-eb", "aon-apb", 1151 0x0, 0x100, BIT(1), 0, 0); 1152 static SPRD_SC_GATE_CLK(agcp_iis2_eb, "agcp-iis2-eb", "aon-apb", 1153 0x0, 0x100, BIT(2), 0, 0); 1154 static SPRD_SC_GATE_CLK(agcp_iis3_eb, "agcp-iis3-eb", "aon-apb", 1155 0x0, 0x100, BIT(3), 0, 0); 1156 static SPRD_SC_GATE_CLK(agcp_uart_eb, "agcp-uart-eb", "aon-apb", 1157 0x0, 0x100, BIT(4), 0, 0); 1158 static SPRD_SC_GATE_CLK(agcp_dmacp_eb, "agcp-dmacp-eb", "aon-apb", 1159 0x0, 0x100, BIT(5), 0, 0); 1160 static SPRD_SC_GATE_CLK(agcp_dmaap_eb, "agcp-dmaap-eb", "aon-apb", 1161 0x0, 0x100, BIT(6), 0, 0); 1162 static SPRD_SC_GATE_CLK(agcp_arc48k_eb, "agcp-arc48k-eb", "aon-apb", 1163 0x0, 0x100, BIT(10), 0, 0); 1164 static SPRD_SC_GATE_CLK(agcp_src44p1k_eb, "agcp-src44p1k-eb", "aon-apb", 1165 0x0, 0x100, BIT(11), 0, 0); 1166 static SPRD_SC_GATE_CLK(agcp_mcdt_eb, "agcp-mcdt-eb", "aon-apb", 1167 0x0, 0x100, BIT(12), 0, 0); 1168 static SPRD_SC_GATE_CLK(agcp_vbcifd_eb, "agcp-vbcifd-eb", "aon-apb", 1169 0x0, 0x100, BIT(13), 0, 0); 1170 static SPRD_SC_GATE_CLK(agcp_vbc_eb, "agcp-vbc-eb", "aon-apb", 1171 0x0, 0x100, BIT(14), 0, 0); 1172 static SPRD_SC_GATE_CLK(agcp_spinlock_eb, "agcp-spinlock-eb", "aon-apb", 1173 0x0, 0x100, BIT(15), 0, 0); 1174 static SPRD_SC_GATE_CLK(agcp_icu_eb, "agcp-icu-eb", "aon-apb", 1175 0x0, 0x100, BIT(16), CLK_IGNORE_UNUSED, 0); 1176 static SPRD_SC_GATE_CLK(agcp_ap_ashb_eb, "agcp-ap-ashb-eb", "aon-apb", 1177 0x0, 0x100, BIT(17), 0, 0); 1178 static SPRD_SC_GATE_CLK(agcp_cp_ashb_eb, "agcp-cp-ashb-eb", "aon-apb", 1179 0x0, 0x100, BIT(18), 0, 0); 1180 static SPRD_SC_GATE_CLK(agcp_aud_eb, "agcp-aud-eb", "aon-apb", 1181 0x0, 0x100, BIT(19), 0, 0); 1182 static SPRD_SC_GATE_CLK(agcp_audif_eb, "agcp-audif-eb", "aon-apb", 1183 0x0, 0x100, BIT(20), 0, 0); 1184 1185 static struct sprd_clk_common *sc9860_agcp_gate[] = { 1186 /* address base is 0x415e0000 */ 1187 &agcp_iis0_eb.common, 1188 &agcp_iis1_eb.common, 1189 &agcp_iis2_eb.common, 1190 &agcp_iis3_eb.common, 1191 &agcp_uart_eb.common, 1192 &agcp_dmacp_eb.common, 1193 &agcp_dmaap_eb.common, 1194 &agcp_arc48k_eb.common, 1195 &agcp_src44p1k_eb.common, 1196 &agcp_mcdt_eb.common, 1197 &agcp_vbcifd_eb.common, 1198 &agcp_vbc_eb.common, 1199 &agcp_spinlock_eb.common, 1200 &agcp_icu_eb.common, 1201 &agcp_ap_ashb_eb.common, 1202 &agcp_cp_ashb_eb.common, 1203 &agcp_aud_eb.common, 1204 &agcp_audif_eb.common, 1205 }; 1206 1207 static struct clk_hw_onecell_data sc9860_agcp_gate_hws = { 1208 .hws = { 1209 [CLK_AGCP_IIS0_EB] = &agcp_iis0_eb.common.hw, 1210 [CLK_AGCP_IIS1_EB] = &agcp_iis1_eb.common.hw, 1211 [CLK_AGCP_IIS2_EB] = &agcp_iis2_eb.common.hw, 1212 [CLK_AGCP_IIS3_EB] = &agcp_iis3_eb.common.hw, 1213 [CLK_AGCP_UART_EB] = &agcp_uart_eb.common.hw, 1214 [CLK_AGCP_DMACP_EB] = &agcp_dmacp_eb.common.hw, 1215 [CLK_AGCP_DMAAP_EB] = &agcp_dmaap_eb.common.hw, 1216 [CLK_AGCP_ARC48K_EB] = &agcp_arc48k_eb.common.hw, 1217 [CLK_AGCP_SRC44P1K_EB] = &agcp_src44p1k_eb.common.hw, 1218 [CLK_AGCP_MCDT_EB] = &agcp_mcdt_eb.common.hw, 1219 [CLK_AGCP_VBCIFD_EB] = &agcp_vbcifd_eb.common.hw, 1220 [CLK_AGCP_VBC_EB] = &agcp_vbc_eb.common.hw, 1221 [CLK_AGCP_SPINLOCK_EB] = &agcp_spinlock_eb.common.hw, 1222 [CLK_AGCP_ICU_EB] = &agcp_icu_eb.common.hw, 1223 [CLK_AGCP_AP_ASHB_EB] = &agcp_ap_ashb_eb.common.hw, 1224 [CLK_AGCP_CP_ASHB_EB] = &agcp_cp_ashb_eb.common.hw, 1225 [CLK_AGCP_AUD_EB] = &agcp_aud_eb.common.hw, 1226 [CLK_AGCP_AUDIF_EB] = &agcp_audif_eb.common.hw, 1227 }, 1228 .num = CLK_AGCP_GATE_NUM, 1229 }; 1230 1231 static const struct sprd_clk_desc sc9860_agcp_gate_desc = { 1232 .clk_clks = sc9860_agcp_gate, 1233 .num_clk_clks = ARRAY_SIZE(sc9860_agcp_gate), 1234 .hw_clks = &sc9860_agcp_gate_hws, 1235 }; 1236 1237 static const char * const gpu_parents[] = { "twpll-512m", 1238 "twpll-768m", 1239 "gpll" }; 1240 static SPRD_COMP_CLK(gpu_clk, "gpu", gpu_parents, 0x20, 1241 0, 2, 8, 4, 0); 1242 1243 static struct sprd_clk_common *sc9860_gpu_clk[] = { 1244 /* address base is 0x60200000 */ 1245 &gpu_clk.common, 1246 }; 1247 1248 static struct clk_hw_onecell_data sc9860_gpu_clk_hws = { 1249 .hws = { 1250 [CLK_GPU] = &gpu_clk.common.hw, 1251 }, 1252 .num = CLK_GPU_NUM, 1253 }; 1254 1255 static const struct sprd_clk_desc sc9860_gpu_clk_desc = { 1256 .clk_clks = sc9860_gpu_clk, 1257 .num_clk_clks = ARRAY_SIZE(sc9860_gpu_clk), 1258 .hw_clks = &sc9860_gpu_clk_hws, 1259 }; 1260 1261 static const char * const ahb_parents[] = { "ext-26m", "twpll-96m", 1262 "twpll-128m", "twpll-153m6" }; 1263 static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20, 1264 0, 2, SC9860_MUX_FLAG); 1265 1266 static const char * const vsp_parents[] = { "twpll-76m8", "twpll-128m", 1267 "twpll-256m", "twpll-307m2", 1268 "twpll-384m" }; 1269 static SPRD_COMP_CLK(vsp_clk, "vsp", vsp_parents, 0x24, 0, 3, 8, 2, 0); 1270 1271 static const char * const dispc_parents[] = { "twpll-76m8", "twpll-128m", 1272 "twpll-256m", "twpll-307m2" }; 1273 static SPRD_COMP_CLK(vsp_enc, "vsp-enc", dispc_parents, 0x28, 0, 2, 8, 2, 0); 1274 1275 static const char * const vpp_parents[] = { "twpll-96m", "twpll-153m6", 1276 "twpll-192m", "twpll-256m" }; 1277 static SPRD_MUX_CLK(vpp_clk, "vpp", vpp_parents, 0x2c, 1278 0, 2, SC9860_MUX_FLAG); 1279 static const char * const vsp_26m_parents[] = { "ext-26m" }; 1280 static SPRD_MUX_CLK(vsp_26m, "vsp-26m", vsp_26m_parents, 0x30, 1281 0, 1, SC9860_MUX_FLAG); 1282 1283 static struct sprd_clk_common *sc9860_vsp_clk[] = { 1284 /* address base is 0x61000000 */ 1285 &ahb_vsp.common, 1286 &vsp_clk.common, 1287 &vsp_enc.common, 1288 &vpp_clk.common, 1289 &vsp_26m.common, 1290 }; 1291 1292 static struct clk_hw_onecell_data sc9860_vsp_clk_hws = { 1293 .hws = { 1294 [CLK_AHB_VSP] = &ahb_vsp.common.hw, 1295 [CLK_VSP] = &vsp_clk.common.hw, 1296 [CLK_VSP_ENC] = &vsp_enc.common.hw, 1297 [CLK_VPP] = &vpp_clk.common.hw, 1298 [CLK_VSP_26M] = &vsp_26m.common.hw, 1299 }, 1300 .num = CLK_VSP_NUM, 1301 }; 1302 1303 static const struct sprd_clk_desc sc9860_vsp_clk_desc = { 1304 .clk_clks = sc9860_vsp_clk, 1305 .num_clk_clks = ARRAY_SIZE(sc9860_vsp_clk), 1306 .hw_clks = &sc9860_vsp_clk_hws, 1307 }; 1308 1309 static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0, 1310 0x1000, BIT(0), 0, 0); 1311 static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0, 1312 0x1000, BIT(1), 0, 0); 1313 static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0, 1314 0x1000, BIT(2), 0, 0); 1315 static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0, 1316 0x1000, BIT(3), 0, 0); 1317 static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0, 1318 0x1000, BIT(4), 0, 0); 1319 static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0, 1320 0x1000, BIT(5), 0, 0); 1321 static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8, 1322 BIT(0), 0, 0); 1323 static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8, 1324 BIT(1), 0, 0); 1325 static SPRD_GATE_CLK(vpp_axi_gate, "vpp-axi-gate", "ahb-vsp", 0x8, 1326 BIT(2), 0, 0); 1327 static SPRD_GATE_CLK(vsp_bm_gate, "vsp-bm-gate", "ahb-vsp", 0x8, 1328 BIT(8), 0, 0); 1329 static SPRD_GATE_CLK(vsp_enc_bm_gate, "vsp-enc-bm-gate", "ahb-vsp", 0x8, 1330 BIT(9), 0, 0); 1331 static SPRD_GATE_CLK(vpp_bm_gate, "vpp-bm-gate", "ahb-vsp", 0x8, 1332 BIT(10), 0, 0); 1333 1334 static struct sprd_clk_common *sc9860_vsp_gate[] = { 1335 /* address base is 0x61100000 */ 1336 &vsp_dec_eb.common, 1337 &vsp_ckg_eb.common, 1338 &vsp_mmu_eb.common, 1339 &vsp_enc_eb.common, 1340 &vpp_eb.common, 1341 &vsp_26m_eb.common, 1342 &vsp_axi_gate.common, 1343 &vsp_enc_gate.common, 1344 &vpp_axi_gate.common, 1345 &vsp_bm_gate.common, 1346 &vsp_enc_bm_gate.common, 1347 &vpp_bm_gate.common, 1348 }; 1349 1350 static struct clk_hw_onecell_data sc9860_vsp_gate_hws = { 1351 .hws = { 1352 [CLK_VSP_DEC_EB] = &vsp_dec_eb.common.hw, 1353 [CLK_VSP_CKG_EB] = &vsp_ckg_eb.common.hw, 1354 [CLK_VSP_MMU_EB] = &vsp_mmu_eb.common.hw, 1355 [CLK_VSP_ENC_EB] = &vsp_enc_eb.common.hw, 1356 [CLK_VPP_EB] = &vpp_eb.common.hw, 1357 [CLK_VSP_26M_EB] = &vsp_26m_eb.common.hw, 1358 [CLK_VSP_AXI_GATE] = &vsp_axi_gate.common.hw, 1359 [CLK_VSP_ENC_GATE] = &vsp_enc_gate.common.hw, 1360 [CLK_VPP_AXI_GATE] = &vpp_axi_gate.common.hw, 1361 [CLK_VSP_BM_GATE] = &vsp_bm_gate.common.hw, 1362 [CLK_VSP_ENC_BM_GATE] = &vsp_enc_bm_gate.common.hw, 1363 [CLK_VPP_BM_GATE] = &vpp_bm_gate.common.hw, 1364 }, 1365 .num = CLK_VSP_GATE_NUM, 1366 }; 1367 1368 static const struct sprd_clk_desc sc9860_vsp_gate_desc = { 1369 .clk_clks = sc9860_vsp_gate, 1370 .num_clk_clks = ARRAY_SIZE(sc9860_vsp_gate), 1371 .hw_clks = &sc9860_vsp_gate_hws, 1372 }; 1373 1374 static SPRD_MUX_CLK(ahb_cam, "ahb-cam", ahb_parents, 0x20, 1375 0, 2, SC9860_MUX_FLAG); 1376 static const char * const sensor_parents[] = { "ext-26m", "twpll-48m", 1377 "twpll-76m8", "twpll-96m" }; 1378 static SPRD_COMP_CLK(sensor0_clk, "sensor0", sensor_parents, 0x24, 1379 0, 2, 8, 3, 0); 1380 static SPRD_COMP_CLK(sensor1_clk, "sensor1", sensor_parents, 0x28, 1381 0, 2, 8, 3, 0); 1382 static SPRD_COMP_CLK(sensor2_clk, "sensor2", sensor_parents, 0x2c, 1383 0, 2, 8, 3, 0); 1384 static SPRD_GATE_CLK(mipi_csi0_eb, "mipi-csi0-eb", "ahb-cam", 0x4c, 1385 BIT(16), 0, 0); 1386 static SPRD_GATE_CLK(mipi_csi1_eb, "mipi-csi1-eb", "ahb-cam", 0x50, 1387 BIT(16), 0, 0); 1388 1389 static struct sprd_clk_common *sc9860_cam_clk[] = { 1390 /* address base is 0x62000000 */ 1391 &ahb_cam.common, 1392 &sensor0_clk.common, 1393 &sensor1_clk.common, 1394 &sensor2_clk.common, 1395 &mipi_csi0_eb.common, 1396 &mipi_csi1_eb.common, 1397 }; 1398 1399 static struct clk_hw_onecell_data sc9860_cam_clk_hws = { 1400 .hws = { 1401 [CLK_AHB_CAM] = &ahb_cam.common.hw, 1402 [CLK_SENSOR0] = &sensor0_clk.common.hw, 1403 [CLK_SENSOR1] = &sensor1_clk.common.hw, 1404 [CLK_SENSOR2] = &sensor2_clk.common.hw, 1405 [CLK_MIPI_CSI0_EB] = &mipi_csi0_eb.common.hw, 1406 [CLK_MIPI_CSI1_EB] = &mipi_csi1_eb.common.hw, 1407 }, 1408 .num = CLK_CAM_NUM, 1409 }; 1410 1411 static const struct sprd_clk_desc sc9860_cam_clk_desc = { 1412 .clk_clks = sc9860_cam_clk, 1413 .num_clk_clks = ARRAY_SIZE(sc9860_cam_clk), 1414 .hw_clks = &sc9860_cam_clk_hws, 1415 }; 1416 1417 static SPRD_SC_GATE_CLK(dcam0_eb, "dcam0-eb", "ahb-cam", 0x0, 1418 0x1000, BIT(0), 0, 0); 1419 static SPRD_SC_GATE_CLK(dcam1_eb, "dcam1-eb", "ahb-cam", 0x0, 1420 0x1000, BIT(1), 0, 0); 1421 static SPRD_SC_GATE_CLK(isp0_eb, "isp0-eb", "ahb-cam", 0x0, 1422 0x1000, BIT(2), 0, 0); 1423 static SPRD_SC_GATE_CLK(csi0_eb, "csi0-eb", "ahb-cam", 0x0, 1424 0x1000, BIT(3), 0, 0); 1425 static SPRD_SC_GATE_CLK(csi1_eb, "csi1-eb", "ahb-cam", 0x0, 1426 0x1000, BIT(4), 0, 0); 1427 static SPRD_SC_GATE_CLK(jpg0_eb, "jpg0-eb", "ahb-cam", 0x0, 1428 0x1000, BIT(5), 0, 0); 1429 static SPRD_SC_GATE_CLK(jpg1_eb, "jpg1-eb", "ahb-cam", 0x0, 1430 0x1000, BIT(6), 0, 0); 1431 static SPRD_SC_GATE_CLK(cam_ckg_eb, "cam-ckg-eb", "ahb-cam", 0x0, 1432 0x1000, BIT(7), 0, 0); 1433 static SPRD_SC_GATE_CLK(cam_mmu_eb, "cam-mmu-eb", "ahb-cam", 0x0, 1434 0x1000, BIT(8), 0, 0); 1435 static SPRD_SC_GATE_CLK(isp1_eb, "isp1-eb", "ahb-cam", 0x0, 1436 0x1000, BIT(9), 0, 0); 1437 static SPRD_SC_GATE_CLK(cpp_eb, "cpp-eb", "ahb-cam", 0x0, 1438 0x1000, BIT(10), 0, 0); 1439 static SPRD_SC_GATE_CLK(mmu_pf_eb, "mmu-pf-eb", "ahb-cam", 0x0, 1440 0x1000, BIT(11), 0, 0); 1441 static SPRD_SC_GATE_CLK(isp2_eb, "isp2-eb", "ahb-cam", 0x0, 1442 0x1000, BIT(12), 0, 0); 1443 static SPRD_SC_GATE_CLK(dcam2isp_if_eb, "dcam2isp-if-eb", "ahb-cam", 0x0, 1444 0x1000, BIT(13), 0, 0); 1445 static SPRD_SC_GATE_CLK(isp2dcam_if_eb, "isp2dcam-if-eb", "ahb-cam", 0x0, 1446 0x1000, BIT(14), 0, 0); 1447 static SPRD_SC_GATE_CLK(isp_lclk_eb, "isp-lclk-eb", "ahb-cam", 0x0, 1448 0x1000, BIT(15), 0, 0); 1449 static SPRD_SC_GATE_CLK(isp_iclk_eb, "isp-iclk-eb", "ahb-cam", 0x0, 1450 0x1000, BIT(16), 0, 0); 1451 static SPRD_SC_GATE_CLK(isp_mclk_eb, "isp-mclk-eb", "ahb-cam", 0x0, 1452 0x1000, BIT(17), 0, 0); 1453 static SPRD_SC_GATE_CLK(isp_pclk_eb, "isp-pclk-eb", "ahb-cam", 0x0, 1454 0x1000, BIT(18), 0, 0); 1455 static SPRD_SC_GATE_CLK(isp_isp2dcam_eb, "isp-isp2dcam-eb", "ahb-cam", 0x0, 1456 0x1000, BIT(19), 0, 0); 1457 static SPRD_SC_GATE_CLK(dcam0_if_eb, "dcam0-if-eb", "ahb-cam", 0x0, 1458 0x1000, BIT(20), 0, 0); 1459 static SPRD_SC_GATE_CLK(clk26m_if_eb, "clk26m-if-eb", "ahb-cam", 0x0, 1460 0x1000, BIT(21), 0, 0); 1461 static SPRD_GATE_CLK(cphy0_gate, "cphy0-gate", "ahb-cam", 0x8, 1462 BIT(0), 0, 0); 1463 static SPRD_GATE_CLK(mipi_csi0_gate, "mipi-csi0-gate", "ahb-cam", 0x8, 1464 BIT(1), 0, 0); 1465 static SPRD_GATE_CLK(cphy1_gate, "cphy1-gate", "ahb-cam", 0x8, 1466 BIT(2), 0, 0); 1467 static SPRD_GATE_CLK(mipi_csi1, "mipi-csi1", "ahb-cam", 0x8, 1468 BIT(3), 0, 0); 1469 static SPRD_GATE_CLK(dcam0_axi_gate, "dcam0-axi-gate", "ahb-cam", 0x8, 1470 BIT(4), 0, 0); 1471 static SPRD_GATE_CLK(dcam1_axi_gate, "dcam1-axi-gate", "ahb-cam", 0x8, 1472 BIT(5), 0, 0); 1473 static SPRD_GATE_CLK(sensor0_gate, "sensor0-gate", "ahb-cam", 0x8, 1474 BIT(6), 0, 0); 1475 static SPRD_GATE_CLK(sensor1_gate, "sensor1-gate", "ahb-cam", 0x8, 1476 BIT(7), 0, 0); 1477 static SPRD_GATE_CLK(jpg0_axi_gate, "jpg0-axi-gate", "ahb-cam", 0x8, 1478 BIT(8), 0, 0); 1479 static SPRD_GATE_CLK(gpg1_axi_gate, "gpg1-axi-gate", "ahb-cam", 0x8, 1480 BIT(9), 0, 0); 1481 static SPRD_GATE_CLK(isp0_axi_gate, "isp0-axi-gate", "ahb-cam", 0x8, 1482 BIT(10), 0, 0); 1483 static SPRD_GATE_CLK(isp1_axi_gate, "isp1-axi-gate", "ahb-cam", 0x8, 1484 BIT(11), 0, 0); 1485 static SPRD_GATE_CLK(isp2_axi_gate, "isp2-axi-gate", "ahb-cam", 0x8, 1486 BIT(12), 0, 0); 1487 static SPRD_GATE_CLK(cpp_axi_gate, "cpp-axi-gate", "ahb-cam", 0x8, 1488 BIT(13), 0, 0); 1489 static SPRD_GATE_CLK(d0_if_axi_gate, "d0-if-axi-gate", "ahb-cam", 0x8, 1490 BIT(14), 0, 0); 1491 static SPRD_GATE_CLK(d2i_if_axi_gate, "d2i-if-axi-gate", "ahb-cam", 0x8, 1492 BIT(15), 0, 0); 1493 static SPRD_GATE_CLK(i2d_if_axi_gate, "i2d-if-axi-gate", "ahb-cam", 0x8, 1494 BIT(16), 0, 0); 1495 static SPRD_GATE_CLK(spare_axi_gate, "spare-axi-gate", "ahb-cam", 0x8, 1496 BIT(17), 0, 0); 1497 static SPRD_GATE_CLK(sensor2_gate, "sensor2-gate", "ahb-cam", 0x8, 1498 BIT(18), 0, 0); 1499 static SPRD_SC_GATE_CLK(d0if_in_d_en, "d0if-in-d-en", "ahb-cam", 0x28, 1500 0x1000, BIT(0), 0, 0); 1501 static SPRD_SC_GATE_CLK(d1if_in_d_en, "d1if-in-d-en", "ahb-cam", 0x28, 1502 0x1000, BIT(1), 0, 0); 1503 static SPRD_SC_GATE_CLK(d0if_in_d2i_en, "d0if-in-d2i-en", "ahb-cam", 0x28, 1504 0x1000, BIT(2), 0, 0); 1505 static SPRD_SC_GATE_CLK(d1if_in_d2i_en, "d1if-in-d2i-en", "ahb-cam", 0x28, 1506 0x1000, BIT(3), 0, 0); 1507 static SPRD_SC_GATE_CLK(ia_in_d2i_en, "ia-in-d2i-en", "ahb-cam", 0x28, 1508 0x1000, BIT(4), 0, 0); 1509 static SPRD_SC_GATE_CLK(ib_in_d2i_en, "ib-in-d2i-en", "ahb-cam", 0x28, 1510 0x1000, BIT(5), 0, 0); 1511 static SPRD_SC_GATE_CLK(ic_in_d2i_en, "ic-in-d2i-en", "ahb-cam", 0x28, 1512 0x1000, BIT(6), 0, 0); 1513 static SPRD_SC_GATE_CLK(ia_in_i_en, "ia-in-i-en", "ahb-cam", 0x28, 1514 0x1000, BIT(7), 0, 0); 1515 static SPRD_SC_GATE_CLK(ib_in_i_en, "ib-in-i-en", "ahb-cam", 0x28, 1516 0x1000, BIT(8), 0, 0); 1517 static SPRD_SC_GATE_CLK(ic_in_i_en, "ic-in-i-en", "ahb-cam", 0x28, 1518 0x1000, BIT(9), 0, 0); 1519 1520 static struct sprd_clk_common *sc9860_cam_gate[] = { 1521 /* address base is 0x62100000 */ 1522 &dcam0_eb.common, 1523 &dcam1_eb.common, 1524 &isp0_eb.common, 1525 &csi0_eb.common, 1526 &csi1_eb.common, 1527 &jpg0_eb.common, 1528 &jpg1_eb.common, 1529 &cam_ckg_eb.common, 1530 &cam_mmu_eb.common, 1531 &isp1_eb.common, 1532 &cpp_eb.common, 1533 &mmu_pf_eb.common, 1534 &isp2_eb.common, 1535 &dcam2isp_if_eb.common, 1536 &isp2dcam_if_eb.common, 1537 &isp_lclk_eb.common, 1538 &isp_iclk_eb.common, 1539 &isp_mclk_eb.common, 1540 &isp_pclk_eb.common, 1541 &isp_isp2dcam_eb.common, 1542 &dcam0_if_eb.common, 1543 &clk26m_if_eb.common, 1544 &cphy0_gate.common, 1545 &mipi_csi0_gate.common, 1546 &cphy1_gate.common, 1547 &mipi_csi1.common, 1548 &dcam0_axi_gate.common, 1549 &dcam1_axi_gate.common, 1550 &sensor0_gate.common, 1551 &sensor1_gate.common, 1552 &jpg0_axi_gate.common, 1553 &gpg1_axi_gate.common, 1554 &isp0_axi_gate.common, 1555 &isp1_axi_gate.common, 1556 &isp2_axi_gate.common, 1557 &cpp_axi_gate.common, 1558 &d0_if_axi_gate.common, 1559 &d2i_if_axi_gate.common, 1560 &i2d_if_axi_gate.common, 1561 &spare_axi_gate.common, 1562 &sensor2_gate.common, 1563 &d0if_in_d_en.common, 1564 &d1if_in_d_en.common, 1565 &d0if_in_d2i_en.common, 1566 &d1if_in_d2i_en.common, 1567 &ia_in_d2i_en.common, 1568 &ib_in_d2i_en.common, 1569 &ic_in_d2i_en.common, 1570 &ia_in_i_en.common, 1571 &ib_in_i_en.common, 1572 &ic_in_i_en.common, 1573 }; 1574 1575 static struct clk_hw_onecell_data sc9860_cam_gate_hws = { 1576 .hws = { 1577 [CLK_DCAM0_EB] = &dcam0_eb.common.hw, 1578 [CLK_DCAM1_EB] = &dcam1_eb.common.hw, 1579 [CLK_ISP0_EB] = &isp0_eb.common.hw, 1580 [CLK_CSI0_EB] = &csi0_eb.common.hw, 1581 [CLK_CSI1_EB] = &csi1_eb.common.hw, 1582 [CLK_JPG0_EB] = &jpg0_eb.common.hw, 1583 [CLK_JPG1_EB] = &jpg1_eb.common.hw, 1584 [CLK_CAM_CKG_EB] = &cam_ckg_eb.common.hw, 1585 [CLK_CAM_MMU_EB] = &cam_mmu_eb.common.hw, 1586 [CLK_ISP1_EB] = &isp1_eb.common.hw, 1587 [CLK_CPP_EB] = &cpp_eb.common.hw, 1588 [CLK_MMU_PF_EB] = &mmu_pf_eb.common.hw, 1589 [CLK_ISP2_EB] = &isp2_eb.common.hw, 1590 [CLK_DCAM2ISP_IF_EB] = &dcam2isp_if_eb.common.hw, 1591 [CLK_ISP2DCAM_IF_EB] = &isp2dcam_if_eb.common.hw, 1592 [CLK_ISP_LCLK_EB] = &isp_lclk_eb.common.hw, 1593 [CLK_ISP_ICLK_EB] = &isp_iclk_eb.common.hw, 1594 [CLK_ISP_MCLK_EB] = &isp_mclk_eb.common.hw, 1595 [CLK_ISP_PCLK_EB] = &isp_pclk_eb.common.hw, 1596 [CLK_ISP_ISP2DCAM_EB] = &isp_isp2dcam_eb.common.hw, 1597 [CLK_DCAM0_IF_EB] = &dcam0_if_eb.common.hw, 1598 [CLK_CLK26M_IF_EB] = &clk26m_if_eb.common.hw, 1599 [CLK_CPHY0_GATE] = &cphy0_gate.common.hw, 1600 [CLK_MIPI_CSI0_GATE] = &mipi_csi0_gate.common.hw, 1601 [CLK_CPHY1_GATE] = &cphy1_gate.common.hw, 1602 [CLK_MIPI_CSI1] = &mipi_csi1.common.hw, 1603 [CLK_DCAM0_AXI_GATE] = &dcam0_axi_gate.common.hw, 1604 [CLK_DCAM1_AXI_GATE] = &dcam1_axi_gate.common.hw, 1605 [CLK_SENSOR0_GATE] = &sensor0_gate.common.hw, 1606 [CLK_SENSOR1_GATE] = &sensor1_gate.common.hw, 1607 [CLK_JPG0_AXI_GATE] = &jpg0_axi_gate.common.hw, 1608 [CLK_GPG1_AXI_GATE] = &gpg1_axi_gate.common.hw, 1609 [CLK_ISP0_AXI_GATE] = &isp0_axi_gate.common.hw, 1610 [CLK_ISP1_AXI_GATE] = &isp1_axi_gate.common.hw, 1611 [CLK_ISP2_AXI_GATE] = &isp2_axi_gate.common.hw, 1612 [CLK_CPP_AXI_GATE] = &cpp_axi_gate.common.hw, 1613 [CLK_D0_IF_AXI_GATE] = &d0_if_axi_gate.common.hw, 1614 [CLK_D2I_IF_AXI_GATE] = &d2i_if_axi_gate.common.hw, 1615 [CLK_I2D_IF_AXI_GATE] = &i2d_if_axi_gate.common.hw, 1616 [CLK_SPARE_AXI_GATE] = &spare_axi_gate.common.hw, 1617 [CLK_SENSOR2_GATE] = &sensor2_gate.common.hw, 1618 [CLK_D0IF_IN_D_EN] = &d0if_in_d_en.common.hw, 1619 [CLK_D1IF_IN_D_EN] = &d1if_in_d_en.common.hw, 1620 [CLK_D0IF_IN_D2I_EN] = &d0if_in_d2i_en.common.hw, 1621 [CLK_D1IF_IN_D2I_EN] = &d1if_in_d2i_en.common.hw, 1622 [CLK_IA_IN_D2I_EN] = &ia_in_d2i_en.common.hw, 1623 [CLK_IB_IN_D2I_EN] = &ib_in_d2i_en.common.hw, 1624 [CLK_IC_IN_D2I_EN] = &ic_in_d2i_en.common.hw, 1625 [CLK_IA_IN_I_EN] = &ia_in_i_en.common.hw, 1626 [CLK_IB_IN_I_EN] = &ib_in_i_en.common.hw, 1627 [CLK_IC_IN_I_EN] = &ic_in_i_en.common.hw, 1628 }, 1629 .num = CLK_CAM_GATE_NUM, 1630 }; 1631 1632 static const struct sprd_clk_desc sc9860_cam_gate_desc = { 1633 .clk_clks = sc9860_cam_gate, 1634 .num_clk_clks = ARRAY_SIZE(sc9860_cam_gate), 1635 .hw_clks = &sc9860_cam_gate_hws, 1636 }; 1637 1638 static SPRD_MUX_CLK(ahb_disp, "ahb-disp", ahb_parents, 0x20, 1639 0, 2, SC9860_MUX_FLAG); 1640 static SPRD_COMP_CLK(dispc0_dpi, "dispc0-dpi", dispc_parents, 0x34, 1641 0, 2, 8, 2, 0); 1642 static SPRD_COMP_CLK(dispc1_dpi, "dispc1-dpi", dispc_parents, 0x40, 1643 0, 2, 8, 2, 0); 1644 1645 static struct sprd_clk_common *sc9860_disp_clk[] = { 1646 /* address base is 0x63000000 */ 1647 &ahb_disp.common, 1648 &dispc0_dpi.common, 1649 &dispc1_dpi.common, 1650 }; 1651 1652 static struct clk_hw_onecell_data sc9860_disp_clk_hws = { 1653 .hws = { 1654 [CLK_AHB_DISP] = &ahb_disp.common.hw, 1655 [CLK_DISPC0_DPI] = &dispc0_dpi.common.hw, 1656 [CLK_DISPC1_DPI] = &dispc1_dpi.common.hw, 1657 }, 1658 .num = CLK_DISP_NUM, 1659 }; 1660 1661 static const struct sprd_clk_desc sc9860_disp_clk_desc = { 1662 .clk_clks = sc9860_disp_clk, 1663 .num_clk_clks = ARRAY_SIZE(sc9860_disp_clk), 1664 .hw_clks = &sc9860_disp_clk_hws, 1665 }; 1666 1667 static SPRD_SC_GATE_CLK(dispc0_eb, "dispc0-eb", "ahb-disp", 0x0, 1668 0x1000, BIT(0), 0, 0); 1669 static SPRD_SC_GATE_CLK(dispc1_eb, "dispc1-eb", "ahb-disp", 0x0, 1670 0x1000, BIT(1), 0, 0); 1671 static SPRD_SC_GATE_CLK(dispc_mmu_eb, "dispc-mmu-eb", "ahb-disp", 0x0, 1672 0x1000, BIT(2), 0, 0); 1673 static SPRD_SC_GATE_CLK(gsp0_eb, "gsp0-eb", "ahb-disp", 0x0, 1674 0x1000, BIT(3), 0, 0); 1675 static SPRD_SC_GATE_CLK(gsp1_eb, "gsp1-eb", "ahb-disp", 0x0, 1676 0x1000, BIT(4), 0, 0); 1677 static SPRD_SC_GATE_CLK(gsp0_mmu_eb, "gsp0-mmu-eb", "ahb-disp", 0x0, 1678 0x1000, BIT(5), 0, 0); 1679 static SPRD_SC_GATE_CLK(gsp1_mmu_eb, "gsp1-mmu-eb", "ahb-disp", 0x0, 1680 0x1000, BIT(6), 0, 0); 1681 static SPRD_SC_GATE_CLK(dsi0_eb, "dsi0-eb", "ahb-disp", 0x0, 1682 0x1000, BIT(7), 0, 0); 1683 static SPRD_SC_GATE_CLK(dsi1_eb, "dsi1-eb", "ahb-disp", 0x0, 1684 0x1000, BIT(8), 0, 0); 1685 static SPRD_SC_GATE_CLK(disp_ckg_eb, "disp-ckg-eb", "ahb-disp", 0x0, 1686 0x1000, BIT(9), 0, 0); 1687 static SPRD_SC_GATE_CLK(disp_gpu_eb, "disp-gpu-eb", "ahb-disp", 0x0, 1688 0x1000, BIT(10), 0, 0); 1689 static SPRD_SC_GATE_CLK(gpu_mtx_eb, "gpu-mtx-eb", "ahb-disp", 0x0, 1690 0x1000, BIT(13), 0, 0); 1691 static SPRD_SC_GATE_CLK(gsp_mtx_eb, "gsp-mtx-eb", "ahb-disp", 0x0, 1692 0x1000, BIT(14), 0, 0); 1693 static SPRD_SC_GATE_CLK(tmc_mtx_eb, "tmc-mtx-eb", "ahb-disp", 0x0, 1694 0x1000, BIT(15), 0, 0); 1695 static SPRD_SC_GATE_CLK(dispc_mtx_eb, "dispc-mtx-eb", "ahb-disp", 0x0, 1696 0x1000, BIT(16), 0, 0); 1697 static SPRD_GATE_CLK(dphy0_gate, "dphy0-gate", "ahb-disp", 0x8, 1698 BIT(0), 0, 0); 1699 static SPRD_GATE_CLK(dphy1_gate, "dphy1-gate", "ahb-disp", 0x8, 1700 BIT(1), 0, 0); 1701 static SPRD_GATE_CLK(gsp0_a_gate, "gsp0-a-gate", "ahb-disp", 0x8, 1702 BIT(2), 0, 0); 1703 static SPRD_GATE_CLK(gsp1_a_gate, "gsp1-a-gate", "ahb-disp", 0x8, 1704 BIT(3), 0, 0); 1705 static SPRD_GATE_CLK(gsp0_f_gate, "gsp0-f-gate", "ahb-disp", 0x8, 1706 BIT(4), 0, 0); 1707 static SPRD_GATE_CLK(gsp1_f_gate, "gsp1-f-gate", "ahb-disp", 0x8, 1708 BIT(5), 0, 0); 1709 static SPRD_GATE_CLK(d_mtx_f_gate, "d-mtx-f-gate", "ahb-disp", 0x8, 1710 BIT(6), 0, 0); 1711 static SPRD_GATE_CLK(d_mtx_a_gate, "d-mtx-a-gate", "ahb-disp", 0x8, 1712 BIT(7), 0, 0); 1713 static SPRD_GATE_CLK(d_noc_f_gate, "d-noc-f-gate", "ahb-disp", 0x8, 1714 BIT(8), 0, 0); 1715 static SPRD_GATE_CLK(d_noc_a_gate, "d-noc-a-gate", "ahb-disp", 0x8, 1716 BIT(9), 0, 0); 1717 static SPRD_GATE_CLK(gsp_mtx_f_gate, "gsp-mtx-f-gate", "ahb-disp", 0x8, 1718 BIT(10), 0, 0); 1719 static SPRD_GATE_CLK(gsp_mtx_a_gate, "gsp-mtx-a-gate", "ahb-disp", 0x8, 1720 BIT(11), 0, 0); 1721 static SPRD_GATE_CLK(gsp_noc_f_gate, "gsp-noc-f-gate", "ahb-disp", 0x8, 1722 BIT(12), 0, 0); 1723 static SPRD_GATE_CLK(gsp_noc_a_gate, "gsp-noc-a-gate", "ahb-disp", 0x8, 1724 BIT(13), 0, 0); 1725 static SPRD_GATE_CLK(dispm0idle_gate, "dispm0idle-gate", "ahb-disp", 0x8, 1726 BIT(14), 0, 0); 1727 static SPRD_GATE_CLK(gspm0idle_gate, "gspm0idle-gate", "ahb-disp", 0x8, 1728 BIT(15), 0, 0); 1729 1730 static struct sprd_clk_common *sc9860_disp_gate[] = { 1731 /* address base is 0x63100000 */ 1732 &dispc0_eb.common, 1733 &dispc1_eb.common, 1734 &dispc_mmu_eb.common, 1735 &gsp0_eb.common, 1736 &gsp1_eb.common, 1737 &gsp0_mmu_eb.common, 1738 &gsp1_mmu_eb.common, 1739 &dsi0_eb.common, 1740 &dsi1_eb.common, 1741 &disp_ckg_eb.common, 1742 &disp_gpu_eb.common, 1743 &gpu_mtx_eb.common, 1744 &gsp_mtx_eb.common, 1745 &tmc_mtx_eb.common, 1746 &dispc_mtx_eb.common, 1747 &dphy0_gate.common, 1748 &dphy1_gate.common, 1749 &gsp0_a_gate.common, 1750 &gsp1_a_gate.common, 1751 &gsp0_f_gate.common, 1752 &gsp1_f_gate.common, 1753 &d_mtx_f_gate.common, 1754 &d_mtx_a_gate.common, 1755 &d_noc_f_gate.common, 1756 &d_noc_a_gate.common, 1757 &gsp_mtx_f_gate.common, 1758 &gsp_mtx_a_gate.common, 1759 &gsp_noc_f_gate.common, 1760 &gsp_noc_a_gate.common, 1761 &dispm0idle_gate.common, 1762 &gspm0idle_gate.common, 1763 }; 1764 1765 static struct clk_hw_onecell_data sc9860_disp_gate_hws = { 1766 .hws = { 1767 [CLK_DISPC0_EB] = &dispc0_eb.common.hw, 1768 [CLK_DISPC1_EB] = &dispc1_eb.common.hw, 1769 [CLK_DISPC_MMU_EB] = &dispc_mmu_eb.common.hw, 1770 [CLK_GSP0_EB] = &gsp0_eb.common.hw, 1771 [CLK_GSP1_EB] = &gsp1_eb.common.hw, 1772 [CLK_GSP0_MMU_EB] = &gsp0_mmu_eb.common.hw, 1773 [CLK_GSP1_MMU_EB] = &gsp1_mmu_eb.common.hw, 1774 [CLK_DSI0_EB] = &dsi0_eb.common.hw, 1775 [CLK_DSI1_EB] = &dsi1_eb.common.hw, 1776 [CLK_DISP_CKG_EB] = &disp_ckg_eb.common.hw, 1777 [CLK_DISP_GPU_EB] = &disp_gpu_eb.common.hw, 1778 [CLK_GPU_MTX_EB] = &gpu_mtx_eb.common.hw, 1779 [CLK_GSP_MTX_EB] = &gsp_mtx_eb.common.hw, 1780 [CLK_TMC_MTX_EB] = &tmc_mtx_eb.common.hw, 1781 [CLK_DISPC_MTX_EB] = &dispc_mtx_eb.common.hw, 1782 [CLK_DPHY0_GATE] = &dphy0_gate.common.hw, 1783 [CLK_DPHY1_GATE] = &dphy1_gate.common.hw, 1784 [CLK_GSP0_A_GATE] = &gsp0_a_gate.common.hw, 1785 [CLK_GSP1_A_GATE] = &gsp1_a_gate.common.hw, 1786 [CLK_GSP0_F_GATE] = &gsp0_f_gate.common.hw, 1787 [CLK_GSP1_F_GATE] = &gsp1_f_gate.common.hw, 1788 [CLK_D_MTX_F_GATE] = &d_mtx_f_gate.common.hw, 1789 [CLK_D_MTX_A_GATE] = &d_mtx_a_gate.common.hw, 1790 [CLK_D_NOC_F_GATE] = &d_noc_f_gate.common.hw, 1791 [CLK_D_NOC_A_GATE] = &d_noc_a_gate.common.hw, 1792 [CLK_GSP_MTX_F_GATE] = &gsp_mtx_f_gate.common.hw, 1793 [CLK_GSP_MTX_A_GATE] = &gsp_mtx_a_gate.common.hw, 1794 [CLK_GSP_NOC_F_GATE] = &gsp_noc_f_gate.common.hw, 1795 [CLK_GSP_NOC_A_GATE] = &gsp_noc_a_gate.common.hw, 1796 [CLK_DISPM0IDLE_GATE] = &dispm0idle_gate.common.hw, 1797 [CLK_GSPM0IDLE_GATE] = &gspm0idle_gate.common.hw, 1798 }, 1799 .num = CLK_DISP_GATE_NUM, 1800 }; 1801 1802 static const struct sprd_clk_desc sc9860_disp_gate_desc = { 1803 .clk_clks = sc9860_disp_gate, 1804 .num_clk_clks = ARRAY_SIZE(sc9860_disp_gate), 1805 .hw_clks = &sc9860_disp_gate_hws, 1806 }; 1807 1808 static SPRD_SC_GATE_CLK(sim0_eb, "sim0-eb", "ap-apb", 0x0, 1809 0x1000, BIT(0), CLK_IGNORE_UNUSED, 0); 1810 static SPRD_SC_GATE_CLK(iis0_eb, "iis0-eb", "ap-apb", 0x0, 1811 0x1000, BIT(1), CLK_IGNORE_UNUSED, 0); 1812 static SPRD_SC_GATE_CLK(iis1_eb, "iis1-eb", "ap-apb", 0x0, 1813 0x1000, BIT(2), CLK_IGNORE_UNUSED, 0); 1814 static SPRD_SC_GATE_CLK(iis2_eb, "iis2-eb", "ap-apb", 0x0, 1815 0x1000, BIT(3), CLK_IGNORE_UNUSED, 0); 1816 static SPRD_SC_GATE_CLK(iis3_eb, "iis3-eb", "ap-apb", 0x0, 1817 0x1000, BIT(4), CLK_IGNORE_UNUSED, 0); 1818 static SPRD_SC_GATE_CLK(spi0_eb, "spi0-eb", "ap-apb", 0x0, 1819 0x1000, BIT(5), CLK_IGNORE_UNUSED, 0); 1820 static SPRD_SC_GATE_CLK(spi1_eb, "spi1-eb", "ap-apb", 0x0, 1821 0x1000, BIT(6), CLK_IGNORE_UNUSED, 0); 1822 static SPRD_SC_GATE_CLK(spi2_eb, "spi2-eb", "ap-apb", 0x0, 1823 0x1000, BIT(7), CLK_IGNORE_UNUSED, 0); 1824 static SPRD_SC_GATE_CLK(i2c0_eb, "i2c0-eb", "ap-apb", 0x0, 1825 0x1000, BIT(8), CLK_IGNORE_UNUSED, 0); 1826 static SPRD_SC_GATE_CLK(i2c1_eb, "i2c1-eb", "ap-apb", 0x0, 1827 0x1000, BIT(9), CLK_IGNORE_UNUSED, 0); 1828 static SPRD_SC_GATE_CLK(i2c2_eb, "i2c2-eb", "ap-apb", 0x0, 1829 0x1000, BIT(10), CLK_IGNORE_UNUSED, 0); 1830 static SPRD_SC_GATE_CLK(i2c3_eb, "i2c3-eb", "ap-apb", 0x0, 1831 0x1000, BIT(11), CLK_IGNORE_UNUSED, 0); 1832 static SPRD_SC_GATE_CLK(i2c4_eb, "i2c4-eb", "ap-apb", 0x0, 1833 0x1000, BIT(12), CLK_IGNORE_UNUSED, 0); 1834 static SPRD_SC_GATE_CLK(i2c5_eb, "i2c5-eb", "ap-apb", 0x0, 1835 0x1000, BIT(13), CLK_IGNORE_UNUSED, 0); 1836 static SPRD_SC_GATE_CLK(uart0_eb, "uart0-eb", "ap-apb", 0x0, 1837 0x1000, BIT(14), CLK_IGNORE_UNUSED, 0); 1838 static SPRD_SC_GATE_CLK(uart1_eb, "uart1-eb", "ap-apb", 0x0, 1839 0x1000, BIT(15), CLK_IGNORE_UNUSED, 0); 1840 static SPRD_SC_GATE_CLK(uart2_eb, "uart2-eb", "ap-apb", 0x0, 1841 0x1000, BIT(16), CLK_IGNORE_UNUSED, 0); 1842 static SPRD_SC_GATE_CLK(uart3_eb, "uart3-eb", "ap-apb", 0x0, 1843 0x1000, BIT(17), CLK_IGNORE_UNUSED, 0); 1844 static SPRD_SC_GATE_CLK(uart4_eb, "uart4-eb", "ap-apb", 0x0, 1845 0x1000, BIT(18), CLK_IGNORE_UNUSED, 0); 1846 static SPRD_SC_GATE_CLK(ap_ckg_eb, "ap-ckg-eb", "ap-apb", 0x0, 1847 0x1000, BIT(19), CLK_IGNORE_UNUSED, 0); 1848 static SPRD_SC_GATE_CLK(spi3_eb, "spi3-eb", "ap-apb", 0x0, 1849 0x1000, BIT(20), CLK_IGNORE_UNUSED, 0); 1850 1851 static struct sprd_clk_common *sc9860_apapb_gate[] = { 1852 /* address base is 0x70b00000 */ 1853 &sim0_eb.common, 1854 &iis0_eb.common, 1855 &iis1_eb.common, 1856 &iis2_eb.common, 1857 &iis3_eb.common, 1858 &spi0_eb.common, 1859 &spi1_eb.common, 1860 &spi2_eb.common, 1861 &i2c0_eb.common, 1862 &i2c1_eb.common, 1863 &i2c2_eb.common, 1864 &i2c3_eb.common, 1865 &i2c4_eb.common, 1866 &i2c5_eb.common, 1867 &uart0_eb.common, 1868 &uart1_eb.common, 1869 &uart2_eb.common, 1870 &uart3_eb.common, 1871 &uart4_eb.common, 1872 &ap_ckg_eb.common, 1873 &spi3_eb.common, 1874 }; 1875 1876 static struct clk_hw_onecell_data sc9860_apapb_gate_hws = { 1877 .hws = { 1878 [CLK_SIM0_EB] = &sim0_eb.common.hw, 1879 [CLK_IIS0_EB] = &iis0_eb.common.hw, 1880 [CLK_IIS1_EB] = &iis1_eb.common.hw, 1881 [CLK_IIS2_EB] = &iis2_eb.common.hw, 1882 [CLK_IIS3_EB] = &iis3_eb.common.hw, 1883 [CLK_SPI0_EB] = &spi0_eb.common.hw, 1884 [CLK_SPI1_EB] = &spi1_eb.common.hw, 1885 [CLK_SPI2_EB] = &spi2_eb.common.hw, 1886 [CLK_I2C0_EB] = &i2c0_eb.common.hw, 1887 [CLK_I2C1_EB] = &i2c1_eb.common.hw, 1888 [CLK_I2C2_EB] = &i2c2_eb.common.hw, 1889 [CLK_I2C3_EB] = &i2c3_eb.common.hw, 1890 [CLK_I2C4_EB] = &i2c4_eb.common.hw, 1891 [CLK_I2C5_EB] = &i2c5_eb.common.hw, 1892 [CLK_UART0_EB] = &uart0_eb.common.hw, 1893 [CLK_UART1_EB] = &uart1_eb.common.hw, 1894 [CLK_UART2_EB] = &uart2_eb.common.hw, 1895 [CLK_UART3_EB] = &uart3_eb.common.hw, 1896 [CLK_UART4_EB] = &uart4_eb.common.hw, 1897 [CLK_AP_CKG_EB] = &ap_ckg_eb.common.hw, 1898 [CLK_SPI3_EB] = &spi3_eb.common.hw, 1899 }, 1900 .num = CLK_APAPB_GATE_NUM, 1901 }; 1902 1903 static const struct sprd_clk_desc sc9860_apapb_gate_desc = { 1904 .clk_clks = sc9860_apapb_gate, 1905 .num_clk_clks = ARRAY_SIZE(sc9860_apapb_gate), 1906 .hw_clks = &sc9860_apapb_gate_hws, 1907 }; 1908 1909 static const struct of_device_id sprd_sc9860_clk_ids[] = { 1910 { .compatible = "sprd,sc9860-pmu-gate", /* 0x402b */ 1911 .data = &sc9860_pmu_gate_desc }, 1912 { .compatible = "sprd,sc9860-pll", /* 0x4040 */ 1913 .data = &sc9860_pll_desc }, 1914 { .compatible = "sprd,sc9860-ap-clk", /* 0x2000 */ 1915 .data = &sc9860_ap_clk_desc }, 1916 { .compatible = "sprd,sc9860-aon-prediv", /* 0x402d */ 1917 .data = &sc9860_aon_prediv_desc }, 1918 { .compatible = "sprd,sc9860-apahb-gate", /* 0x2021 */ 1919 .data = &sc9860_apahb_gate_desc }, 1920 { .compatible = "sprd,sc9860-aon-gate", /* 0x402e */ 1921 .data = &sc9860_aon_gate_desc }, 1922 { .compatible = "sprd,sc9860-aonsecure-clk", /* 0x4088 */ 1923 .data = &sc9860_aonsecure_clk_desc }, 1924 { .compatible = "sprd,sc9860-agcp-gate", /* 0x415e */ 1925 .data = &sc9860_agcp_gate_desc }, 1926 { .compatible = "sprd,sc9860-gpu-clk", /* 0x6020 */ 1927 .data = &sc9860_gpu_clk_desc }, 1928 { .compatible = "sprd,sc9860-vsp-clk", /* 0x6100 */ 1929 .data = &sc9860_vsp_clk_desc }, 1930 { .compatible = "sprd,sc9860-vsp-gate", /* 0x6110 */ 1931 .data = &sc9860_vsp_gate_desc }, 1932 { .compatible = "sprd,sc9860-cam-clk", /* 0x6200 */ 1933 .data = &sc9860_cam_clk_desc }, 1934 { .compatible = "sprd,sc9860-cam-gate", /* 0x6210 */ 1935 .data = &sc9860_cam_gate_desc }, 1936 { .compatible = "sprd,sc9860-disp-clk", /* 0x6300 */ 1937 .data = &sc9860_disp_clk_desc }, 1938 { .compatible = "sprd,sc9860-disp-gate", /* 0x6310 */ 1939 .data = &sc9860_disp_gate_desc }, 1940 { .compatible = "sprd,sc9860-apapb-gate", /* 0x70b0 */ 1941 .data = &sc9860_apapb_gate_desc }, 1942 { } 1943 }; 1944 MODULE_DEVICE_TABLE(of, sprd_sc9860_clk_ids); 1945 1946 static int sc9860_clk_probe(struct platform_device *pdev) 1947 { 1948 const struct of_device_id *match; 1949 const struct sprd_clk_desc *desc; 1950 1951 match = of_match_node(sprd_sc9860_clk_ids, pdev->dev.of_node); 1952 if (!match) { 1953 pr_err("%s: of_match_node() failed", __func__); 1954 return -ENODEV; 1955 } 1956 1957 desc = match->data; 1958 sprd_clk_regmap_init(pdev, desc); 1959 1960 return sprd_clk_probe(&pdev->dev, desc->hw_clks); 1961 } 1962 1963 static struct platform_driver sc9860_clk_driver = { 1964 .probe = sc9860_clk_probe, 1965 .driver = { 1966 .name = "sc9860-clk", 1967 .of_match_table = sprd_sc9860_clk_ids, 1968 }, 1969 }; 1970 module_platform_driver(sc9860_clk_driver); 1971 1972 MODULE_DESCRIPTION("Spreadtrum SC9860 Clock Driver"); 1973 MODULE_LICENSE("GPL v2"); 1974 MODULE_ALIAS("platform:sc9860-clk"); 1975