1 /* SPDX-License-Identifier: GPL-2.0 */ 2 // 3 // Spreadtrum divider clock driver 4 // 5 // Copyright (C) 2017 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com> 7 8 #ifndef _SPRD_DIV_H_ 9 #define _SPRD_DIV_H_ 10 11 #include "common.h" 12 13 /** 14 * struct sprd_div_internal - Internal divider description 15 * @shift: Bit offset of the divider in its register 16 * @width: Width of the divider field in its register 17 * 18 * That structure represents a single divider, and is meant to be 19 * embedded in other structures representing the various clock 20 * classes. 21 */ 22 struct sprd_div_internal { 23 u8 shift; 24 u8 width; 25 }; 26 27 #define _SPRD_DIV_CLK(_shift, _width) \ 28 { \ 29 .shift = _shift, \ 30 .width = _width, \ 31 } 32 33 struct sprd_div { 34 struct sprd_div_internal div; 35 struct sprd_clk_common common; 36 }; 37 38 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ 39 _shift, _width, _flags) \ 40 struct sprd_div _struct = { \ 41 .div = _SPRD_DIV_CLK(_shift, _width), \ 42 .common = { \ 43 .regmap = NULL, \ 44 .reg = _reg, \ 45 .hw.init = CLK_HW_INIT(_name, \ 46 _parent, \ 47 &sprd_div_ops, \ 48 _flags), \ 49 } \ 50 } 51 52 static inline struct sprd_div *hw_to_sprd_div(const struct clk_hw *hw) 53 { 54 struct sprd_clk_common *common = hw_to_sprd_clk_common(hw); 55 56 return container_of(common, struct sprd_div, common); 57 } 58 59 long sprd_div_helper_round_rate(struct sprd_clk_common *common, 60 const struct sprd_div_internal *div, 61 unsigned long rate, 62 unsigned long *parent_rate); 63 64 unsigned long sprd_div_helper_recalc_rate(struct sprd_clk_common *common, 65 const struct sprd_div_internal *div, 66 unsigned long parent_rate); 67 68 int sprd_div_helper_set_rate(const struct sprd_clk_common *common, 69 const struct sprd_div_internal *div, 70 unsigned long rate, 71 unsigned long parent_rate); 72 73 extern const struct clk_ops sprd_div_ops; 74 75 #endif /* _SPRD_DIV_H_ */ 76