1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPEAr6xx machines clock framework source file 4 * 5 * Copyright (C) 2012 ST Microelectronics 6 * Viresh Kumar <vireshk@kernel.org> 7 */ 8 9 #include <linux/clkdev.h> 10 #include <linux/io.h> 11 #include <linux/spinlock_types.h> 12 #include "clk.h" 13 14 static DEFINE_SPINLOCK(_lock); 15 16 #define PLL1_CTR (misc_base + 0x008) 17 #define PLL1_FRQ (misc_base + 0x00C) 18 #define PLL2_CTR (misc_base + 0x014) 19 #define PLL2_FRQ (misc_base + 0x018) 20 #define PLL_CLK_CFG (misc_base + 0x020) 21 /* PLL_CLK_CFG register masks */ 22 #define MCTR_CLK_SHIFT 28 23 #define MCTR_CLK_MASK 3 24 25 #define CORE_CLK_CFG (misc_base + 0x024) 26 /* CORE CLK CFG register masks */ 27 #define HCLK_RATIO_SHIFT 10 28 #define HCLK_RATIO_MASK 2 29 #define PCLK_RATIO_SHIFT 8 30 #define PCLK_RATIO_MASK 2 31 32 #define PERIP_CLK_CFG (misc_base + 0x028) 33 /* PERIP_CLK_CFG register masks */ 34 #define CLCD_CLK_SHIFT 2 35 #define CLCD_CLK_MASK 2 36 #define UART_CLK_SHIFT 4 37 #define UART_CLK_MASK 1 38 #define FIRDA_CLK_SHIFT 5 39 #define FIRDA_CLK_MASK 2 40 #define GPT0_CLK_SHIFT 8 41 #define GPT1_CLK_SHIFT 10 42 #define GPT2_CLK_SHIFT 11 43 #define GPT3_CLK_SHIFT 12 44 #define GPT_CLK_MASK 1 45 46 #define PERIP1_CLK_ENB (misc_base + 0x02C) 47 /* PERIP1_CLK_ENB register masks */ 48 #define UART0_CLK_ENB 3 49 #define UART1_CLK_ENB 4 50 #define SSP0_CLK_ENB 5 51 #define SSP1_CLK_ENB 6 52 #define I2C_CLK_ENB 7 53 #define JPEG_CLK_ENB 8 54 #define FSMC_CLK_ENB 9 55 #define FIRDA_CLK_ENB 10 56 #define GPT2_CLK_ENB 11 57 #define GPT3_CLK_ENB 12 58 #define GPIO2_CLK_ENB 13 59 #define SSP2_CLK_ENB 14 60 #define ADC_CLK_ENB 15 61 #define GPT1_CLK_ENB 11 62 #define RTC_CLK_ENB 17 63 #define GPIO1_CLK_ENB 18 64 #define DMA_CLK_ENB 19 65 #define SMI_CLK_ENB 21 66 #define CLCD_CLK_ENB 22 67 #define GMAC_CLK_ENB 23 68 #define USBD_CLK_ENB 24 69 #define USBH0_CLK_ENB 25 70 #define USBH1_CLK_ENB 26 71 72 #define PRSC0_CLK_CFG (misc_base + 0x044) 73 #define PRSC1_CLK_CFG (misc_base + 0x048) 74 #define PRSC2_CLK_CFG (misc_base + 0x04C) 75 76 #define CLCD_CLK_SYNT (misc_base + 0x05C) 77 #define FIRDA_CLK_SYNT (misc_base + 0x060) 78 #define UART_CLK_SYNT (misc_base + 0x064) 79 80 /* vco rate configuration table, in ascending order of rates */ 81 static struct pll_rate_tbl pll_rtbl[] = { 82 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */ 83 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */ 84 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */ 85 }; 86 87 /* aux rate configuration table, in ascending order of rates */ 88 static struct aux_rate_tbl aux_rtbl[] = { 89 /* For PLL1 = 332 MHz */ 90 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ 91 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ 92 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ 93 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ 94 }; 95 96 static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", }; 97 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", }; 98 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", }; 99 static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", }; 100 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; 101 static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", }; 102 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", 103 "pll2_clk", }; 104 105 /* gpt rate configuration table, in ascending order of rates */ 106 static struct gpt_rate_tbl gpt_rtbl[] = { 107 /* For pll1 = 332 MHz */ 108 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ 109 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ 110 {.mscale = 1, .nscale = 0}, /* 83 MHz */ 111 }; 112 113 void __init spear6xx_clk_init(void __iomem *misc_base) 114 { 115 struct clk *clk, *clk1; 116 117 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); 118 clk_register_clkdev(clk, "osc_32k_clk", NULL); 119 120 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); 121 clk_register_clkdev(clk, "osc_30m_clk", NULL); 122 123 /* clock derived from 32 KHz osc clk */ 124 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, 125 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); 126 clk_register_clkdev(clk, NULL, "rtc-spear"); 127 128 /* clock derived from 30 MHz osc clk */ 129 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, 130 48000000); 131 clk_register_clkdev(clk, "pll3_clk", NULL); 132 133 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", 134 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 135 &_lock, &clk1, NULL); 136 clk_register_clkdev(clk, "vco1_clk", NULL); 137 clk_register_clkdev(clk1, "pll1_clk", NULL); 138 139 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk", 140 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 141 &_lock, &clk1, NULL); 142 clk_register_clkdev(clk, "vco2_clk", NULL); 143 clk_register_clkdev(clk1, "pll2_clk", NULL); 144 145 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 146 1); 147 clk_register_clkdev(clk, NULL, "fc880000.wdt"); 148 149 /* clock derived from pll1 clk */ 150 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 151 CLK_SET_RATE_PARENT, 1, 1); 152 clk_register_clkdev(clk, "cpu_clk", NULL); 153 154 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 155 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 156 HCLK_RATIO_MASK, 0, &_lock); 157 clk_register_clkdev(clk, "ahb_clk", NULL); 158 159 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, 160 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 161 &_lock, &clk1); 162 clk_register_clkdev(clk, "uart_syn_clk", NULL); 163 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 164 165 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, 166 ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT, 167 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, 168 &_lock); 169 clk_register_clkdev(clk, "uart_mclk", NULL); 170 171 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, 172 UART0_CLK_ENB, 0, &_lock); 173 clk_register_clkdev(clk, NULL, "d0000000.serial"); 174 175 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, 176 UART1_CLK_ENB, 0, &_lock); 177 clk_register_clkdev(clk, NULL, "d0080000.serial"); 178 179 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 180 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 181 &_lock, &clk1); 182 clk_register_clkdev(clk, "firda_syn_clk", NULL); 183 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 184 185 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 186 ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT, 187 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, 188 &_lock); 189 clk_register_clkdev(clk, "firda_mclk", NULL); 190 191 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, 192 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 193 clk_register_clkdev(clk, NULL, "firda"); 194 195 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk", 196 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 197 &_lock, &clk1); 198 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 199 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL); 200 201 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, 202 ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT, 203 PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, 204 &_lock); 205 clk_register_clkdev(clk, "clcd_mclk", NULL); 206 207 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, 208 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); 209 clk_register_clkdev(clk, NULL, "clcd"); 210 211 /* gpt clocks */ 212 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, 213 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 214 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); 215 216 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, 217 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT, 218 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 219 clk_register_clkdev(clk, NULL, "gpt0"); 220 221 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, 222 ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT, 223 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 224 clk_register_clkdev(clk, "gpt1_mclk", NULL); 225 226 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 227 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 228 clk_register_clkdev(clk, NULL, "gpt1"); 229 230 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, 231 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 232 clk_register_clkdev(clk, "gpt2_syn_clk", NULL); 233 234 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 235 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT, 236 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 237 clk_register_clkdev(clk, "gpt2_mclk", NULL); 238 239 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 240 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 241 clk_register_clkdev(clk, NULL, "gpt2"); 242 243 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, 244 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 245 clk_register_clkdev(clk, "gpt3_syn_clk", NULL); 246 247 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, 248 ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT, 249 PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 250 clk_register_clkdev(clk, "gpt3_mclk", NULL); 251 252 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 253 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); 254 clk_register_clkdev(clk, NULL, "gpt3"); 255 256 /* clock derived from pll3 clk */ 257 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, 258 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); 259 clk_register_clkdev(clk, NULL, "e1800000.ehci"); 260 clk_register_clkdev(clk, NULL, "e1900000.ohci"); 261 262 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, 263 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); 264 clk_register_clkdev(clk, NULL, "e2000000.ehci"); 265 clk_register_clkdev(clk, NULL, "e2100000.ohci"); 266 267 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 268 USBD_CLK_ENB, 0, &_lock); 269 clk_register_clkdev(clk, NULL, "designware_udc"); 270 271 /* clock derived from ahb clk */ 272 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 273 1); 274 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 275 276 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 277 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT, 278 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock); 279 clk_register_clkdev(clk, "ddr_clk", NULL); 280 281 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 282 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, 283 PCLK_RATIO_MASK, 0, &_lock); 284 clk_register_clkdev(clk, "apb_clk", NULL); 285 286 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 287 DMA_CLK_ENB, 0, &_lock); 288 clk_register_clkdev(clk, NULL, "fc400000.dma"); 289 290 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 291 FSMC_CLK_ENB, 0, &_lock); 292 clk_register_clkdev(clk, NULL, "d1800000.flash"); 293 294 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 295 GMAC_CLK_ENB, 0, &_lock); 296 clk_register_clkdev(clk, NULL, "e0800000.ethernet"); 297 298 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 299 I2C_CLK_ENB, 0, &_lock); 300 clk_register_clkdev(clk, NULL, "d0200000.i2c"); 301 302 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 303 JPEG_CLK_ENB, 0, &_lock); 304 clk_register_clkdev(clk, NULL, "jpeg"); 305 306 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 307 SMI_CLK_ENB, 0, &_lock); 308 clk_register_clkdev(clk, NULL, "fc000000.flash"); 309 310 /* clock derived from apb clk */ 311 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, 312 ADC_CLK_ENB, 0, &_lock); 313 clk_register_clkdev(clk, NULL, "d820b000.adc"); 314 315 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); 316 clk_register_clkdev(clk, NULL, "f0100000.gpio"); 317 318 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 319 GPIO1_CLK_ENB, 0, &_lock); 320 clk_register_clkdev(clk, NULL, "fc980000.gpio"); 321 322 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 323 GPIO2_CLK_ENB, 0, &_lock); 324 clk_register_clkdev(clk, NULL, "d8100000.gpio"); 325 326 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, 327 SSP0_CLK_ENB, 0, &_lock); 328 clk_register_clkdev(clk, NULL, "ssp-pl022.0"); 329 330 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 331 SSP1_CLK_ENB, 0, &_lock); 332 clk_register_clkdev(clk, NULL, "ssp-pl022.1"); 333 334 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 335 SSP2_CLK_ENB, 0, &_lock); 336 clk_register_clkdev(clk, NULL, "ssp-pl022.2"); 337 } 338