1 /* 2 * SPEAr6xx machines clock framework source file 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/io.h> 15 #include <linux/spinlock_types.h> 16 #include <mach/misc_regs.h> 17 #include "clk.h" 18 19 static DEFINE_SPINLOCK(_lock); 20 21 #define PLL1_CTR (MISC_BASE + 0x008) 22 #define PLL1_FRQ (MISC_BASE + 0x00C) 23 #define PLL2_CTR (MISC_BASE + 0x014) 24 #define PLL2_FRQ (MISC_BASE + 0x018) 25 #define PLL_CLK_CFG (MISC_BASE + 0x020) 26 /* PLL_CLK_CFG register masks */ 27 #define MCTR_CLK_SHIFT 28 28 #define MCTR_CLK_MASK 3 29 30 #define CORE_CLK_CFG (MISC_BASE + 0x024) 31 /* CORE CLK CFG register masks */ 32 #define HCLK_RATIO_SHIFT 10 33 #define HCLK_RATIO_MASK 2 34 #define PCLK_RATIO_SHIFT 8 35 #define PCLK_RATIO_MASK 2 36 37 #define PERIP_CLK_CFG (MISC_BASE + 0x028) 38 /* PERIP_CLK_CFG register masks */ 39 #define CLCD_CLK_SHIFT 2 40 #define CLCD_CLK_MASK 2 41 #define UART_CLK_SHIFT 4 42 #define UART_CLK_MASK 1 43 #define FIRDA_CLK_SHIFT 5 44 #define FIRDA_CLK_MASK 2 45 #define GPT0_CLK_SHIFT 8 46 #define GPT1_CLK_SHIFT 10 47 #define GPT2_CLK_SHIFT 11 48 #define GPT3_CLK_SHIFT 12 49 #define GPT_CLK_MASK 1 50 51 #define PERIP1_CLK_ENB (MISC_BASE + 0x02C) 52 /* PERIP1_CLK_ENB register masks */ 53 #define UART0_CLK_ENB 3 54 #define UART1_CLK_ENB 4 55 #define SSP0_CLK_ENB 5 56 #define SSP1_CLK_ENB 6 57 #define I2C_CLK_ENB 7 58 #define JPEG_CLK_ENB 8 59 #define FSMC_CLK_ENB 9 60 #define FIRDA_CLK_ENB 10 61 #define GPT2_CLK_ENB 11 62 #define GPT3_CLK_ENB 12 63 #define GPIO2_CLK_ENB 13 64 #define SSP2_CLK_ENB 14 65 #define ADC_CLK_ENB 15 66 #define GPT1_CLK_ENB 11 67 #define RTC_CLK_ENB 17 68 #define GPIO1_CLK_ENB 18 69 #define DMA_CLK_ENB 19 70 #define SMI_CLK_ENB 21 71 #define CLCD_CLK_ENB 22 72 #define GMAC_CLK_ENB 23 73 #define USBD_CLK_ENB 24 74 #define USBH0_CLK_ENB 25 75 #define USBH1_CLK_ENB 26 76 77 #define PRSC0_CLK_CFG (MISC_BASE + 0x044) 78 #define PRSC1_CLK_CFG (MISC_BASE + 0x048) 79 #define PRSC2_CLK_CFG (MISC_BASE + 0x04C) 80 81 #define CLCD_CLK_SYNT (MISC_BASE + 0x05C) 82 #define FIRDA_CLK_SYNT (MISC_BASE + 0x060) 83 #define UART_CLK_SYNT (MISC_BASE + 0x064) 84 85 /* vco rate configuration table, in ascending order of rates */ 86 static struct pll_rate_tbl pll_rtbl[] = { 87 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */ 88 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */ 89 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */ 90 }; 91 92 /* aux rate configuration table, in ascending order of rates */ 93 static struct aux_rate_tbl aux_rtbl[] = { 94 /* For PLL1 = 332 MHz */ 95 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ 96 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ 97 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ 98 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ 99 }; 100 101 static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", }; 102 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", }; 103 static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", }; 104 static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", }; 105 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; 106 static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", }; 107 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", 108 "pll2_clk", }; 109 110 /* gpt rate configuration table, in ascending order of rates */ 111 static struct gpt_rate_tbl gpt_rtbl[] = { 112 /* For pll1 = 332 MHz */ 113 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ 114 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ 115 {.mscale = 1, .nscale = 0}, /* 83 MHz */ 116 }; 117 118 void __init spear6xx_clk_init(void) 119 { 120 struct clk *clk, *clk1; 121 122 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 123 32000); 124 clk_register_clkdev(clk, "osc_32k_clk", NULL); 125 126 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, 127 30000000); 128 clk_register_clkdev(clk, "osc_30m_clk", NULL); 129 130 /* clock derived from 32 KHz osc clk */ 131 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, 132 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); 133 clk_register_clkdev(clk, NULL, "rtc-spear"); 134 135 /* clock derived from 30 MHz osc clk */ 136 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, 137 48000000); 138 clk_register_clkdev(clk, "pll3_clk", NULL); 139 140 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", 141 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 142 &_lock, &clk1, NULL); 143 clk_register_clkdev(clk, "vco1_clk", NULL); 144 clk_register_clkdev(clk1, "pll1_clk", NULL); 145 146 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk", 147 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 148 &_lock, &clk1, NULL); 149 clk_register_clkdev(clk, "vco2_clk", NULL); 150 clk_register_clkdev(clk1, "pll2_clk", NULL); 151 152 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 153 1); 154 clk_register_clkdev(clk, NULL, "wdt"); 155 156 /* clock derived from pll1 clk */ 157 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 158 CLK_SET_RATE_PARENT, 1, 1); 159 clk_register_clkdev(clk, "cpu_clk", NULL); 160 161 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 162 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 163 HCLK_RATIO_MASK, 0, &_lock); 164 clk_register_clkdev(clk, "ahb_clk", NULL); 165 166 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, 167 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 168 &_lock, &clk1); 169 clk_register_clkdev(clk, "uart_syn_clk", NULL); 170 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 171 172 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, 173 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, 174 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 175 clk_register_clkdev(clk, "uart_mclk", NULL); 176 177 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, 178 UART0_CLK_ENB, 0, &_lock); 179 clk_register_clkdev(clk, NULL, "d0000000.serial"); 180 181 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, 182 UART1_CLK_ENB, 0, &_lock); 183 clk_register_clkdev(clk, NULL, "d0080000.serial"); 184 185 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 186 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 187 &_lock, &clk1); 188 clk_register_clkdev(clk, "firda_syn_clk", NULL); 189 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 190 191 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 192 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 193 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 194 clk_register_clkdev(clk, "firda_mclk", NULL); 195 196 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, 197 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 198 clk_register_clkdev(clk, NULL, "firda"); 199 200 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk", 201 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 202 &_lock, &clk1); 203 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 204 clk_register_clkdev(clk1, "clcd_syn_gclk", NULL); 205 206 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, 207 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, 208 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); 209 clk_register_clkdev(clk, "clcd_mclk", NULL); 210 211 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, 212 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); 213 clk_register_clkdev(clk, NULL, "clcd"); 214 215 /* gpt clocks */ 216 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, 217 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 218 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); 219 220 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, 221 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 222 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 223 clk_register_clkdev(clk, NULL, "gpt0"); 224 225 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, 226 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 227 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 228 clk_register_clkdev(clk, "gpt1_mclk", NULL); 229 230 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 231 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 232 clk_register_clkdev(clk, NULL, "gpt1"); 233 234 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, 235 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 236 clk_register_clkdev(clk, "gpt2_syn_clk", NULL); 237 238 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 239 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 240 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 241 clk_register_clkdev(clk, "gpt2_mclk", NULL); 242 243 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 244 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 245 clk_register_clkdev(clk, NULL, "gpt2"); 246 247 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, 248 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 249 clk_register_clkdev(clk, "gpt3_syn_clk", NULL); 250 251 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, 252 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, 253 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 254 clk_register_clkdev(clk, "gpt3_mclk", NULL); 255 256 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, 257 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); 258 clk_register_clkdev(clk, NULL, "gpt3"); 259 260 /* clock derived from pll3 clk */ 261 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, 262 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); 263 clk_register_clkdev(clk, NULL, "e1800000.ehci"); 264 clk_register_clkdev(clk, NULL, "e1900000.ohci"); 265 266 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, 267 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); 268 clk_register_clkdev(clk, NULL, "e2000000.ehci"); 269 clk_register_clkdev(clk, NULL, "e2100000.ohci"); 270 271 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 272 USBD_CLK_ENB, 0, &_lock); 273 clk_register_clkdev(clk, NULL, "designware_udc"); 274 275 /* clock derived from ahb clk */ 276 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 277 1); 278 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 279 280 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 281 ARRAY_SIZE(ddr_parents), 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, 282 MCTR_CLK_MASK, 0, &_lock); 283 clk_register_clkdev(clk, "ddr_clk", NULL); 284 285 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 286 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, 287 PCLK_RATIO_MASK, 0, &_lock); 288 clk_register_clkdev(clk, "apb_clk", NULL); 289 290 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 291 DMA_CLK_ENB, 0, &_lock); 292 clk_register_clkdev(clk, NULL, "fc400000.dma"); 293 294 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 295 FSMC_CLK_ENB, 0, &_lock); 296 clk_register_clkdev(clk, NULL, "d1800000.flash"); 297 298 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 299 GMAC_CLK_ENB, 0, &_lock); 300 clk_register_clkdev(clk, NULL, "e0800000.ethernet"); 301 302 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 303 I2C_CLK_ENB, 0, &_lock); 304 clk_register_clkdev(clk, NULL, "d0200000.i2c"); 305 306 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 307 JPEG_CLK_ENB, 0, &_lock); 308 clk_register_clkdev(clk, NULL, "jpeg"); 309 310 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 311 SMI_CLK_ENB, 0, &_lock); 312 clk_register_clkdev(clk, NULL, "fc000000.flash"); 313 314 /* clock derived from apb clk */ 315 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, 316 ADC_CLK_ENB, 0, &_lock); 317 clk_register_clkdev(clk, NULL, "adc"); 318 319 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); 320 clk_register_clkdev(clk, NULL, "f0100000.gpio"); 321 322 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 323 GPIO1_CLK_ENB, 0, &_lock); 324 clk_register_clkdev(clk, NULL, "fc980000.gpio"); 325 326 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 327 GPIO2_CLK_ENB, 0, &_lock); 328 clk_register_clkdev(clk, NULL, "d8100000.gpio"); 329 330 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, 331 SSP0_CLK_ENB, 0, &_lock); 332 clk_register_clkdev(clk, NULL, "ssp-pl022.0"); 333 334 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 335 SSP1_CLK_ENB, 0, &_lock); 336 clk_register_clkdev(clk, NULL, "ssp-pl022.1"); 337 338 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 339 SSP2_CLK_ENB, 0, &_lock); 340 clk_register_clkdev(clk, NULL, "ssp-pl022.2"); 341 } 342