1 /* 2 * SPEAr6xx machines clock framework source file 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <viresh.kumar@st.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/io.h> 15 #include <linux/spinlock_types.h> 16 #include <mach/misc_regs.h> 17 #include "clk.h" 18 19 static DEFINE_SPINLOCK(_lock); 20 21 #define PLL1_CTR (MISC_BASE + 0x008) 22 #define PLL1_FRQ (MISC_BASE + 0x00C) 23 #define PLL2_CTR (MISC_BASE + 0x014) 24 #define PLL2_FRQ (MISC_BASE + 0x018) 25 #define PLL_CLK_CFG (MISC_BASE + 0x020) 26 /* PLL_CLK_CFG register masks */ 27 #define MCTR_CLK_SHIFT 28 28 #define MCTR_CLK_MASK 3 29 30 #define CORE_CLK_CFG (MISC_BASE + 0x024) 31 /* CORE CLK CFG register masks */ 32 #define HCLK_RATIO_SHIFT 10 33 #define HCLK_RATIO_MASK 2 34 #define PCLK_RATIO_SHIFT 8 35 #define PCLK_RATIO_MASK 2 36 37 #define PERIP_CLK_CFG (MISC_BASE + 0x028) 38 /* PERIP_CLK_CFG register masks */ 39 #define CLCD_CLK_SHIFT 2 40 #define CLCD_CLK_MASK 2 41 #define UART_CLK_SHIFT 4 42 #define UART_CLK_MASK 1 43 #define FIRDA_CLK_SHIFT 5 44 #define FIRDA_CLK_MASK 2 45 #define GPT0_CLK_SHIFT 8 46 #define GPT1_CLK_SHIFT 10 47 #define GPT2_CLK_SHIFT 11 48 #define GPT3_CLK_SHIFT 12 49 #define GPT_CLK_MASK 1 50 51 #define PERIP1_CLK_ENB (MISC_BASE + 0x02C) 52 /* PERIP1_CLK_ENB register masks */ 53 #define UART0_CLK_ENB 3 54 #define UART1_CLK_ENB 4 55 #define SSP0_CLK_ENB 5 56 #define SSP1_CLK_ENB 6 57 #define I2C_CLK_ENB 7 58 #define JPEG_CLK_ENB 8 59 #define FSMC_CLK_ENB 9 60 #define FIRDA_CLK_ENB 10 61 #define GPT2_CLK_ENB 11 62 #define GPT3_CLK_ENB 12 63 #define GPIO2_CLK_ENB 13 64 #define SSP2_CLK_ENB 14 65 #define ADC_CLK_ENB 15 66 #define GPT1_CLK_ENB 11 67 #define RTC_CLK_ENB 17 68 #define GPIO1_CLK_ENB 18 69 #define DMA_CLK_ENB 19 70 #define SMI_CLK_ENB 21 71 #define CLCD_CLK_ENB 22 72 #define GMAC_CLK_ENB 23 73 #define USBD_CLK_ENB 24 74 #define USBH0_CLK_ENB 25 75 #define USBH1_CLK_ENB 26 76 77 #define PRSC0_CLK_CFG (MISC_BASE + 0x044) 78 #define PRSC1_CLK_CFG (MISC_BASE + 0x048) 79 #define PRSC2_CLK_CFG (MISC_BASE + 0x04C) 80 81 #define CLCD_CLK_SYNT (MISC_BASE + 0x05C) 82 #define FIRDA_CLK_SYNT (MISC_BASE + 0x060) 83 #define UART_CLK_SYNT (MISC_BASE + 0x064) 84 85 /* vco rate configuration table, in ascending order of rates */ 86 static struct pll_rate_tbl pll_rtbl[] = { 87 {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */ 88 {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */ 89 {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */ 90 }; 91 92 /* aux rate configuration table, in ascending order of rates */ 93 static struct aux_rate_tbl aux_rtbl[] = { 94 /* For PLL1 = 332 MHz */ 95 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ 96 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ 97 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ 98 }; 99 100 static const char *clcd_parents[] = { "pll3_48m_clk", "clcd_synth_gate_clk", }; 101 static const char *firda_parents[] = { "pll3_48m_clk", "firda_synth_gate_clk", 102 }; 103 static const char *uart_parents[] = { "pll3_48m_clk", "uart_synth_gate_clk", }; 104 static const char *gpt0_1_parents[] = { "pll3_48m_clk", "gpt0_1_synth_clk", }; 105 static const char *gpt2_parents[] = { "pll3_48m_clk", "gpt2_synth_clk", }; 106 static const char *gpt3_parents[] = { "pll3_48m_clk", "gpt3_synth_clk", }; 107 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", 108 "pll2_clk", }; 109 110 /* gpt rate configuration table, in ascending order of rates */ 111 static struct gpt_rate_tbl gpt_rtbl[] = { 112 /* For pll1 = 332 MHz */ 113 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ 114 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ 115 {.mscale = 1, .nscale = 0}, /* 83 MHz */ 116 }; 117 118 void __init spear6xx_clk_init(void) 119 { 120 struct clk *clk, *clk1; 121 122 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); 123 clk_register_clkdev(clk, "apb_pclk", NULL); 124 125 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 126 32000); 127 clk_register_clkdev(clk, "osc_32k_clk", NULL); 128 129 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, 130 30000000); 131 clk_register_clkdev(clk, "osc_30m_clk", NULL); 132 133 /* clock derived from 32 KHz osc clk */ 134 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, 135 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); 136 clk_register_clkdev(clk, NULL, "rtc-spear"); 137 138 /* clock derived from 30 MHz osc clk */ 139 clk = clk_register_fixed_rate(NULL, "pll3_48m_clk", "osc_24m_clk", 0, 140 48000000); 141 clk_register_clkdev(clk, "pll3_48m_clk", NULL); 142 143 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", 144 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl), 145 &_lock, &clk1, NULL); 146 clk_register_clkdev(clk, "vco1_clk", NULL); 147 clk_register_clkdev(clk1, "pll1_clk", NULL); 148 149 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, 150 "osc_30m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, 151 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 152 clk_register_clkdev(clk, "vco2_clk", NULL); 153 clk_register_clkdev(clk1, "pll2_clk", NULL); 154 155 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, 156 1); 157 clk_register_clkdev(clk, NULL, "wdt"); 158 159 /* clock derived from pll1 clk */ 160 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); 161 clk_register_clkdev(clk, "cpu_clk", NULL); 162 163 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 164 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 165 HCLK_RATIO_MASK, 0, &_lock); 166 clk_register_clkdev(clk, "ahb_clk", NULL); 167 168 clk = clk_register_aux("uart_synth_clk", "uart_synth_gate_clk", 169 "pll1_clk", 0, UART_CLK_SYNT, NULL, aux_rtbl, 170 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 171 clk_register_clkdev(clk, "uart_synth_clk", NULL); 172 clk_register_clkdev(clk1, "uart_synth_gate_clk", NULL); 173 174 clk = clk_register_mux(NULL, "uart_mux_clk", uart_parents, 175 ARRAY_SIZE(uart_parents), 0, PERIP_CLK_CFG, 176 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 177 clk_register_clkdev(clk, "uart_mux_clk", NULL); 178 179 clk = clk_register_gate(NULL, "uart0", "uart_mux_clk", 0, 180 PERIP1_CLK_ENB, UART0_CLK_ENB, 0, &_lock); 181 clk_register_clkdev(clk, NULL, "d0000000.serial"); 182 183 clk = clk_register_gate(NULL, "uart1", "uart_mux_clk", 0, 184 PERIP1_CLK_ENB, UART1_CLK_ENB, 0, &_lock); 185 clk_register_clkdev(clk, NULL, "d0080000.serial"); 186 187 clk = clk_register_aux("firda_synth_clk", "firda_synth_gate_clk", 188 "pll1_clk", 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, 189 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 190 clk_register_clkdev(clk, "firda_synth_clk", NULL); 191 clk_register_clkdev(clk1, "firda_synth_gate_clk", NULL); 192 193 clk = clk_register_mux(NULL, "firda_mux_clk", firda_parents, 194 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 195 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 196 clk_register_clkdev(clk, "firda_mux_clk", NULL); 197 198 clk = clk_register_gate(NULL, "firda_clk", "firda_mux_clk", 0, 199 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 200 clk_register_clkdev(clk, NULL, "firda"); 201 202 clk = clk_register_aux("clcd_synth_clk", "clcd_synth_gate_clk", 203 "pll1_clk", 0, CLCD_CLK_SYNT, NULL, aux_rtbl, 204 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 205 clk_register_clkdev(clk, "clcd_synth_clk", NULL); 206 clk_register_clkdev(clk1, "clcd_synth_gate_clk", NULL); 207 208 clk = clk_register_mux(NULL, "clcd_mux_clk", clcd_parents, 209 ARRAY_SIZE(clcd_parents), 0, PERIP_CLK_CFG, 210 CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0, &_lock); 211 clk_register_clkdev(clk, "clcd_mux_clk", NULL); 212 213 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mux_clk", 0, 214 PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock); 215 clk_register_clkdev(clk, NULL, "clcd"); 216 217 /* gpt clocks */ 218 clk = clk_register_gpt("gpt0_1_synth_clk", "pll1_clk", 0, PRSC0_CLK_CFG, 219 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 220 clk_register_clkdev(clk, "gpt0_1_synth_clk", NULL); 221 222 clk = clk_register_mux(NULL, "gpt0_mux_clk", gpt0_1_parents, 223 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 224 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 225 clk_register_clkdev(clk, NULL, "gpt0"); 226 227 clk = clk_register_mux(NULL, "gpt1_mux_clk", gpt0_1_parents, 228 ARRAY_SIZE(gpt0_1_parents), 0, PERIP_CLK_CFG, 229 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 230 clk_register_clkdev(clk, "gpt1_mux_clk", NULL); 231 232 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mux_clk", 0, 233 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 234 clk_register_clkdev(clk, NULL, "gpt1"); 235 236 clk = clk_register_gpt("gpt2_synth_clk", "pll1_clk", 0, PRSC1_CLK_CFG, 237 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 238 clk_register_clkdev(clk, "gpt2_synth_clk", NULL); 239 240 clk = clk_register_mux(NULL, "gpt2_mux_clk", gpt2_parents, 241 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 242 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 243 clk_register_clkdev(clk, "gpt2_mux_clk", NULL); 244 245 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mux_clk", 0, 246 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 247 clk_register_clkdev(clk, NULL, "gpt2"); 248 249 clk = clk_register_gpt("gpt3_synth_clk", "pll1_clk", 0, PRSC2_CLK_CFG, 250 gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock); 251 clk_register_clkdev(clk, "gpt3_synth_clk", NULL); 252 253 clk = clk_register_mux(NULL, "gpt3_mux_clk", gpt3_parents, 254 ARRAY_SIZE(gpt3_parents), 0, PERIP_CLK_CFG, 255 GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 256 clk_register_clkdev(clk, "gpt3_mux_clk", NULL); 257 258 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mux_clk", 0, 259 PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock); 260 clk_register_clkdev(clk, NULL, "gpt3"); 261 262 /* clock derived from pll3 clk */ 263 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_48m_clk", 0, 264 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); 265 clk_register_clkdev(clk, NULL, "usbh.0_clk"); 266 267 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_48m_clk", 0, 268 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); 269 clk_register_clkdev(clk, NULL, "usbh.1_clk"); 270 271 clk = clk_register_gate(NULL, "usbd_clk", "pll3_48m_clk", 0, 272 PERIP1_CLK_ENB, USBD_CLK_ENB, 0, &_lock); 273 clk_register_clkdev(clk, NULL, "designware_udc"); 274 275 /* clock derived from ahb clk */ 276 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 277 1); 278 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 279 280 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 281 ARRAY_SIZE(ddr_parents), 282 0, PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, 283 &_lock); 284 clk_register_clkdev(clk, "ddr_clk", NULL); 285 286 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 287 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, 288 PCLK_RATIO_MASK, 0, &_lock); 289 clk_register_clkdev(clk, "apb_clk", NULL); 290 291 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 292 DMA_CLK_ENB, 0, &_lock); 293 clk_register_clkdev(clk, NULL, "fc400000.dma"); 294 295 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 296 FSMC_CLK_ENB, 0, &_lock); 297 clk_register_clkdev(clk, NULL, "d1800000.flash"); 298 299 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 300 GMAC_CLK_ENB, 0, &_lock); 301 clk_register_clkdev(clk, NULL, "gmac"); 302 303 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 304 I2C_CLK_ENB, 0, &_lock); 305 clk_register_clkdev(clk, NULL, "d0200000.i2c"); 306 307 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 308 JPEG_CLK_ENB, 0, &_lock); 309 clk_register_clkdev(clk, NULL, "jpeg"); 310 311 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 312 SMI_CLK_ENB, 0, &_lock); 313 clk_register_clkdev(clk, NULL, "fc000000.flash"); 314 315 /* clock derived from apb clk */ 316 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, 317 ADC_CLK_ENB, 0, &_lock); 318 clk_register_clkdev(clk, NULL, "adc"); 319 320 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); 321 clk_register_clkdev(clk, NULL, "f0100000.gpio"); 322 323 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 324 GPIO1_CLK_ENB, 0, &_lock); 325 clk_register_clkdev(clk, NULL, "fc980000.gpio"); 326 327 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 328 GPIO2_CLK_ENB, 0, &_lock); 329 clk_register_clkdev(clk, NULL, "d8100000.gpio"); 330 331 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, 332 SSP0_CLK_ENB, 0, &_lock); 333 clk_register_clkdev(clk, NULL, "ssp-pl022.0"); 334 335 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, 336 SSP1_CLK_ENB, 0, &_lock); 337 clk_register_clkdev(clk, NULL, "ssp-pl022.1"); 338 339 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, 340 SSP2_CLK_ENB, 0, &_lock); 341 clk_register_clkdev(clk, NULL, "ssp-pl022.2"); 342 } 343