1 /* 2 * SPEAr3xx machines clock framework source file 3 * 4 * Copyright (C) 2012 ST Microelectronics 5 * Viresh Kumar <viresh.linux@gmail.com> 6 * 7 * This file is licensed under the terms of the GNU General Public 8 * License version 2. This program is licensed "as is" without any 9 * warranty of any kind, whether express or implied. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clkdev.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/of_platform.h> 17 #include <linux/spinlock_types.h> 18 #include "clk.h" 19 20 static DEFINE_SPINLOCK(_lock); 21 22 #define PLL1_CTR (misc_base + 0x008) 23 #define PLL1_FRQ (misc_base + 0x00C) 24 #define PLL2_CTR (misc_base + 0x014) 25 #define PLL2_FRQ (misc_base + 0x018) 26 #define PLL_CLK_CFG (misc_base + 0x020) 27 /* PLL_CLK_CFG register masks */ 28 #define MCTR_CLK_SHIFT 28 29 #define MCTR_CLK_MASK 3 30 31 #define CORE_CLK_CFG (misc_base + 0x024) 32 /* CORE CLK CFG register masks */ 33 #define GEN_SYNTH2_3_CLK_SHIFT 18 34 #define GEN_SYNTH2_3_CLK_MASK 1 35 36 #define HCLK_RATIO_SHIFT 10 37 #define HCLK_RATIO_MASK 2 38 #define PCLK_RATIO_SHIFT 8 39 #define PCLK_RATIO_MASK 2 40 41 #define PERIP_CLK_CFG (misc_base + 0x028) 42 /* PERIP_CLK_CFG register masks */ 43 #define UART_CLK_SHIFT 4 44 #define UART_CLK_MASK 1 45 #define FIRDA_CLK_SHIFT 5 46 #define FIRDA_CLK_MASK 2 47 #define GPT0_CLK_SHIFT 8 48 #define GPT1_CLK_SHIFT 11 49 #define GPT2_CLK_SHIFT 12 50 #define GPT_CLK_MASK 1 51 52 #define PERIP1_CLK_ENB (misc_base + 0x02C) 53 /* PERIP1_CLK_ENB register masks */ 54 #define UART_CLK_ENB 3 55 #define SSP_CLK_ENB 5 56 #define I2C_CLK_ENB 7 57 #define JPEG_CLK_ENB 8 58 #define FIRDA_CLK_ENB 10 59 #define GPT1_CLK_ENB 11 60 #define GPT2_CLK_ENB 12 61 #define ADC_CLK_ENB 15 62 #define RTC_CLK_ENB 17 63 #define GPIO_CLK_ENB 18 64 #define DMA_CLK_ENB 19 65 #define SMI_CLK_ENB 21 66 #define GMAC_CLK_ENB 23 67 #define USBD_CLK_ENB 24 68 #define USBH_CLK_ENB 25 69 #define C3_CLK_ENB 31 70 71 #define RAS_CLK_ENB (misc_base + 0x034) 72 #define RAS_AHB_CLK_ENB 0 73 #define RAS_PLL1_CLK_ENB 1 74 #define RAS_APB_CLK_ENB 2 75 #define RAS_32K_CLK_ENB 3 76 #define RAS_24M_CLK_ENB 4 77 #define RAS_48M_CLK_ENB 5 78 #define RAS_PLL2_CLK_ENB 7 79 #define RAS_SYNT0_CLK_ENB 8 80 #define RAS_SYNT1_CLK_ENB 9 81 #define RAS_SYNT2_CLK_ENB 10 82 #define RAS_SYNT3_CLK_ENB 11 83 84 #define PRSC0_CLK_CFG (misc_base + 0x044) 85 #define PRSC1_CLK_CFG (misc_base + 0x048) 86 #define PRSC2_CLK_CFG (misc_base + 0x04C) 87 #define AMEM_CLK_CFG (misc_base + 0x050) 88 #define AMEM_CLK_ENB 0 89 90 #define CLCD_CLK_SYNT (misc_base + 0x05C) 91 #define FIRDA_CLK_SYNT (misc_base + 0x060) 92 #define UART_CLK_SYNT (misc_base + 0x064) 93 #define GMAC_CLK_SYNT (misc_base + 0x068) 94 #define GEN0_CLK_SYNT (misc_base + 0x06C) 95 #define GEN1_CLK_SYNT (misc_base + 0x070) 96 #define GEN2_CLK_SYNT (misc_base + 0x074) 97 #define GEN3_CLK_SYNT (misc_base + 0x078) 98 99 /* pll rate configuration table, in ascending order of rates */ 100 static struct pll_rate_tbl pll_rtbl[] = { 101 {.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */ 102 {.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */ 103 {.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */ 104 }; 105 106 /* aux rate configuration table, in ascending order of rates */ 107 static struct aux_rate_tbl aux_rtbl[] = { 108 /* For PLL1 = 332 MHz */ 109 {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */ 110 {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */ 111 {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */ 112 {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */ 113 {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */ 114 {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */ 115 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ 116 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ 117 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ 118 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ 119 }; 120 121 /* gpt rate configuration table, in ascending order of rates */ 122 static struct gpt_rate_tbl gpt_rtbl[] = { 123 /* For pll1 = 332 MHz */ 124 {.mscale = 4, .nscale = 0}, /* 41.5 MHz */ 125 {.mscale = 2, .nscale = 0}, /* 55.3 MHz */ 126 {.mscale = 1, .nscale = 0}, /* 83 MHz */ 127 }; 128 129 /* clock parents */ 130 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", }; 131 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", 132 }; 133 static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", }; 134 static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", }; 135 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", }; 136 static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", }; 137 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none", 138 "pll2_clk", }; 139 140 #ifdef CONFIG_MACH_SPEAR300 141 static void __init spear300_clk_init(void) 142 { 143 struct clk *clk; 144 145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 146 1, 1); 147 clk_register_clkdev(clk, NULL, "60000000.clcd"); 148 149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, 150 1); 151 clk_register_clkdev(clk, NULL, "94000000.flash"); 152 153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, 154 1); 155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); 156 157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, 158 1); 159 clk_register_clkdev(clk, NULL, "a9000000.gpio"); 160 161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, 162 1); 163 clk_register_clkdev(clk, NULL, "a0000000.kbd"); 164 } 165 #else 166 static inline void spear300_clk_init(void) { } 167 #endif 168 169 /* array of all spear 310 clock lookups */ 170 #ifdef CONFIG_MACH_SPEAR310 171 static void __init spear310_clk_init(void) 172 { 173 struct clk *clk; 174 175 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 176 1); 177 clk_register_clkdev(clk, "emi", NULL); 178 179 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, 180 1); 181 clk_register_clkdev(clk, NULL, "44000000.flash"); 182 183 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1, 184 1); 185 clk_register_clkdev(clk, NULL, "tdm"); 186 187 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1, 188 1); 189 clk_register_clkdev(clk, NULL, "b2000000.serial"); 190 191 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1, 192 1); 193 clk_register_clkdev(clk, NULL, "b2080000.serial"); 194 195 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1, 196 1); 197 clk_register_clkdev(clk, NULL, "b2100000.serial"); 198 199 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1, 200 1); 201 clk_register_clkdev(clk, NULL, "b2180000.serial"); 202 203 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1, 204 1); 205 clk_register_clkdev(clk, NULL, "b2200000.serial"); 206 } 207 #else 208 static inline void spear310_clk_init(void) { } 209 #endif 210 211 /* array of all spear 320 clock lookups */ 212 #ifdef CONFIG_MACH_SPEAR320 213 214 #define SPEAR320_CONTROL_REG (soc_config_base + 0x0000) 215 #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) 216 217 #define SPEAR320_UARTX_PCLK_MASK 0x1 218 #define SPEAR320_UART2_PCLK_SHIFT 8 219 #define SPEAR320_UART3_PCLK_SHIFT 9 220 #define SPEAR320_UART4_PCLK_SHIFT 10 221 #define SPEAR320_UART5_PCLK_SHIFT 11 222 #define SPEAR320_UART6_PCLK_SHIFT 12 223 #define SPEAR320_RS485_PCLK_SHIFT 13 224 #define SMII_PCLK_SHIFT 18 225 #define SMII_PCLK_MASK 2 226 #define SMII_PCLK_VAL_PAD 0x0 227 #define SMII_PCLK_VAL_PLL2 0x1 228 #define SMII_PCLK_VAL_SYNTH0 0x2 229 #define SDHCI_PCLK_SHIFT 15 230 #define SDHCI_PCLK_MASK 1 231 #define SDHCI_PCLK_VAL_48M 0x0 232 #define SDHCI_PCLK_VAL_SYNTH3 0x1 233 #define I2S_REF_PCLK_SHIFT 8 234 #define I2S_REF_PCLK_MASK 1 235 #define I2S_REF_PCLK_SYNTH_VAL 0x1 236 #define I2S_REF_PCLK_PLL2_VAL 0x0 237 #define UART1_PCLK_SHIFT 6 238 #define UART1_PCLK_MASK 1 239 #define SPEAR320_UARTX_PCLK_VAL_SYNTH1 0x0 240 #define SPEAR320_UARTX_PCLK_VAL_APB 0x1 241 242 static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", }; 243 static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", }; 244 static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk", 245 "ras_syn0_gclk", }; 246 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", }; 247 248 static void __init spear320_clk_init(void __iomem *soc_config_base) 249 { 250 struct clk *clk; 251 252 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, 253 CLK_IS_ROOT, 125000000); 254 clk_register_clkdev(clk, "smii_125m_pad", NULL); 255 256 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, 257 1, 1); 258 clk_register_clkdev(clk, NULL, "90000000.clcd"); 259 260 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, 261 1); 262 clk_register_clkdev(clk, "emi", NULL); 263 264 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, 265 1); 266 clk_register_clkdev(clk, NULL, "4c000000.flash"); 267 268 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1, 269 1); 270 clk_register_clkdev(clk, NULL, "a7000000.i2c"); 271 272 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1, 273 1); 274 clk_register_clkdev(clk, NULL, "a8000000.pwm"); 275 276 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1, 277 1); 278 clk_register_clkdev(clk, NULL, "a5000000.spi"); 279 280 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1, 281 1); 282 clk_register_clkdev(clk, NULL, "a6000000.spi"); 283 284 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1, 285 1); 286 clk_register_clkdev(clk, NULL, "c_can_platform.0"); 287 288 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1, 289 1); 290 clk_register_clkdev(clk, NULL, "c_can_platform.1"); 291 292 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1, 293 1); 294 clk_register_clkdev(clk, NULL, "a9400000.i2s"); 295 296 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, 297 ARRAY_SIZE(i2s_ref_parents), 298 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 299 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT, 300 I2S_REF_PCLK_MASK, 0, &_lock); 301 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 302 303 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 304 CLK_SET_RATE_PARENT, 1, 305 4); 306 clk_register_clkdev(clk, "i2s_sclk", NULL); 307 308 clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1, 309 1); 310 clk_register_clkdev(clk, "hclk", "aa000000.eth"); 311 312 clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1, 313 1); 314 clk_register_clkdev(clk, "hclk", "ab000000.eth"); 315 316 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, 317 ARRAY_SIZE(uartx_parents), 318 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 319 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT, 320 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 321 clk_register_clkdev(clk, NULL, "a9300000.serial"); 322 323 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, 324 ARRAY_SIZE(sdhci_parents), 325 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 326 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 327 0, &_lock); 328 clk_register_clkdev(clk, NULL, "70000000.sdhci"); 329 330 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, 331 ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT, 332 SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK, 333 0, &_lock); 334 clk_register_clkdev(clk, NULL, "smii_pclk"); 335 336 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); 337 clk_register_clkdev(clk, NULL, "smii"); 338 339 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, 340 ARRAY_SIZE(uartx_parents), 341 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 342 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK, 343 0, &_lock); 344 clk_register_clkdev(clk, NULL, "a3000000.serial"); 345 346 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, 347 ARRAY_SIZE(uartx_parents), 348 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 349 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT, 350 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 351 clk_register_clkdev(clk, NULL, "a4000000.serial"); 352 353 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, 354 ARRAY_SIZE(uartx_parents), 355 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 356 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT, 357 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 358 clk_register_clkdev(clk, NULL, "a9100000.serial"); 359 360 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, 361 ARRAY_SIZE(uartx_parents), 362 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 363 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT, 364 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 365 clk_register_clkdev(clk, NULL, "a9200000.serial"); 366 367 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, 368 ARRAY_SIZE(uartx_parents), 369 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 370 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT, 371 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 372 clk_register_clkdev(clk, NULL, "60000000.serial"); 373 374 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, 375 ARRAY_SIZE(uartx_parents), 376 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 377 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT, 378 SPEAR320_UARTX_PCLK_MASK, 0, &_lock); 379 clk_register_clkdev(clk, NULL, "60100000.serial"); 380 } 381 #else 382 static inline void spear320_clk_init(void __iomem *soc_config_base) { } 383 #endif 384 385 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base) 386 { 387 struct clk *clk, *clk1; 388 389 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 390 32000); 391 clk_register_clkdev(clk, "osc_32k_clk", NULL); 392 393 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, 394 24000000); 395 clk_register_clkdev(clk, "osc_24m_clk", NULL); 396 397 /* clock derived from 32 KHz osc clk */ 398 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 399 PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock); 400 clk_register_clkdev(clk, NULL, "fc900000.rtc"); 401 402 /* clock derived from 24 MHz osc clk */ 403 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, 404 48000000); 405 clk_register_clkdev(clk, "pll3_clk", NULL); 406 407 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, 408 1); 409 clk_register_clkdev(clk, NULL, "fc880000.wdt"); 410 411 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, 412 "osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, 413 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 414 clk_register_clkdev(clk, "vco1_clk", NULL); 415 clk_register_clkdev(clk1, "pll1_clk", NULL); 416 417 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, 418 "osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, 419 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); 420 clk_register_clkdev(clk, "vco2_clk", NULL); 421 clk_register_clkdev(clk1, "pll2_clk", NULL); 422 423 /* clock derived from pll1 clk */ 424 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 425 CLK_SET_RATE_PARENT, 1, 1); 426 clk_register_clkdev(clk, "cpu_clk", NULL); 427 428 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 429 CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT, 430 HCLK_RATIO_MASK, 0, &_lock); 431 clk_register_clkdev(clk, "ahb_clk", NULL); 432 433 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, 434 UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 435 &_lock, &clk1); 436 clk_register_clkdev(clk, "uart_syn_clk", NULL); 437 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 438 439 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 440 ARRAY_SIZE(uart0_parents), 441 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 442 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0, 443 &_lock); 444 clk_register_clkdev(clk, "uart0_mclk", NULL); 445 446 clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 447 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0, 448 &_lock); 449 clk_register_clkdev(clk, NULL, "d0000000.serial"); 450 451 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, 452 FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 453 &_lock, &clk1); 454 clk_register_clkdev(clk, "firda_syn_clk", NULL); 455 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 456 457 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 458 ARRAY_SIZE(firda_parents), 459 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 460 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, 461 &_lock); 462 clk_register_clkdev(clk, "firda_mclk", NULL); 463 464 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 465 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, 466 &_lock); 467 clk_register_clkdev(clk, NULL, "firda"); 468 469 /* gpt clocks */ 470 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, 471 ARRAY_SIZE(gpt_rtbl), &_lock); 472 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, 473 ARRAY_SIZE(gpt0_parents), 474 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 475 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 476 clk_register_clkdev(clk, NULL, "gpt0"); 477 478 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, 479 ARRAY_SIZE(gpt_rtbl), &_lock); 480 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, 481 ARRAY_SIZE(gpt1_parents), 482 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 483 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 484 clk_register_clkdev(clk, "gpt1_mclk", NULL); 485 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 486 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, 487 &_lock); 488 clk_register_clkdev(clk, NULL, "gpt1"); 489 490 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, 491 ARRAY_SIZE(gpt_rtbl), &_lock); 492 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 493 ARRAY_SIZE(gpt2_parents), 494 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 495 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 496 clk_register_clkdev(clk, "gpt2_mclk", NULL); 497 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 498 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, 499 &_lock); 500 clk_register_clkdev(clk, NULL, "gpt2"); 501 502 /* general synths clocks */ 503 clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk", 504 0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 505 &_lock, &clk1); 506 clk_register_clkdev(clk, "gen0_syn_clk", NULL); 507 clk_register_clkdev(clk1, "gen0_syn_gclk", NULL); 508 509 clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk", 510 0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl), 511 &_lock, &clk1); 512 clk_register_clkdev(clk, "gen1_syn_clk", NULL); 513 clk_register_clkdev(clk1, "gen1_syn_gclk", NULL); 514 515 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, 516 ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT, 517 CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT, 518 GEN_SYNTH2_3_CLK_MASK, 0, &_lock); 519 clk_register_clkdev(clk, "gen2_3_par_clk", NULL); 520 521 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", 522 "gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl, 523 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 524 clk_register_clkdev(clk, "gen2_syn_clk", NULL); 525 clk_register_clkdev(clk1, "gen2_syn_gclk", NULL); 526 527 clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk", 528 "gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl, 529 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); 530 clk_register_clkdev(clk, "gen3_syn_clk", NULL); 531 clk_register_clkdev(clk1, "gen3_syn_gclk", NULL); 532 533 /* clock derived from pll3 clk */ 534 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 535 USBH_CLK_ENB, 0, &_lock); 536 clk_register_clkdev(clk, NULL, "e1800000.ehci"); 537 clk_register_clkdev(clk, NULL, "e1900000.ohci"); 538 clk_register_clkdev(clk, NULL, "e2100000.ohci"); 539 540 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, 541 1); 542 clk_register_clkdev(clk, "usbh.0_clk", NULL); 543 544 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1, 545 1); 546 clk_register_clkdev(clk, "usbh.1_clk", NULL); 547 548 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 549 USBD_CLK_ENB, 0, &_lock); 550 clk_register_clkdev(clk, NULL, "e1100000.usbd"); 551 552 /* clock derived from ahb clk */ 553 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 554 1); 555 clk_register_clkdev(clk, "ahbmult2_clk", NULL); 556 557 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, 558 ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT, 559 PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock); 560 clk_register_clkdev(clk, "ddr_clk", NULL); 561 562 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", 563 CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT, 564 PCLK_RATIO_MASK, 0, &_lock); 565 clk_register_clkdev(clk, "apb_clk", NULL); 566 567 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG, 568 AMEM_CLK_ENB, 0, &_lock); 569 clk_register_clkdev(clk, "amem_clk", NULL); 570 571 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 572 C3_CLK_ENB, 0, &_lock); 573 clk_register_clkdev(clk, NULL, "c3_clk"); 574 575 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 576 DMA_CLK_ENB, 0, &_lock); 577 clk_register_clkdev(clk, NULL, "fc400000.dma"); 578 579 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 580 GMAC_CLK_ENB, 0, &_lock); 581 clk_register_clkdev(clk, NULL, "e0800000.eth"); 582 583 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 584 I2C_CLK_ENB, 0, &_lock); 585 clk_register_clkdev(clk, NULL, "d0180000.i2c"); 586 587 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 588 JPEG_CLK_ENB, 0, &_lock); 589 clk_register_clkdev(clk, NULL, "jpeg"); 590 591 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, 592 SMI_CLK_ENB, 0, &_lock); 593 clk_register_clkdev(clk, NULL, "fc000000.flash"); 594 595 /* clock derived from apb clk */ 596 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, 597 ADC_CLK_ENB, 0, &_lock); 598 clk_register_clkdev(clk, NULL, "d0080000.adc"); 599 600 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, 601 GPIO_CLK_ENB, 0, &_lock); 602 clk_register_clkdev(clk, NULL, "fc980000.gpio"); 603 604 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, 605 SSP_CLK_ENB, 0, &_lock); 606 clk_register_clkdev(clk, NULL, "d0100000.spi"); 607 608 /* RAS clk enable */ 609 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, 610 RAS_AHB_CLK_ENB, 0, &_lock); 611 clk_register_clkdev(clk, "ras_ahb_clk", NULL); 612 613 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, 614 RAS_APB_CLK_ENB, 0, &_lock); 615 clk_register_clkdev(clk, "ras_apb_clk", NULL); 616 617 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, 618 RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock); 619 clk_register_clkdev(clk, "ras_32k_clk", NULL); 620 621 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0, 622 RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock); 623 clk_register_clkdev(clk, "ras_24m_clk", NULL); 624 625 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0, 626 RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock); 627 clk_register_clkdev(clk, "ras_pll1_clk", NULL); 628 629 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, 630 RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock); 631 clk_register_clkdev(clk, "ras_pll2_clk", NULL); 632 633 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, 634 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); 635 clk_register_clkdev(clk, "ras_pll3_clk", NULL); 636 637 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 638 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, 639 &_lock); 640 clk_register_clkdev(clk, "ras_syn0_gclk", NULL); 641 642 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 643 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, 644 &_lock); 645 clk_register_clkdev(clk, "ras_syn1_gclk", NULL); 646 647 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 648 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, 649 &_lock); 650 clk_register_clkdev(clk, "ras_syn2_gclk", NULL); 651 652 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 653 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, 654 &_lock); 655 clk_register_clkdev(clk, "ras_syn3_gclk", NULL); 656 657 if (of_machine_is_compatible("st,spear300")) 658 spear300_clk_init(); 659 else if (of_machine_is_compatible("st,spear310")) 660 spear310_clk_init(); 661 else if (of_machine_is_compatible("st,spear320")) 662 spear320_clk_init(soc_config_base); 663 } 664