1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * SPEAr3xx machines clock framework source file
4  *
5  * Copyright (C) 2012 ST Microelectronics
6  * Viresh Kumar <vireshk@kernel.org>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/clkdev.h>
11 #include <linux/clk/spear.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/of_platform.h>
15 #include <linux/spinlock_types.h>
16 #include "clk.h"
17 
18 static DEFINE_SPINLOCK(_lock);
19 
20 #define PLL1_CTR			(misc_base + 0x008)
21 #define PLL1_FRQ			(misc_base + 0x00C)
22 #define PLL2_CTR			(misc_base + 0x014)
23 #define PLL2_FRQ			(misc_base + 0x018)
24 #define PLL_CLK_CFG			(misc_base + 0x020)
25 	/* PLL_CLK_CFG register masks */
26 	#define MCTR_CLK_SHIFT		28
27 	#define MCTR_CLK_MASK		3
28 
29 #define CORE_CLK_CFG			(misc_base + 0x024)
30 	/* CORE CLK CFG register masks */
31 	#define GEN_SYNTH2_3_CLK_SHIFT	18
32 	#define GEN_SYNTH2_3_CLK_MASK	1
33 
34 	#define HCLK_RATIO_SHIFT	10
35 	#define HCLK_RATIO_MASK		2
36 	#define PCLK_RATIO_SHIFT	8
37 	#define PCLK_RATIO_MASK		2
38 
39 #define PERIP_CLK_CFG			(misc_base + 0x028)
40 	/* PERIP_CLK_CFG register masks */
41 	#define UART_CLK_SHIFT		4
42 	#define UART_CLK_MASK		1
43 	#define FIRDA_CLK_SHIFT		5
44 	#define FIRDA_CLK_MASK		2
45 	#define GPT0_CLK_SHIFT		8
46 	#define GPT1_CLK_SHIFT		11
47 	#define GPT2_CLK_SHIFT		12
48 	#define GPT_CLK_MASK		1
49 
50 #define PERIP1_CLK_ENB			(misc_base + 0x02C)
51 	/* PERIP1_CLK_ENB register masks */
52 	#define UART_CLK_ENB		3
53 	#define SSP_CLK_ENB		5
54 	#define I2C_CLK_ENB		7
55 	#define JPEG_CLK_ENB		8
56 	#define FIRDA_CLK_ENB		10
57 	#define GPT1_CLK_ENB		11
58 	#define GPT2_CLK_ENB		12
59 	#define ADC_CLK_ENB		15
60 	#define RTC_CLK_ENB		17
61 	#define GPIO_CLK_ENB		18
62 	#define DMA_CLK_ENB		19
63 	#define SMI_CLK_ENB		21
64 	#define GMAC_CLK_ENB		23
65 	#define USBD_CLK_ENB		24
66 	#define USBH_CLK_ENB		25
67 	#define C3_CLK_ENB		31
68 
69 #define RAS_CLK_ENB			(misc_base + 0x034)
70 	#define RAS_AHB_CLK_ENB		0
71 	#define RAS_PLL1_CLK_ENB	1
72 	#define RAS_APB_CLK_ENB		2
73 	#define RAS_32K_CLK_ENB		3
74 	#define RAS_24M_CLK_ENB		4
75 	#define RAS_48M_CLK_ENB		5
76 	#define RAS_PLL2_CLK_ENB	7
77 	#define RAS_SYNT0_CLK_ENB	8
78 	#define RAS_SYNT1_CLK_ENB	9
79 	#define RAS_SYNT2_CLK_ENB	10
80 	#define RAS_SYNT3_CLK_ENB	11
81 
82 #define PRSC0_CLK_CFG			(misc_base + 0x044)
83 #define PRSC1_CLK_CFG			(misc_base + 0x048)
84 #define PRSC2_CLK_CFG			(misc_base + 0x04C)
85 #define AMEM_CLK_CFG			(misc_base + 0x050)
86 	#define AMEM_CLK_ENB		0
87 
88 #define CLCD_CLK_SYNT			(misc_base + 0x05C)
89 #define FIRDA_CLK_SYNT			(misc_base + 0x060)
90 #define UART_CLK_SYNT			(misc_base + 0x064)
91 #define GMAC_CLK_SYNT			(misc_base + 0x068)
92 #define GEN0_CLK_SYNT			(misc_base + 0x06C)
93 #define GEN1_CLK_SYNT			(misc_base + 0x070)
94 #define GEN2_CLK_SYNT			(misc_base + 0x074)
95 #define GEN3_CLK_SYNT			(misc_base + 0x078)
96 
97 /* pll rate configuration table, in ascending order of rates */
98 static struct pll_rate_tbl pll_rtbl[] = {
99 	{.mode = 0, .m = 0x53, .n = 0x0C, .p = 0x1}, /* vco 332 & pll 166 MHz */
100 	{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* vco 532 & pll 266 MHz */
101 	{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* vco 664 & pll 332 MHz */
102 };
103 
104 /* aux rate configuration table, in ascending order of rates */
105 static struct aux_rate_tbl aux_rtbl[] = {
106 	/* For PLL1 = 332 MHz */
107 	{.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */
108 	{.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */
109 	{.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */
110 	{.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */
111 	{.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */
112 	{.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */
113 	{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
114 	{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
115 	{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
116 	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
117 };
118 
119 /* gpt rate configuration table, in ascending order of rates */
120 static struct gpt_rate_tbl gpt_rtbl[] = {
121 	/* For pll1 = 332 MHz */
122 	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
123 	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
124 	{.mscale = 1, .nscale = 0}, /* 83 MHz */
125 };
126 
127 /* clock parents */
128 static const char *uart0_parents[] = { "pll3_clk", "uart_syn_gclk", };
129 static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk",
130 };
131 static const char *gpt0_parents[] = { "pll3_clk", "gpt0_syn_clk", };
132 static const char *gpt1_parents[] = { "pll3_clk", "gpt1_syn_clk", };
133 static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
134 static const char *gen2_3_parents[] = { "pll1_clk", "pll2_clk", };
135 static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
136 	"pll2_clk", };
137 
138 #ifdef CONFIG_MACH_SPEAR300
139 static void __init spear300_clk_init(void)
140 {
141 	struct clk *clk;
142 
143 	clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
144 			1, 1);
145 	clk_register_clkdev(clk, NULL, "60000000.clcd");
146 
147 	clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
148 			1);
149 	clk_register_clkdev(clk, NULL, "94000000.flash");
150 
151 	clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1,
152 			1);
153 	clk_register_clkdev(clk, NULL, "70000000.sdhci");
154 
155 	clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1,
156 			1);
157 	clk_register_clkdev(clk, NULL, "a9000000.gpio");
158 
159 	clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1,
160 			1);
161 	clk_register_clkdev(clk, NULL, "a0000000.kbd");
162 }
163 #else
164 static inline void spear300_clk_init(void) { }
165 #endif
166 
167 /* array of all spear 310 clock lookups */
168 #ifdef CONFIG_MACH_SPEAR310
169 static void __init spear310_clk_init(void)
170 {
171 	struct clk *clk;
172 
173 	clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
174 			1);
175 	clk_register_clkdev(clk, "emi", NULL);
176 
177 	clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
178 			1);
179 	clk_register_clkdev(clk, NULL, "44000000.flash");
180 
181 	clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1,
182 			1);
183 	clk_register_clkdev(clk, NULL, "tdm");
184 
185 	clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1,
186 			1);
187 	clk_register_clkdev(clk, NULL, "b2000000.serial");
188 
189 	clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1,
190 			1);
191 	clk_register_clkdev(clk, NULL, "b2080000.serial");
192 
193 	clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1,
194 			1);
195 	clk_register_clkdev(clk, NULL, "b2100000.serial");
196 
197 	clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1,
198 			1);
199 	clk_register_clkdev(clk, NULL, "b2180000.serial");
200 
201 	clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1,
202 			1);
203 	clk_register_clkdev(clk, NULL, "b2200000.serial");
204 }
205 #else
206 static inline void spear310_clk_init(void) { }
207 #endif
208 
209 /* array of all spear 320 clock lookups */
210 #ifdef CONFIG_MACH_SPEAR320
211 
212 #define SPEAR320_CONTROL_REG		(soc_config_base + 0x0010)
213 #define SPEAR320_EXT_CTRL_REG		(soc_config_base + 0x0018)
214 
215 	#define SPEAR320_UARTX_PCLK_MASK		0x1
216 	#define SPEAR320_UART2_PCLK_SHIFT		8
217 	#define SPEAR320_UART3_PCLK_SHIFT		9
218 	#define SPEAR320_UART4_PCLK_SHIFT		10
219 	#define SPEAR320_UART5_PCLK_SHIFT		11
220 	#define SPEAR320_UART6_PCLK_SHIFT		12
221 	#define SPEAR320_RS485_PCLK_SHIFT		13
222 	#define SMII_PCLK_SHIFT				18
223 	#define SMII_PCLK_MASK				2
224 	#define SMII_PCLK_VAL_PAD			0x0
225 	#define SMII_PCLK_VAL_PLL2			0x1
226 	#define SMII_PCLK_VAL_SYNTH0			0x2
227 	#define SDHCI_PCLK_SHIFT			15
228 	#define SDHCI_PCLK_MASK				1
229 	#define SDHCI_PCLK_VAL_48M			0x0
230 	#define SDHCI_PCLK_VAL_SYNTH3			0x1
231 	#define I2S_REF_PCLK_SHIFT			8
232 	#define I2S_REF_PCLK_MASK			1
233 	#define I2S_REF_PCLK_SYNTH_VAL			0x1
234 	#define I2S_REF_PCLK_PLL2_VAL			0x0
235 	#define UART1_PCLK_SHIFT			6
236 	#define UART1_PCLK_MASK				1
237 	#define SPEAR320_UARTX_PCLK_VAL_SYNTH1		0x0
238 	#define SPEAR320_UARTX_PCLK_VAL_APB		0x1
239 
240 static const char *i2s_ref_parents[] = { "ras_pll2_clk", "ras_syn2_gclk", };
241 static const char *sdhci_parents[] = { "ras_pll3_clk", "ras_syn3_gclk", };
242 static const char *smii0_parents[] = { "smii_125m_pad", "ras_pll2_clk",
243 	"ras_syn0_gclk", };
244 static const char *uartx_parents[] = { "ras_syn1_gclk", "ras_apb_clk", };
245 
246 static void __init spear320_clk_init(void __iomem *soc_config_base,
247 				     struct clk *ras_apb_clk)
248 {
249 	struct clk *clk;
250 
251 	clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL,
252 			0, 125000000);
253 	clk_register_clkdev(clk, "smii_125m_pad", NULL);
254 
255 	clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0,
256 			1, 1);
257 	clk_register_clkdev(clk, NULL, "90000000.clcd");
258 
259 	clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1,
260 			1);
261 	clk_register_clkdev(clk, "emi", NULL);
262 
263 	clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1,
264 			1);
265 	clk_register_clkdev(clk, NULL, "4c000000.flash");
266 
267 	clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1,
268 			1);
269 	clk_register_clkdev(clk, NULL, "a7000000.i2c");
270 
271 	clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
272 			1);
273 	clk_register_clkdev(clk, NULL, "a8000000.pwm");
274 
275 	clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
276 			1);
277 	clk_register_clkdev(clk, NULL, "a5000000.spi");
278 
279 	clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1,
280 			1);
281 	clk_register_clkdev(clk, NULL, "a6000000.spi");
282 
283 	clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1,
284 			1);
285 	clk_register_clkdev(clk, NULL, "c_can_platform.0");
286 
287 	clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1,
288 			1);
289 	clk_register_clkdev(clk, NULL, "c_can_platform.1");
290 
291 	clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
292 			1);
293 	clk_register_clkdev(clk, NULL, "a9400000.i2s");
294 
295 	clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
296 			ARRAY_SIZE(i2s_ref_parents),
297 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
298 			SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
299 			I2S_REF_PCLK_MASK, 0, &_lock);
300 	clk_register_clkdev(clk, "i2s_ref_clk", NULL);
301 
302 	clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
303 			CLK_SET_RATE_PARENT, 1,
304 			4);
305 	clk_register_clkdev(clk, "i2s_sclk", NULL);
306 
307 	clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
308 			1);
309 	clk_register_clkdev(clk, "hclk", "aa000000.eth");
310 
311 	clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
312 			1);
313 	clk_register_clkdev(clk, "hclk", "ab000000.eth");
314 
315 	clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
316 			ARRAY_SIZE(uartx_parents),
317 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
318 			SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
319 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
320 	clk_register_clkdev(clk, NULL, "a9300000.serial");
321 
322 	clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
323 			ARRAY_SIZE(sdhci_parents),
324 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
325 			SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
326 			0, &_lock);
327 	clk_register_clkdev(clk, NULL, "70000000.sdhci");
328 
329 	clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
330 			ARRAY_SIZE(smii0_parents), CLK_SET_RATE_NO_REPARENT,
331 			SPEAR320_CONTROL_REG, SMII_PCLK_SHIFT, SMII_PCLK_MASK,
332 			0, &_lock);
333 	clk_register_clkdev(clk, NULL, "smii_pclk");
334 
335 	clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1);
336 	clk_register_clkdev(clk, NULL, "smii");
337 
338 	clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
339 			ARRAY_SIZE(uartx_parents),
340 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
341 			SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
342 			0, &_lock);
343 	clk_register_clkdev(clk, NULL, "a3000000.serial");
344 	/* Enforce ras_apb_clk */
345 	clk_set_parent(clk, ras_apb_clk);
346 
347 	clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
348 			ARRAY_SIZE(uartx_parents),
349 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
350 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
351 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
352 	clk_register_clkdev(clk, NULL, "a4000000.serial");
353 	/* Enforce ras_apb_clk */
354 	clk_set_parent(clk, ras_apb_clk);
355 
356 	clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
357 			ARRAY_SIZE(uartx_parents),
358 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
359 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
360 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
361 	clk_register_clkdev(clk, NULL, "a9100000.serial");
362 
363 	clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
364 			ARRAY_SIZE(uartx_parents),
365 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
366 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
367 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
368 	clk_register_clkdev(clk, NULL, "a9200000.serial");
369 
370 	clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
371 			ARRAY_SIZE(uartx_parents),
372 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
373 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
374 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
375 	clk_register_clkdev(clk, NULL, "60000000.serial");
376 
377 	clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
378 			ARRAY_SIZE(uartx_parents),
379 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
380 			SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
381 			SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
382 	clk_register_clkdev(clk, NULL, "60100000.serial");
383 }
384 #else
385 static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { }
386 #endif
387 
388 void __init spear3xx_clk_init(void __iomem *misc_base, void __iomem *soc_config_base)
389 {
390 	struct clk *clk, *clk1, *ras_apb_clk;
391 
392 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
393 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
394 
395 	clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
396 	clk_register_clkdev(clk, "osc_24m_clk", NULL);
397 
398 	/* clock derived from 32 KHz osc clk */
399 	clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
400 			PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
401 	clk_register_clkdev(clk, NULL, "fc900000.rtc");
402 
403 	/* clock derived from 24 MHz osc clk */
404 	clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
405 			48000000);
406 	clk_register_clkdev(clk, "pll3_clk", NULL);
407 
408 	clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1,
409 			1);
410 	clk_register_clkdev(clk, NULL, "fc880000.wdt");
411 
412 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL,
413 			"osc_24m_clk", 0, PLL1_CTR, PLL1_FRQ, pll_rtbl,
414 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
415 	clk_register_clkdev(clk, "vco1_clk", NULL);
416 	clk_register_clkdev(clk1, "pll1_clk", NULL);
417 
418 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL,
419 			"osc_24m_clk", 0, PLL2_CTR, PLL2_FRQ, pll_rtbl,
420 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
421 	clk_register_clkdev(clk, "vco2_clk", NULL);
422 	clk_register_clkdev(clk1, "pll2_clk", NULL);
423 
424 	/* clock derived from pll1 clk */
425 	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
426 			CLK_SET_RATE_PARENT, 1, 1);
427 	clk_register_clkdev(clk, "cpu_clk", NULL);
428 
429 	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
430 			CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
431 			HCLK_RATIO_MASK, 0, &_lock);
432 	clk_register_clkdev(clk, "ahb_clk", NULL);
433 
434 	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
435 			UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
436 			&_lock, &clk1);
437 	clk_register_clkdev(clk, "uart_syn_clk", NULL);
438 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
439 
440 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
441 			ARRAY_SIZE(uart0_parents),
442 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
443 			PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
444 			&_lock);
445 	clk_register_clkdev(clk, "uart0_mclk", NULL);
446 
447 	clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
448 			CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0,
449 			&_lock);
450 	clk_register_clkdev(clk, NULL, "d0000000.serial");
451 
452 	clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
453 			FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
454 			&_lock, &clk1);
455 	clk_register_clkdev(clk, "firda_syn_clk", NULL);
456 	clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
457 
458 	clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
459 			ARRAY_SIZE(firda_parents),
460 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
461 			PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
462 			&_lock);
463 	clk_register_clkdev(clk, "firda_mclk", NULL);
464 
465 	clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
466 			CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,
467 			&_lock);
468 	clk_register_clkdev(clk, NULL, "firda");
469 
470 	/* gpt clocks */
471 	clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
472 			ARRAY_SIZE(gpt_rtbl), &_lock);
473 	clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
474 			ARRAY_SIZE(gpt0_parents),
475 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
476 			PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
477 	clk_register_clkdev(clk, NULL, "gpt0");
478 
479 	clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
480 			ARRAY_SIZE(gpt_rtbl), &_lock);
481 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
482 			ARRAY_SIZE(gpt1_parents),
483 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
484 			PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
485 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
486 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
487 			CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0,
488 			&_lock);
489 	clk_register_clkdev(clk, NULL, "gpt1");
490 
491 	clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
492 			ARRAY_SIZE(gpt_rtbl), &_lock);
493 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
494 			ARRAY_SIZE(gpt2_parents),
495 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
496 			PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
497 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
498 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
499 			CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0,
500 			&_lock);
501 	clk_register_clkdev(clk, NULL, "gpt2");
502 
503 	/* general synths clocks */
504 	clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk",
505 			0, GEN0_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
506 			&_lock, &clk1);
507 	clk_register_clkdev(clk, "gen0_syn_clk", NULL);
508 	clk_register_clkdev(clk1, "gen0_syn_gclk", NULL);
509 
510 	clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk",
511 			0, GEN1_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
512 			&_lock, &clk1);
513 	clk_register_clkdev(clk, "gen1_syn_clk", NULL);
514 	clk_register_clkdev(clk1, "gen1_syn_gclk", NULL);
515 
516 	clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents,
517 			ARRAY_SIZE(gen2_3_parents), CLK_SET_RATE_NO_REPARENT,
518 			CORE_CLK_CFG, GEN_SYNTH2_3_CLK_SHIFT,
519 			GEN_SYNTH2_3_CLK_MASK, 0, &_lock);
520 	clk_register_clkdev(clk, "gen2_3_par_clk", NULL);
521 
522 	clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk",
523 			"gen2_3_par_clk", 0, GEN2_CLK_SYNT, NULL, aux_rtbl,
524 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
525 	clk_register_clkdev(clk, "gen2_syn_clk", NULL);
526 	clk_register_clkdev(clk1, "gen2_syn_gclk", NULL);
527 
528 	clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk",
529 			"gen2_3_par_clk", 0, GEN3_CLK_SYNT, NULL, aux_rtbl,
530 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
531 	clk_register_clkdev(clk, "gen3_syn_clk", NULL);
532 	clk_register_clkdev(clk1, "gen3_syn_gclk", NULL);
533 
534 	/* clock derived from pll3 clk */
535 	clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
536 			USBH_CLK_ENB, 0, &_lock);
537 	clk_register_clkdev(clk, NULL, "e1800000.ehci");
538 	clk_register_clkdev(clk, NULL, "e1900000.ohci");
539 	clk_register_clkdev(clk, NULL, "e2100000.ohci");
540 
541 	clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
542 			1);
543 	clk_register_clkdev(clk, "usbh.0_clk", NULL);
544 
545 	clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1,
546 			1);
547 	clk_register_clkdev(clk, "usbh.1_clk", NULL);
548 
549 	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
550 			USBD_CLK_ENB, 0, &_lock);
551 	clk_register_clkdev(clk, NULL, "e1100000.usbd");
552 
553 	/* clock derived from ahb clk */
554 	clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
555 			1);
556 	clk_register_clkdev(clk, "ahbmult2_clk", NULL);
557 
558 	clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
559 			ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
560 			PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
561 	clk_register_clkdev(clk, "ddr_clk", NULL);
562 
563 	clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
564 			CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
565 			PCLK_RATIO_MASK, 0, &_lock);
566 	clk_register_clkdev(clk, "apb_clk", NULL);
567 
568 	clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG,
569 			AMEM_CLK_ENB, 0, &_lock);
570 	clk_register_clkdev(clk, "amem_clk", NULL);
571 
572 	clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
573 			C3_CLK_ENB, 0, &_lock);
574 	clk_register_clkdev(clk, NULL, "c3_clk");
575 
576 	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
577 			DMA_CLK_ENB, 0, &_lock);
578 	clk_register_clkdev(clk, NULL, "fc400000.dma");
579 
580 	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
581 			GMAC_CLK_ENB, 0, &_lock);
582 	clk_register_clkdev(clk, NULL, "e0800000.eth");
583 
584 	clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
585 			I2C_CLK_ENB, 0, &_lock);
586 	clk_register_clkdev(clk, NULL, "d0180000.i2c");
587 
588 	clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
589 			JPEG_CLK_ENB, 0, &_lock);
590 	clk_register_clkdev(clk, NULL, "jpeg");
591 
592 	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
593 			SMI_CLK_ENB, 0, &_lock);
594 	clk_register_clkdev(clk, NULL, "fc000000.flash");
595 
596 	/* clock derived from apb clk */
597 	clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
598 			ADC_CLK_ENB, 0, &_lock);
599 	clk_register_clkdev(clk, NULL, "d0080000.adc");
600 
601 	clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
602 			GPIO_CLK_ENB, 0, &_lock);
603 	clk_register_clkdev(clk, NULL, "fc980000.gpio");
604 
605 	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
606 			SSP_CLK_ENB, 0, &_lock);
607 	clk_register_clkdev(clk, NULL, "d0100000.spi");
608 
609 	/* RAS clk enable */
610 	clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB,
611 			RAS_AHB_CLK_ENB, 0, &_lock);
612 	clk_register_clkdev(clk, "ras_ahb_clk", NULL);
613 
614 	clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB,
615 			RAS_APB_CLK_ENB, 0, &_lock);
616 	clk_register_clkdev(clk, "ras_apb_clk", NULL);
617 	ras_apb_clk = clk;
618 
619 	clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0,
620 			RAS_CLK_ENB, RAS_32K_CLK_ENB, 0, &_lock);
621 	clk_register_clkdev(clk, "ras_32k_clk", NULL);
622 
623 	clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0,
624 			RAS_CLK_ENB, RAS_24M_CLK_ENB, 0, &_lock);
625 	clk_register_clkdev(clk, "ras_24m_clk", NULL);
626 
627 	clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0,
628 			RAS_CLK_ENB, RAS_PLL1_CLK_ENB, 0, &_lock);
629 	clk_register_clkdev(clk, "ras_pll1_clk", NULL);
630 
631 	clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
632 			RAS_CLK_ENB, RAS_PLL2_CLK_ENB, 0, &_lock);
633 	clk_register_clkdev(clk, "ras_pll2_clk", NULL);
634 
635 	clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
636 			RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
637 	clk_register_clkdev(clk, "ras_pll3_clk", NULL);
638 
639 	clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
640 			CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
641 			&_lock);
642 	clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
643 
644 	clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
645 			CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
646 			&_lock);
647 	clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
648 
649 	clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
650 			CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
651 			&_lock);
652 	clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
653 
654 	clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
655 			CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,
656 			&_lock);
657 	clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
658 
659 	if (of_machine_is_compatible("st,spear300"))
660 		spear300_clk_init();
661 	else if (of_machine_is_compatible("st,spear310"))
662 		spear310_clk_init();
663 	else if (of_machine_is_compatible("st,spear320"))
664 		spear320_clk_init(soc_config_base, ras_apb_clk);
665 }
666