1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * arch/arm/mach-spear13xx/spear1340_clock.c
4  *
5  * SPEAr1340 machine clock framework source file
6  *
7  * Copyright (C) 2012 ST Microelectronics
8  * Viresh Kumar <vireshk@kernel.org>
9  */
10 
11 #include <linux/clkdev.h>
12 #include <linux/clk/spear.h>
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/spinlock_types.h>
16 #include "clk.h"
17 
18 /* Clock Configuration Registers */
19 #define SPEAR1340_SYS_CLK_CTRL			(misc_base + 0x200)
20 	#define SPEAR1340_HCLK_SRC_SEL_SHIFT	27
21 	#define SPEAR1340_HCLK_SRC_SEL_MASK	1
22 	#define SPEAR1340_SCLK_SRC_SEL_SHIFT	23
23 	#define SPEAR1340_SCLK_SRC_SEL_MASK	3
24 
25 /* PLL related registers and bit values */
26 #define SPEAR1340_PLL_CFG			(misc_base + 0x210)
27 	/* PLL_CFG bit values */
28 	#define SPEAR1340_CLCD_SYNT_CLK_MASK		1
29 	#define SPEAR1340_CLCD_SYNT_CLK_SHIFT		31
30 	#define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT		29
31 	#define SPEAR1340_GEN_SYNT_CLK_MASK		2
32 	#define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT		27
33 	#define SPEAR1340_PLL_CLK_MASK			2
34 	#define SPEAR1340_PLL3_CLK_SHIFT		24
35 	#define SPEAR1340_PLL2_CLK_SHIFT		22
36 	#define SPEAR1340_PLL1_CLK_SHIFT		20
37 
38 #define SPEAR1340_PLL1_CTR			(misc_base + 0x214)
39 #define SPEAR1340_PLL1_FRQ			(misc_base + 0x218)
40 #define SPEAR1340_PLL2_CTR			(misc_base + 0x220)
41 #define SPEAR1340_PLL2_FRQ			(misc_base + 0x224)
42 #define SPEAR1340_PLL3_CTR			(misc_base + 0x22C)
43 #define SPEAR1340_PLL3_FRQ			(misc_base + 0x230)
44 #define SPEAR1340_PLL4_CTR			(misc_base + 0x238)
45 #define SPEAR1340_PLL4_FRQ			(misc_base + 0x23C)
46 #define SPEAR1340_PERIP_CLK_CFG			(misc_base + 0x244)
47 	/* PERIP_CLK_CFG bit values */
48 	#define SPEAR1340_SPDIF_CLK_MASK		1
49 	#define SPEAR1340_SPDIF_OUT_CLK_SHIFT		15
50 	#define SPEAR1340_SPDIF_IN_CLK_SHIFT		14
51 	#define SPEAR1340_GPT3_CLK_SHIFT		13
52 	#define SPEAR1340_GPT2_CLK_SHIFT		12
53 	#define SPEAR1340_GPT_CLK_MASK			1
54 	#define SPEAR1340_GPT1_CLK_SHIFT		9
55 	#define SPEAR1340_GPT0_CLK_SHIFT		8
56 	#define SPEAR1340_UART_CLK_MASK			2
57 	#define SPEAR1340_UART1_CLK_SHIFT		6
58 	#define SPEAR1340_UART0_CLK_SHIFT		4
59 	#define SPEAR1340_CLCD_CLK_MASK			2
60 	#define SPEAR1340_CLCD_CLK_SHIFT		2
61 	#define SPEAR1340_C3_CLK_MASK			1
62 	#define SPEAR1340_C3_CLK_SHIFT			1
63 
64 #define SPEAR1340_GMAC_CLK_CFG			(misc_base + 0x248)
65 	#define SPEAR1340_GMAC_PHY_CLK_MASK		1
66 	#define SPEAR1340_GMAC_PHY_CLK_SHIFT		2
67 	#define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK	2
68 	#define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT	0
69 
70 #define SPEAR1340_I2S_CLK_CFG			(misc_base + 0x24C)
71 	/* I2S_CLK_CFG register mask */
72 	#define SPEAR1340_I2S_SCLK_X_MASK		0x1F
73 	#define SPEAR1340_I2S_SCLK_X_SHIFT		27
74 	#define SPEAR1340_I2S_SCLK_Y_MASK		0x1F
75 	#define SPEAR1340_I2S_SCLK_Y_SHIFT		22
76 	#define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT		21
77 	#define SPEAR1340_I2S_SCLK_SYNTH_ENB		20
78 	#define SPEAR1340_I2S_PRS1_CLK_X_MASK		0xFF
79 	#define SPEAR1340_I2S_PRS1_CLK_X_SHIFT		12
80 	#define SPEAR1340_I2S_PRS1_CLK_Y_MASK		0xFF
81 	#define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT		4
82 	#define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT		3
83 	#define SPEAR1340_I2S_REF_SEL_MASK		1
84 	#define SPEAR1340_I2S_REF_SHIFT			2
85 	#define SPEAR1340_I2S_SRC_CLK_MASK		2
86 	#define SPEAR1340_I2S_SRC_CLK_SHIFT		0
87 
88 #define SPEAR1340_C3_CLK_SYNT			(misc_base + 0x250)
89 #define SPEAR1340_UART0_CLK_SYNT		(misc_base + 0x254)
90 #define SPEAR1340_UART1_CLK_SYNT		(misc_base + 0x258)
91 #define SPEAR1340_GMAC_CLK_SYNT			(misc_base + 0x25C)
92 #define SPEAR1340_SDHCI_CLK_SYNT		(misc_base + 0x260)
93 #define SPEAR1340_CFXD_CLK_SYNT			(misc_base + 0x264)
94 #define SPEAR1340_ADC_CLK_SYNT			(misc_base + 0x270)
95 #define SPEAR1340_AMBA_CLK_SYNT			(misc_base + 0x274)
96 #define SPEAR1340_CLCD_CLK_SYNT			(misc_base + 0x27C)
97 #define SPEAR1340_SYS_CLK_SYNT			(misc_base + 0x284)
98 #define SPEAR1340_GEN_CLK_SYNT0			(misc_base + 0x28C)
99 #define SPEAR1340_GEN_CLK_SYNT1			(misc_base + 0x294)
100 #define SPEAR1340_GEN_CLK_SYNT2			(misc_base + 0x29C)
101 #define SPEAR1340_GEN_CLK_SYNT3			(misc_base + 0x304)
102 #define SPEAR1340_PERIP1_CLK_ENB		(misc_base + 0x30C)
103 	#define SPEAR1340_RTC_CLK_ENB			31
104 	#define SPEAR1340_ADC_CLK_ENB			30
105 	#define SPEAR1340_C3_CLK_ENB			29
106 	#define SPEAR1340_CLCD_CLK_ENB			27
107 	#define SPEAR1340_DMA_CLK_ENB			25
108 	#define SPEAR1340_GPIO1_CLK_ENB			24
109 	#define SPEAR1340_GPIO0_CLK_ENB			23
110 	#define SPEAR1340_GPT1_CLK_ENB			22
111 	#define SPEAR1340_GPT0_CLK_ENB			21
112 	#define SPEAR1340_I2S_PLAY_CLK_ENB		20
113 	#define SPEAR1340_I2S_REC_CLK_ENB		19
114 	#define SPEAR1340_I2C0_CLK_ENB			18
115 	#define SPEAR1340_SSP_CLK_ENB			17
116 	#define SPEAR1340_UART0_CLK_ENB			15
117 	#define SPEAR1340_PCIE_SATA_CLK_ENB		12
118 	#define SPEAR1340_UOC_CLK_ENB			11
119 	#define SPEAR1340_UHC1_CLK_ENB			10
120 	#define SPEAR1340_UHC0_CLK_ENB			9
121 	#define SPEAR1340_GMAC_CLK_ENB			8
122 	#define SPEAR1340_CFXD_CLK_ENB			7
123 	#define SPEAR1340_SDHCI_CLK_ENB			6
124 	#define SPEAR1340_SMI_CLK_ENB			5
125 	#define SPEAR1340_FSMC_CLK_ENB			4
126 	#define SPEAR1340_SYSRAM0_CLK_ENB		3
127 	#define SPEAR1340_SYSRAM1_CLK_ENB		2
128 	#define SPEAR1340_SYSROM_CLK_ENB		1
129 	#define SPEAR1340_BUS_CLK_ENB			0
130 
131 #define SPEAR1340_PERIP2_CLK_ENB		(misc_base + 0x310)
132 	#define SPEAR1340_THSENS_CLK_ENB		8
133 	#define SPEAR1340_I2S_REF_PAD_CLK_ENB		7
134 	#define SPEAR1340_ACP_CLK_ENB			6
135 	#define SPEAR1340_GPT3_CLK_ENB			5
136 	#define SPEAR1340_GPT2_CLK_ENB			4
137 	#define SPEAR1340_KBD_CLK_ENB			3
138 	#define SPEAR1340_CPU_DBG_CLK_ENB		2
139 	#define SPEAR1340_DDR_CORE_CLK_ENB		1
140 	#define SPEAR1340_DDR_CTRL_CLK_ENB		0
141 
142 #define SPEAR1340_PERIP3_CLK_ENB		(misc_base + 0x314)
143 	#define SPEAR1340_PLGPIO_CLK_ENB		18
144 	#define SPEAR1340_VIDEO_DEC_CLK_ENB		16
145 	#define SPEAR1340_VIDEO_ENC_CLK_ENB		15
146 	#define SPEAR1340_SPDIF_OUT_CLK_ENB		13
147 	#define SPEAR1340_SPDIF_IN_CLK_ENB		12
148 	#define SPEAR1340_VIDEO_IN_CLK_ENB		11
149 	#define SPEAR1340_CAM0_CLK_ENB			10
150 	#define SPEAR1340_CAM1_CLK_ENB			9
151 	#define SPEAR1340_CAM2_CLK_ENB			8
152 	#define SPEAR1340_CAM3_CLK_ENB			7
153 	#define SPEAR1340_MALI_CLK_ENB			6
154 	#define SPEAR1340_CEC0_CLK_ENB			5
155 	#define SPEAR1340_CEC1_CLK_ENB			4
156 	#define SPEAR1340_PWM_CLK_ENB			3
157 	#define SPEAR1340_I2C1_CLK_ENB			2
158 	#define SPEAR1340_UART1_CLK_ENB			1
159 
160 static DEFINE_SPINLOCK(_lock);
161 
162 /* pll rate configuration table, in ascending order of rates */
163 static struct pll_rate_tbl pll_rtbl[] = {
164 	/* PCLK 24MHz */
165 	{.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
166 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
167 	{.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
168 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
169 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
170 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
171 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
172 	{.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
173 };
174 
175 /* vco-pll4 rate configuration table, in ascending order of rates */
176 static struct pll_rate_tbl pll4_rtbl[] = {
177 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
178 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
179 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
180 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
181 };
182 
183 /*
184  * All below entries generate 166 MHz for
185  * different values of vco1div2
186  */
187 static struct frac_rate_tbl amba_synth_rtbl[] = {
188 	{.div = 0x073A8}, /* for vco1div2 = 600 MHz */
189 	{.div = 0x06062}, /* for vco1div2 = 500 MHz */
190 	{.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
191 	{.div = 0x04000}, /* for vco1div2 = 332 MHz */
192 	{.div = 0x03031}, /* for vco1div2 = 250 MHz */
193 	{.div = 0x0268D}, /* for vco1div2 = 200 MHz */
194 };
195 
196 /*
197  * Synthesizer Clock derived from vcodiv2. This clock is one of the
198  * possible clocks to feed cpu directly.
199  * We can program this synthesizer to make cpu run on different clock
200  * frequencies.
201  * Following table provides configuration values to let cpu run on 200,
202  * 250, 332, 400 or 500 MHz considering different possibilites of input
203  * (vco1div2) clock.
204  *
205  * --------------------------------------------------------------------
206  * vco1div2(Mhz)	fout(Mhz)	cpuclk = fout/2		div
207  * --------------------------------------------------------------------
208  * 400			200		100			0x04000
209  * 400			250		125			0x03333
210  * 400			332		166			0x0268D
211  * 400			400		200			0x02000
212  * --------------------------------------------------------------------
213  * 500			200		100			0x05000
214  * 500			250		125			0x04000
215  * 500			332		166			0x03031
216  * 500			400		200			0x02800
217  * 500			500		250			0x02000
218  * --------------------------------------------------------------------
219  * 600			200		100			0x06000
220  * 600			250		125			0x04CCE
221  * 600			332		166			0x039D5
222  * 600			400		200			0x03000
223  * 600			500		250			0x02666
224  * --------------------------------------------------------------------
225  * 664			200		100			0x06a38
226  * 664			250		125			0x054FD
227  * 664			332		166			0x04000
228  * 664			400		200			0x0351E
229  * 664			500		250			0x02A7E
230  * --------------------------------------------------------------------
231  * 800			200		100			0x08000
232  * 800			250		125			0x06666
233  * 800			332		166			0x04D18
234  * 800			400		200			0x04000
235  * 800			500		250			0x03333
236  * --------------------------------------------------------------------
237  * sys rate configuration table is in descending order of divisor.
238  */
239 static struct frac_rate_tbl sys_synth_rtbl[] = {
240 	{.div = 0x08000},
241 	{.div = 0x06a38},
242 	{.div = 0x06666},
243 	{.div = 0x06000},
244 	{.div = 0x054FD},
245 	{.div = 0x05000},
246 	{.div = 0x04D18},
247 	{.div = 0x04CCE},
248 	{.div = 0x04000},
249 	{.div = 0x039D5},
250 	{.div = 0x0351E},
251 	{.div = 0x03333},
252 	{.div = 0x03031},
253 	{.div = 0x03000},
254 	{.div = 0x02A7E},
255 	{.div = 0x02800},
256 	{.div = 0x0268D},
257 	{.div = 0x02666},
258 	{.div = 0x02000},
259 };
260 
261 /* aux rate configuration table, in ascending order of rates */
262 static struct aux_rate_tbl aux_rtbl[] = {
263 	/* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */
264 	{.xscale = 5, .yscale = 122, .eq = 0},
265 	/* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */
266 	{.xscale = 10, .yscale = 204, .eq = 0},
267 	/* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */
268 	{.xscale = 4, .yscale = 25, .eq = 0},
269 	/* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */
270 	{.xscale = 4, .yscale = 21, .eq = 0},
271 	/* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */
272 	{.xscale = 5, .yscale = 18, .eq = 0},
273 	/* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */
274 	{.xscale = 2, .yscale = 6, .eq = 0},
275 	/* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */
276 	{.xscale = 5, .yscale = 12, .eq = 0},
277 	/* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */
278 	{.xscale = 2, .yscale = 4, .eq = 0},
279 	/* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */
280 	{.xscale = 5, .yscale = 18, .eq = 1},
281 	/* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */
282 	{.xscale = 1, .yscale = 3, .eq = 1},
283 	/* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */
284 	{.xscale = 5, .yscale = 12, .eq = 1},
285 	/* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */
286 	{.xscale = 1, .yscale = 2, .eq = 1},
287 };
288 
289 /* gmac rate configuration table, in ascending order of rates */
290 static struct aux_rate_tbl gmac_rtbl[] = {
291 	/* For gmac phy input clk */
292 	{.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
293 	{.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
294 	{.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
295 	{.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
296 };
297 
298 /* clcd rate configuration table, in ascending order of rates */
299 static struct frac_rate_tbl clcd_rtbl[] = {
300 	{.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
301 	{.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
302 	{.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
303 	{.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
304 	{.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
305 	{.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
306 	{.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
307 	{.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
308 	{.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
309 	{.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
310 	{.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
311 	{.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
312 	{.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
313 	{.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
314 	{.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
315 	{.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
316 	{.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
317 	{.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
318 	{.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
319 	{.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
320 };
321 
322 /* i2s prescaler1 masks */
323 static const struct aux_clk_masks i2s_prs1_masks = {
324 	.eq_sel_mask = AUX_EQ_SEL_MASK,
325 	.eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
326 	.eq1_mask = AUX_EQ1_SEL,
327 	.eq2_mask = AUX_EQ2_SEL,
328 	.xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
329 	.xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
330 	.yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
331 	.yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
332 };
333 
334 /* i2s sclk (bit clock) syynthesizers masks */
335 static const struct aux_clk_masks i2s_sclk_masks = {
336 	.eq_sel_mask = AUX_EQ_SEL_MASK,
337 	.eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
338 	.eq1_mask = AUX_EQ1_SEL,
339 	.eq2_mask = AUX_EQ2_SEL,
340 	.xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
341 	.xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
342 	.yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
343 	.yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
344 	.enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
345 };
346 
347 /* i2s prs1 aux rate configuration table, in ascending order of rates */
348 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
349 	/* For parent clk = 49.152 MHz */
350 	{.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
351 	{.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
352 	{.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
353 	{.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
354 
355 	/*
356 	 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
357 	 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
358 	 */
359 	{.xscale = 1, .yscale = 3, .eq = 0},
360 
361 	/* For parent clk = 49.152 MHz */
362 	{.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
363 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
364 };
365 
366 /* i2s sclk aux rate configuration table, in ascending order of rates */
367 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
368 	/* For sclk = ref_clk * x/2/y */
369 	{.xscale = 1, .yscale = 4, .eq = 0},
370 	{.xscale = 1, .yscale = 2, .eq = 0},
371 };
372 
373 /* adc rate configuration table, in ascending order of rates */
374 /* possible adc range is 2.5 MHz to 20 MHz. */
375 static struct aux_rate_tbl adc_rtbl[] = {
376 	/* For ahb = 166.67 MHz */
377 	{.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
378 	{.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
379 	{.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
380 	{.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
381 };
382 
383 /* General synth rate configuration table, in ascending order of rates */
384 static struct frac_rate_tbl gen_rtbl[] = {
385 	{.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
386 	{.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
387 	{.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
388 	{.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
389 	{.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
390 	{.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
391 	{.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
392 	{.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
393 	{.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
394 	{.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
395 	{.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
396 	{.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
397 	{.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
398 	{.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
399 	{.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
400 	{.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
401 	{.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
402 	{.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
403 	{.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
404 	{.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
405 	{.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
406 	{.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
407 	{.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
408 	{.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
409 	{.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
410 };
411 
412 /* clock parents */
413 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
414 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
415 	"pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
416 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
417 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
418 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
419 	"uart0_syn_gclk", };
420 static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
421 	"uart1_syn_gclk", };
422 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
423 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
424 	"osc_25m_clk", };
425 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
426 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
427 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
428 static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
429 	"i2s_src_pad_clk", };
430 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
431 static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
432 static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
433 
434 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
435 	"pll3_clk", };
436 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
437 	"pll2_clk", };
438 
439 void __init spear1340_clk_init(void __iomem *misc_base)
440 {
441 	struct clk *clk, *clk1;
442 
443 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
444 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
445 
446 	clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
447 	clk_register_clkdev(clk, "osc_24m_clk", NULL);
448 
449 	clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
450 	clk_register_clkdev(clk, "osc_25m_clk", NULL);
451 
452 	clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
453 	clk_register_clkdev(clk, "gmii_pad_clk", NULL);
454 
455 	clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
456 				      12288000);
457 	clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
458 
459 	/* clock derived from 32 KHz osc clk */
460 	clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
461 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
462 			&_lock);
463 	clk_register_clkdev(clk, NULL, "e0580000.rtc");
464 
465 	/* clock derived from 24 or 25 MHz osc clk */
466 	/* vco-pll */
467 	clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
468 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
469 			SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
470 			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
471 	clk_register_clkdev(clk, "vco1_mclk", NULL);
472 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
473 			SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
474 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
475 	clk_register_clkdev(clk, "vco1_clk", NULL);
476 	clk_register_clkdev(clk1, "pll1_clk", NULL);
477 
478 	clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
479 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
480 			SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
481 			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
482 	clk_register_clkdev(clk, "vco2_mclk", NULL);
483 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
484 			SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
485 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
486 	clk_register_clkdev(clk, "vco2_clk", NULL);
487 	clk_register_clkdev(clk1, "pll2_clk", NULL);
488 
489 	clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
490 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
491 			SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
492 			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
493 	clk_register_clkdev(clk, "vco3_mclk", NULL);
494 	clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
495 			SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
496 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
497 	clk_register_clkdev(clk, "vco3_clk", NULL);
498 	clk_register_clkdev(clk1, "pll3_clk", NULL);
499 
500 	clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
501 			0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
502 			ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
503 	clk_register_clkdev(clk, "vco4_clk", NULL);
504 	clk_register_clkdev(clk1, "pll4_clk", NULL);
505 
506 	clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
507 			48000000);
508 	clk_register_clkdev(clk, "pll5_clk", NULL);
509 
510 	clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
511 			25000000);
512 	clk_register_clkdev(clk, "pll6_clk", NULL);
513 
514 	/* vco div n clocks */
515 	clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
516 			2);
517 	clk_register_clkdev(clk, "vco1div2_clk", NULL);
518 
519 	clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
520 			4);
521 	clk_register_clkdev(clk, "vco1div4_clk", NULL);
522 
523 	clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
524 			2);
525 	clk_register_clkdev(clk, "vco2div2_clk", NULL);
526 
527 	clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
528 			2);
529 	clk_register_clkdev(clk, "vco3div2_clk", NULL);
530 
531 	/* peripherals */
532 	clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
533 			128);
534 	clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
535 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
536 			&_lock);
537 	clk_register_clkdev(clk, NULL, "e07008c4.thermal");
538 
539 	/* clock derived from pll4 clk */
540 	clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
541 			1);
542 	clk_register_clkdev(clk, "ddr_clk", NULL);
543 
544 	/* clock derived from pll1 clk */
545 	clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
546 			SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
547 			ARRAY_SIZE(sys_synth_rtbl), &_lock);
548 	clk_register_clkdev(clk, "sys_syn_clk", NULL);
549 
550 	clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
551 			SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
552 			ARRAY_SIZE(amba_synth_rtbl), &_lock);
553 	clk_register_clkdev(clk, "amba_syn_clk", NULL);
554 
555 	clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
556 			ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
557 			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
558 			SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
559 	clk_register_clkdev(clk, "sys_mclk", NULL);
560 
561 	clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
562 			2);
563 	clk_register_clkdev(clk, "cpu_clk", NULL);
564 
565 	clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
566 			3);
567 	clk_register_clkdev(clk, "cpu_div3_clk", NULL);
568 
569 	clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
570 			2);
571 	clk_register_clkdev(clk, NULL, "ec800620.wdt");
572 
573 	clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
574 			2);
575 	clk_register_clkdev(clk, NULL, "smp_twd");
576 
577 	clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
578 			ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
579 			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
580 			SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
581 	clk_register_clkdev(clk, "ahb_clk", NULL);
582 
583 	clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
584 			2);
585 	clk_register_clkdev(clk, "apb_clk", NULL);
586 
587 	/* gpt clocks */
588 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
589 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
590 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
591 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
592 	clk_register_clkdev(clk, "gpt0_mclk", NULL);
593 	clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
594 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
595 			&_lock);
596 	clk_register_clkdev(clk, NULL, "gpt0");
597 
598 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
599 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
600 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
601 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
602 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
603 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
604 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
605 			&_lock);
606 	clk_register_clkdev(clk, NULL, "gpt1");
607 
608 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
609 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
610 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
611 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
612 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
613 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
614 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
615 			&_lock);
616 	clk_register_clkdev(clk, NULL, "gpt2");
617 
618 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
619 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
620 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
621 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
622 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
623 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
624 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
625 			&_lock);
626 	clk_register_clkdev(clk, NULL, "gpt3");
627 
628 	/* others */
629 	clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
630 			"vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
631 			aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
632 	clk_register_clkdev(clk, "uart0_syn_clk", NULL);
633 	clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
634 
635 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
636 			ARRAY_SIZE(uart0_parents),
637 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
638 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
639 			SPEAR1340_UART_CLK_MASK, 0, &_lock);
640 	clk_register_clkdev(clk, "uart0_mclk", NULL);
641 
642 	clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
643 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
644 			SPEAR1340_UART0_CLK_ENB, 0, &_lock);
645 	clk_register_clkdev(clk, NULL, "e0000000.serial");
646 
647 	clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
648 			"vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
649 			aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
650 	clk_register_clkdev(clk, "uart1_syn_clk", NULL);
651 	clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
652 
653 	clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
654 			ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
655 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
656 			SPEAR1340_UART_CLK_MASK, 0, &_lock);
657 	clk_register_clkdev(clk, "uart1_mclk", NULL);
658 
659 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
660 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
661 			&_lock);
662 	clk_register_clkdev(clk, NULL, "b4100000.serial");
663 
664 	clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
665 			"vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
666 			aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
667 	clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
668 	clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
669 
670 	clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
671 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
672 			SPEAR1340_SDHCI_CLK_ENB, 0, &_lock);
673 	clk_register_clkdev(clk, NULL, "b3000000.sdhci");
674 
675 	clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
676 			0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl,
677 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
678 	clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
679 	clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
680 
681 	clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
682 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
683 			SPEAR1340_CFXD_CLK_ENB, 0, &_lock);
684 	clk_register_clkdev(clk, NULL, "b2800000.cf");
685 	clk_register_clkdev(clk, NULL, "arasan_xd");
686 
687 	clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
688 			SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl,
689 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
690 	clk_register_clkdev(clk, "c3_syn_clk", NULL);
691 	clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
692 
693 	clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
694 			ARRAY_SIZE(c3_parents),
695 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
696 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
697 			SPEAR1340_C3_CLK_MASK, 0, &_lock);
698 	clk_register_clkdev(clk, "c3_mclk", NULL);
699 
700 	clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT,
701 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
702 			&_lock);
703 	clk_register_clkdev(clk, NULL, "e1800000.c3");
704 
705 	/* gmac */
706 	clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
707 			ARRAY_SIZE(gmac_phy_input_parents),
708 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
709 			SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
710 			SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
711 	clk_register_clkdev(clk, "phy_input_mclk", NULL);
712 
713 	clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
714 			0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl,
715 			ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
716 	clk_register_clkdev(clk, "phy_syn_clk", NULL);
717 	clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
718 
719 	clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
720 			ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
721 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
722 			SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
723 	clk_register_clkdev(clk, "stmmacphy.0", NULL);
724 
725 	/* clcd */
726 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
727 			ARRAY_SIZE(clcd_synth_parents),
728 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
729 			SPEAR1340_CLCD_SYNT_CLK_SHIFT,
730 			SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
731 	clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
732 
733 	clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
734 			SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
735 			ARRAY_SIZE(clcd_rtbl), &_lock);
736 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
737 
738 	clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
739 			ARRAY_SIZE(clcd_pixel_parents),
740 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
741 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
742 			SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
743 	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
744 
745 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
746 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
747 			&_lock);
748 	clk_register_clkdev(clk, NULL, "e1000000.clcd");
749 
750 	/* i2s */
751 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
752 			ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
753 			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
754 			SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
755 	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
756 
757 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
758 			CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG,
759 			&i2s_prs1_masks, i2s_prs1_rtbl,
760 			ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
761 	clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
762 
763 	clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
764 			ARRAY_SIZE(i2s_ref_parents),
765 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
766 			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
767 			SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
768 	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
769 
770 	clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
771 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
772 			0, &_lock);
773 	clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
774 
775 	clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
776 			0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks,
777 			i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock,
778 			&clk1);
779 	clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
780 	clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
781 
782 	/* clock derived from ahb clk */
783 	clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
784 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
785 			&_lock);
786 	clk_register_clkdev(clk, NULL, "e0280000.i2c");
787 
788 	clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
789 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
790 			&_lock);
791 	clk_register_clkdev(clk, NULL, "b4000000.i2c");
792 
793 	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
794 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
795 			&_lock);
796 	clk_register_clkdev(clk, NULL, "ea800000.dma");
797 	clk_register_clkdev(clk, NULL, "eb000000.dma");
798 
799 	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
800 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
801 			&_lock);
802 	clk_register_clkdev(clk, NULL, "e2000000.eth");
803 
804 	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
805 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
806 			&_lock);
807 	clk_register_clkdev(clk, NULL, "b0000000.flash");
808 
809 	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
810 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
811 			&_lock);
812 	clk_register_clkdev(clk, NULL, "ea000000.flash");
813 
814 	clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
815 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
816 			&_lock);
817 	clk_register_clkdev(clk, NULL, "e4000000.ohci");
818 	clk_register_clkdev(clk, NULL, "e4800000.ehci");
819 
820 	clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
821 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
822 			&_lock);
823 	clk_register_clkdev(clk, NULL, "e5000000.ohci");
824 	clk_register_clkdev(clk, NULL, "e5800000.ehci");
825 
826 	clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
827 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
828 			&_lock);
829 	clk_register_clkdev(clk, NULL, "e3800000.otg");
830 
831 	clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
832 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
833 			0, &_lock);
834 	clk_register_clkdev(clk, NULL, "b1000000.pcie");
835 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
836 
837 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
838 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
839 			&_lock);
840 	clk_register_clkdev(clk, "sysram0_clk", NULL);
841 
842 	clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
843 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
844 			&_lock);
845 	clk_register_clkdev(clk, "sysram1_clk", NULL);
846 
847 	clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
848 			0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
849 			ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
850 	clk_register_clkdev(clk, "adc_syn_clk", NULL);
851 	clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
852 
853 	clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
854 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
855 			SPEAR1340_ADC_CLK_ENB, 0, &_lock);
856 	clk_register_clkdev(clk, NULL, "e0080000.adc");
857 
858 	/* clock derived from apb clk */
859 	clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
860 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
861 			&_lock);
862 	clk_register_clkdev(clk, NULL, "e0100000.spi");
863 
864 	clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
865 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
866 			&_lock);
867 	clk_register_clkdev(clk, NULL, "e0600000.gpio");
868 
869 	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
870 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
871 			&_lock);
872 	clk_register_clkdev(clk, NULL, "e0680000.gpio");
873 
874 	clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
875 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
876 			&_lock);
877 	clk_register_clkdev(clk, NULL, "b2400000.i2s-play");
878 
879 	clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
880 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
881 			&_lock);
882 	clk_register_clkdev(clk, NULL, "b2000000.i2s-rec");
883 
884 	clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
885 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
886 			&_lock);
887 	clk_register_clkdev(clk, NULL, "e0300000.kbd");
888 
889 	/* RAS clks */
890 	clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
891 			ARRAY_SIZE(gen_synth0_1_parents),
892 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
893 			SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
894 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
895 	clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
896 
897 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
898 			ARRAY_SIZE(gen_synth2_3_parents),
899 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
900 			SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
901 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
902 	clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
903 
904 	clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
905 			SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
906 			&_lock);
907 	clk_register_clkdev(clk, "gen_syn0_clk", NULL);
908 
909 	clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
910 			SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
911 			&_lock);
912 	clk_register_clkdev(clk, "gen_syn1_clk", NULL);
913 
914 	clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
915 			SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
916 			&_lock);
917 	clk_register_clkdev(clk, "gen_syn2_clk", NULL);
918 
919 	clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
920 			SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
921 			&_lock);
922 	clk_register_clkdev(clk, "gen_syn3_clk", NULL);
923 
924 	clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk",
925 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
926 			SPEAR1340_MALI_CLK_ENB, 0, &_lock);
927 	clk_register_clkdev(clk, NULL, "mali");
928 
929 	clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
930 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
931 			&_lock);
932 	clk_register_clkdev(clk, NULL, "spear_cec.0");
933 
934 	clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
935 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
936 			&_lock);
937 	clk_register_clkdev(clk, NULL, "spear_cec.1");
938 
939 	clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
940 			ARRAY_SIZE(spdif_out_parents),
941 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
942 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
943 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
944 	clk_register_clkdev(clk, "spdif_out_mclk", NULL);
945 
946 	clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk",
947 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
948 			SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock);
949 	clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
950 
951 	clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
952 			ARRAY_SIZE(spdif_in_parents),
953 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
954 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
955 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
956 	clk_register_clkdev(clk, "spdif_in_mclk", NULL);
957 
958 	clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk",
959 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
960 			SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
961 	clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
962 
963 	clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
964 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
965 			&_lock);
966 	clk_register_clkdev(clk, NULL, "acp_clk");
967 
968 	clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
969 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
970 			&_lock);
971 	clk_register_clkdev(clk, NULL, "e2800000.gpio");
972 
973 	clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
974 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
975 			0, &_lock);
976 	clk_register_clkdev(clk, NULL, "video_dec");
977 
978 	clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
979 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
980 			0, &_lock);
981 	clk_register_clkdev(clk, NULL, "video_enc");
982 
983 	clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
984 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
985 			&_lock);
986 	clk_register_clkdev(clk, NULL, "spear_vip");
987 
988 	clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
989 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
990 			&_lock);
991 	clk_register_clkdev(clk, NULL, "d0200000.cam0");
992 
993 	clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
994 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
995 			&_lock);
996 	clk_register_clkdev(clk, NULL, "d0300000.cam1");
997 
998 	clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
999 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
1000 			&_lock);
1001 	clk_register_clkdev(clk, NULL, "d0400000.cam2");
1002 
1003 	clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
1004 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
1005 			&_lock);
1006 	clk_register_clkdev(clk, NULL, "d0500000.cam3");
1007 
1008 	clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
1009 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
1010 			&_lock);
1011 	clk_register_clkdev(clk, NULL, "e0180000.pwm");
1012 }
1013