1 /*
2  * arch/arm/mach-spear13xx/spear1340_clock.c
3  *
4  * SPEAr1340 machine clock framework source file
5  *
6  * Copyright (C) 2012 ST Microelectronics
7  * Viresh Kumar <vireshk@kernel.org>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13 
14 #include <linux/clkdev.h>
15 #include <linux/clk/spear.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/of_platform.h>
19 #include <linux/spinlock_types.h>
20 #include "clk.h"
21 
22 /* Clock Configuration Registers */
23 #define SPEAR1340_SYS_CLK_CTRL			(misc_base + 0x200)
24 	#define SPEAR1340_HCLK_SRC_SEL_SHIFT	27
25 	#define SPEAR1340_HCLK_SRC_SEL_MASK	1
26 	#define SPEAR1340_SCLK_SRC_SEL_SHIFT	23
27 	#define SPEAR1340_SCLK_SRC_SEL_MASK	3
28 
29 /* PLL related registers and bit values */
30 #define SPEAR1340_PLL_CFG			(misc_base + 0x210)
31 	/* PLL_CFG bit values */
32 	#define SPEAR1340_CLCD_SYNT_CLK_MASK		1
33 	#define SPEAR1340_CLCD_SYNT_CLK_SHIFT		31
34 	#define SPEAR1340_GEN_SYNT2_3_CLK_SHIFT		29
35 	#define SPEAR1340_GEN_SYNT_CLK_MASK		2
36 	#define SPEAR1340_GEN_SYNT0_1_CLK_SHIFT		27
37 	#define SPEAR1340_PLL_CLK_MASK			2
38 	#define SPEAR1340_PLL3_CLK_SHIFT		24
39 	#define SPEAR1340_PLL2_CLK_SHIFT		22
40 	#define SPEAR1340_PLL1_CLK_SHIFT		20
41 
42 #define SPEAR1340_PLL1_CTR			(misc_base + 0x214)
43 #define SPEAR1340_PLL1_FRQ			(misc_base + 0x218)
44 #define SPEAR1340_PLL2_CTR			(misc_base + 0x220)
45 #define SPEAR1340_PLL2_FRQ			(misc_base + 0x224)
46 #define SPEAR1340_PLL3_CTR			(misc_base + 0x22C)
47 #define SPEAR1340_PLL3_FRQ			(misc_base + 0x230)
48 #define SPEAR1340_PLL4_CTR			(misc_base + 0x238)
49 #define SPEAR1340_PLL4_FRQ			(misc_base + 0x23C)
50 #define SPEAR1340_PERIP_CLK_CFG			(misc_base + 0x244)
51 	/* PERIP_CLK_CFG bit values */
52 	#define SPEAR1340_SPDIF_CLK_MASK		1
53 	#define SPEAR1340_SPDIF_OUT_CLK_SHIFT		15
54 	#define SPEAR1340_SPDIF_IN_CLK_SHIFT		14
55 	#define SPEAR1340_GPT3_CLK_SHIFT		13
56 	#define SPEAR1340_GPT2_CLK_SHIFT		12
57 	#define SPEAR1340_GPT_CLK_MASK			1
58 	#define SPEAR1340_GPT1_CLK_SHIFT		9
59 	#define SPEAR1340_GPT0_CLK_SHIFT		8
60 	#define SPEAR1340_UART_CLK_MASK			2
61 	#define SPEAR1340_UART1_CLK_SHIFT		6
62 	#define SPEAR1340_UART0_CLK_SHIFT		4
63 	#define SPEAR1340_CLCD_CLK_MASK			2
64 	#define SPEAR1340_CLCD_CLK_SHIFT		2
65 	#define SPEAR1340_C3_CLK_MASK			1
66 	#define SPEAR1340_C3_CLK_SHIFT			1
67 
68 #define SPEAR1340_GMAC_CLK_CFG			(misc_base + 0x248)
69 	#define SPEAR1340_GMAC_PHY_CLK_MASK		1
70 	#define SPEAR1340_GMAC_PHY_CLK_SHIFT		2
71 	#define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK	2
72 	#define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT	0
73 
74 #define SPEAR1340_I2S_CLK_CFG			(misc_base + 0x24C)
75 	/* I2S_CLK_CFG register mask */
76 	#define SPEAR1340_I2S_SCLK_X_MASK		0x1F
77 	#define SPEAR1340_I2S_SCLK_X_SHIFT		27
78 	#define SPEAR1340_I2S_SCLK_Y_MASK		0x1F
79 	#define SPEAR1340_I2S_SCLK_Y_SHIFT		22
80 	#define SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT		21
81 	#define SPEAR1340_I2S_SCLK_SYNTH_ENB		20
82 	#define SPEAR1340_I2S_PRS1_CLK_X_MASK		0xFF
83 	#define SPEAR1340_I2S_PRS1_CLK_X_SHIFT		12
84 	#define SPEAR1340_I2S_PRS1_CLK_Y_MASK		0xFF
85 	#define SPEAR1340_I2S_PRS1_CLK_Y_SHIFT		4
86 	#define SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT		3
87 	#define SPEAR1340_I2S_REF_SEL_MASK		1
88 	#define SPEAR1340_I2S_REF_SHIFT			2
89 	#define SPEAR1340_I2S_SRC_CLK_MASK		2
90 	#define SPEAR1340_I2S_SRC_CLK_SHIFT		0
91 
92 #define SPEAR1340_C3_CLK_SYNT			(misc_base + 0x250)
93 #define SPEAR1340_UART0_CLK_SYNT		(misc_base + 0x254)
94 #define SPEAR1340_UART1_CLK_SYNT		(misc_base + 0x258)
95 #define SPEAR1340_GMAC_CLK_SYNT			(misc_base + 0x25C)
96 #define SPEAR1340_SDHCI_CLK_SYNT		(misc_base + 0x260)
97 #define SPEAR1340_CFXD_CLK_SYNT			(misc_base + 0x264)
98 #define SPEAR1340_ADC_CLK_SYNT			(misc_base + 0x270)
99 #define SPEAR1340_AMBA_CLK_SYNT			(misc_base + 0x274)
100 #define SPEAR1340_CLCD_CLK_SYNT			(misc_base + 0x27C)
101 #define SPEAR1340_SYS_CLK_SYNT			(misc_base + 0x284)
102 #define SPEAR1340_GEN_CLK_SYNT0			(misc_base + 0x28C)
103 #define SPEAR1340_GEN_CLK_SYNT1			(misc_base + 0x294)
104 #define SPEAR1340_GEN_CLK_SYNT2			(misc_base + 0x29C)
105 #define SPEAR1340_GEN_CLK_SYNT3			(misc_base + 0x304)
106 #define SPEAR1340_PERIP1_CLK_ENB		(misc_base + 0x30C)
107 	#define SPEAR1340_RTC_CLK_ENB			31
108 	#define SPEAR1340_ADC_CLK_ENB			30
109 	#define SPEAR1340_C3_CLK_ENB			29
110 	#define SPEAR1340_CLCD_CLK_ENB			27
111 	#define SPEAR1340_DMA_CLK_ENB			25
112 	#define SPEAR1340_GPIO1_CLK_ENB			24
113 	#define SPEAR1340_GPIO0_CLK_ENB			23
114 	#define SPEAR1340_GPT1_CLK_ENB			22
115 	#define SPEAR1340_GPT0_CLK_ENB			21
116 	#define SPEAR1340_I2S_PLAY_CLK_ENB		20
117 	#define SPEAR1340_I2S_REC_CLK_ENB		19
118 	#define SPEAR1340_I2C0_CLK_ENB			18
119 	#define SPEAR1340_SSP_CLK_ENB			17
120 	#define SPEAR1340_UART0_CLK_ENB			15
121 	#define SPEAR1340_PCIE_SATA_CLK_ENB		12
122 	#define SPEAR1340_UOC_CLK_ENB			11
123 	#define SPEAR1340_UHC1_CLK_ENB			10
124 	#define SPEAR1340_UHC0_CLK_ENB			9
125 	#define SPEAR1340_GMAC_CLK_ENB			8
126 	#define SPEAR1340_CFXD_CLK_ENB			7
127 	#define SPEAR1340_SDHCI_CLK_ENB			6
128 	#define SPEAR1340_SMI_CLK_ENB			5
129 	#define SPEAR1340_FSMC_CLK_ENB			4
130 	#define SPEAR1340_SYSRAM0_CLK_ENB		3
131 	#define SPEAR1340_SYSRAM1_CLK_ENB		2
132 	#define SPEAR1340_SYSROM_CLK_ENB		1
133 	#define SPEAR1340_BUS_CLK_ENB			0
134 
135 #define SPEAR1340_PERIP2_CLK_ENB		(misc_base + 0x310)
136 	#define SPEAR1340_THSENS_CLK_ENB		8
137 	#define SPEAR1340_I2S_REF_PAD_CLK_ENB		7
138 	#define SPEAR1340_ACP_CLK_ENB			6
139 	#define SPEAR1340_GPT3_CLK_ENB			5
140 	#define SPEAR1340_GPT2_CLK_ENB			4
141 	#define SPEAR1340_KBD_CLK_ENB			3
142 	#define SPEAR1340_CPU_DBG_CLK_ENB		2
143 	#define SPEAR1340_DDR_CORE_CLK_ENB		1
144 	#define SPEAR1340_DDR_CTRL_CLK_ENB		0
145 
146 #define SPEAR1340_PERIP3_CLK_ENB		(misc_base + 0x314)
147 	#define SPEAR1340_PLGPIO_CLK_ENB		18
148 	#define SPEAR1340_VIDEO_DEC_CLK_ENB		16
149 	#define SPEAR1340_VIDEO_ENC_CLK_ENB		15
150 	#define SPEAR1340_SPDIF_OUT_CLK_ENB		13
151 	#define SPEAR1340_SPDIF_IN_CLK_ENB		12
152 	#define SPEAR1340_VIDEO_IN_CLK_ENB		11
153 	#define SPEAR1340_CAM0_CLK_ENB			10
154 	#define SPEAR1340_CAM1_CLK_ENB			9
155 	#define SPEAR1340_CAM2_CLK_ENB			8
156 	#define SPEAR1340_CAM3_CLK_ENB			7
157 	#define SPEAR1340_MALI_CLK_ENB			6
158 	#define SPEAR1340_CEC0_CLK_ENB			5
159 	#define SPEAR1340_CEC1_CLK_ENB			4
160 	#define SPEAR1340_PWM_CLK_ENB			3
161 	#define SPEAR1340_I2C1_CLK_ENB			2
162 	#define SPEAR1340_UART1_CLK_ENB			1
163 
164 static DEFINE_SPINLOCK(_lock);
165 
166 /* pll rate configuration table, in ascending order of rates */
167 static struct pll_rate_tbl pll_rtbl[] = {
168 	/* PCLK 24MHz */
169 	{.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
170 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
171 	{.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
172 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
173 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
174 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
176 	{.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
177 };
178 
179 /* vco-pll4 rate configuration table, in ascending order of rates */
180 static struct pll_rate_tbl pll4_rtbl[] = {
181 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
182 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
183 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
184 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
185 };
186 
187 /*
188  * All below entries generate 166 MHz for
189  * different values of vco1div2
190  */
191 static struct frac_rate_tbl amba_synth_rtbl[] = {
192 	{.div = 0x073A8}, /* for vco1div2 = 600 MHz */
193 	{.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 	{.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 	{.div = 0x04000}, /* for vco1div2 = 332 MHz */
196 	{.div = 0x03031}, /* for vco1div2 = 250 MHz */
197 	{.div = 0x0268D}, /* for vco1div2 = 200 MHz */
198 };
199 
200 /*
201  * Synthesizer Clock derived from vcodiv2. This clock is one of the
202  * possible clocks to feed cpu directly.
203  * We can program this synthesizer to make cpu run on different clock
204  * frequencies.
205  * Following table provides configuration values to let cpu run on 200,
206  * 250, 332, 400 or 500 MHz considering different possibilites of input
207  * (vco1div2) clock.
208  *
209  * --------------------------------------------------------------------
210  * vco1div2(Mhz)	fout(Mhz)	cpuclk = fout/2		div
211  * --------------------------------------------------------------------
212  * 400			200		100			0x04000
213  * 400			250		125			0x03333
214  * 400			332		166			0x0268D
215  * 400			400		200			0x02000
216  * --------------------------------------------------------------------
217  * 500			200		100			0x05000
218  * 500			250		125			0x04000
219  * 500			332		166			0x03031
220  * 500			400		200			0x02800
221  * 500			500		250			0x02000
222  * --------------------------------------------------------------------
223  * 600			200		100			0x06000
224  * 600			250		125			0x04CCE
225  * 600			332		166			0x039D5
226  * 600			400		200			0x03000
227  * 600			500		250			0x02666
228  * --------------------------------------------------------------------
229  * 664			200		100			0x06a38
230  * 664			250		125			0x054FD
231  * 664			332		166			0x04000
232  * 664			400		200			0x0351E
233  * 664			500		250			0x02A7E
234  * --------------------------------------------------------------------
235  * 800			200		100			0x08000
236  * 800			250		125			0x06666
237  * 800			332		166			0x04D18
238  * 800			400		200			0x04000
239  * 800			500		250			0x03333
240  * --------------------------------------------------------------------
241  * sys rate configuration table is in descending order of divisor.
242  */
243 static struct frac_rate_tbl sys_synth_rtbl[] = {
244 	{.div = 0x08000},
245 	{.div = 0x06a38},
246 	{.div = 0x06666},
247 	{.div = 0x06000},
248 	{.div = 0x054FD},
249 	{.div = 0x05000},
250 	{.div = 0x04D18},
251 	{.div = 0x04CCE},
252 	{.div = 0x04000},
253 	{.div = 0x039D5},
254 	{.div = 0x0351E},
255 	{.div = 0x03333},
256 	{.div = 0x03031},
257 	{.div = 0x03000},
258 	{.div = 0x02A7E},
259 	{.div = 0x02800},
260 	{.div = 0x0268D},
261 	{.div = 0x02666},
262 	{.div = 0x02000},
263 };
264 
265 /* aux rate configuration table, in ascending order of rates */
266 static struct aux_rate_tbl aux_rtbl[] = {
267 	/* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */
268 	{.xscale = 5, .yscale = 122, .eq = 0},
269 	/* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */
270 	{.xscale = 10, .yscale = 204, .eq = 0},
271 	/* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */
272 	{.xscale = 4, .yscale = 25, .eq = 0},
273 	/* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */
274 	{.xscale = 4, .yscale = 21, .eq = 0},
275 	/* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */
276 	{.xscale = 5, .yscale = 18, .eq = 0},
277 	/* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */
278 	{.xscale = 2, .yscale = 6, .eq = 0},
279 	/* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */
280 	{.xscale = 5, .yscale = 12, .eq = 0},
281 	/* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */
282 	{.xscale = 2, .yscale = 4, .eq = 0},
283 	/* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */
284 	{.xscale = 5, .yscale = 18, .eq = 1},
285 	/* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */
286 	{.xscale = 1, .yscale = 3, .eq = 1},
287 	/* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */
288 	{.xscale = 5, .yscale = 12, .eq = 1},
289 	/* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */
290 	{.xscale = 1, .yscale = 2, .eq = 1},
291 };
292 
293 /* gmac rate configuration table, in ascending order of rates */
294 static struct aux_rate_tbl gmac_rtbl[] = {
295 	/* For gmac phy input clk */
296 	{.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
297 	{.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
298 	{.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
299 	{.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
300 };
301 
302 /* clcd rate configuration table, in ascending order of rates */
303 static struct frac_rate_tbl clcd_rtbl[] = {
304 	{.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
305 	{.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
306 	{.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
307 	{.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
308 	{.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
309 	{.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
310 	{.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
311 	{.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
312 	{.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
313 	{.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
314 	{.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
315 	{.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
316 	{.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
317 	{.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
318 	{.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
319 	{.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
320 	{.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
321 	{.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
322 	{.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
323 	{.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
324 };
325 
326 /* i2s prescaler1 masks */
327 static const struct aux_clk_masks i2s_prs1_masks = {
328 	.eq_sel_mask = AUX_EQ_SEL_MASK,
329 	.eq_sel_shift = SPEAR1340_I2S_PRS1_EQ_SEL_SHIFT,
330 	.eq1_mask = AUX_EQ1_SEL,
331 	.eq2_mask = AUX_EQ2_SEL,
332 	.xscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_X_MASK,
333 	.xscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_X_SHIFT,
334 	.yscale_sel_mask = SPEAR1340_I2S_PRS1_CLK_Y_MASK,
335 	.yscale_sel_shift = SPEAR1340_I2S_PRS1_CLK_Y_SHIFT,
336 };
337 
338 /* i2s sclk (bit clock) syynthesizers masks */
339 static const struct aux_clk_masks i2s_sclk_masks = {
340 	.eq_sel_mask = AUX_EQ_SEL_MASK,
341 	.eq_sel_shift = SPEAR1340_I2S_SCLK_EQ_SEL_SHIFT,
342 	.eq1_mask = AUX_EQ1_SEL,
343 	.eq2_mask = AUX_EQ2_SEL,
344 	.xscale_sel_mask = SPEAR1340_I2S_SCLK_X_MASK,
345 	.xscale_sel_shift = SPEAR1340_I2S_SCLK_X_SHIFT,
346 	.yscale_sel_mask = SPEAR1340_I2S_SCLK_Y_MASK,
347 	.yscale_sel_shift = SPEAR1340_I2S_SCLK_Y_SHIFT,
348 	.enable_bit = SPEAR1340_I2S_SCLK_SYNTH_ENB,
349 };
350 
351 /* i2s prs1 aux rate configuration table, in ascending order of rates */
352 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
353 	/* For parent clk = 49.152 MHz */
354 	{.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
355 	{.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
356 	{.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
357 	{.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
358 
359 	/*
360 	 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
361 	 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
362 	 */
363 	{.xscale = 1, .yscale = 3, .eq = 0},
364 
365 	/* For parent clk = 49.152 MHz */
366 	{.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
367 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz, smp freq = 48Khz*/
368 };
369 
370 /* i2s sclk aux rate configuration table, in ascending order of rates */
371 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
372 	/* For sclk = ref_clk * x/2/y */
373 	{.xscale = 1, .yscale = 4, .eq = 0},
374 	{.xscale = 1, .yscale = 2, .eq = 0},
375 };
376 
377 /* adc rate configuration table, in ascending order of rates */
378 /* possible adc range is 2.5 MHz to 20 MHz. */
379 static struct aux_rate_tbl adc_rtbl[] = {
380 	/* For ahb = 166.67 MHz */
381 	{.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
382 	{.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
383 	{.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
384 	{.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
385 };
386 
387 /* General synth rate configuration table, in ascending order of rates */
388 static struct frac_rate_tbl gen_rtbl[] = {
389 	{.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
390 	{.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
391 	{.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
392 	{.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
393 	{.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
394 	{.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
395 	{.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
396 	{.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
397 	{.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
398 	{.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
399 	{.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
400 	{.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
401 	{.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
402 	{.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
403 	{.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
404 	{.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
405 	{.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
406 	{.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
407 	{.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
408 	{.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
409 	{.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
410 	{.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
411 	{.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
412 	{.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
413 	{.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
414 };
415 
416 /* clock parents */
417 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
418 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
419 	"pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
420 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
421 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
422 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
423 	"uart0_syn_gclk", };
424 static const char *uart1_parents[] = { "pll5_clk", "osc_24m_clk",
425 	"uart1_syn_gclk", };
426 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
427 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
428 	"osc_25m_clk", };
429 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
430 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
431 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
432 static const char *i2s_src_parents[] = { "vco1div2_clk", "pll2_clk", "pll3_clk",
433 	"i2s_src_pad_clk", };
434 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
435 static const char *spdif_out_parents[] = { "i2s_src_pad_clk", "gen_syn2_clk", };
436 static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
437 
438 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
439 	"pll3_clk", };
440 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
441 	"pll2_clk", };
442 
443 void __init spear1340_clk_init(void __iomem *misc_base)
444 {
445 	struct clk *clk, *clk1;
446 
447 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
448 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
449 
450 	clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000);
451 	clk_register_clkdev(clk, "osc_24m_clk", NULL);
452 
453 	clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000);
454 	clk_register_clkdev(clk, "osc_25m_clk", NULL);
455 
456 	clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000);
457 	clk_register_clkdev(clk, "gmii_pad_clk", NULL);
458 
459 	clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0,
460 				      12288000);
461 	clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
462 
463 	/* clock derived from 32 KHz osc clk */
464 	clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
465 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
466 			&_lock);
467 	clk_register_clkdev(clk, NULL, "e0580000.rtc");
468 
469 	/* clock derived from 24 or 25 MHz osc clk */
470 	/* vco-pll */
471 	clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
472 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
473 			SPEAR1340_PLL_CFG, SPEAR1340_PLL1_CLK_SHIFT,
474 			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
475 	clk_register_clkdev(clk, "vco1_mclk", NULL);
476 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0,
477 			SPEAR1340_PLL1_CTR, SPEAR1340_PLL1_FRQ, pll_rtbl,
478 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
479 	clk_register_clkdev(clk, "vco1_clk", NULL);
480 	clk_register_clkdev(clk1, "pll1_clk", NULL);
481 
482 	clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
483 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
484 			SPEAR1340_PLL_CFG, SPEAR1340_PLL2_CLK_SHIFT,
485 			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
486 	clk_register_clkdev(clk, "vco2_mclk", NULL);
487 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0,
488 			SPEAR1340_PLL2_CTR, SPEAR1340_PLL2_FRQ, pll_rtbl,
489 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
490 	clk_register_clkdev(clk, "vco2_clk", NULL);
491 	clk_register_clkdev(clk1, "pll2_clk", NULL);
492 
493 	clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
494 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
495 			SPEAR1340_PLL_CFG, SPEAR1340_PLL3_CLK_SHIFT,
496 			SPEAR1340_PLL_CLK_MASK, 0, &_lock);
497 	clk_register_clkdev(clk, "vco3_mclk", NULL);
498 	clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0,
499 			SPEAR1340_PLL3_CTR, SPEAR1340_PLL3_FRQ, pll_rtbl,
500 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
501 	clk_register_clkdev(clk, "vco3_clk", NULL);
502 	clk_register_clkdev(clk1, "pll3_clk", NULL);
503 
504 	clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
505 			0, SPEAR1340_PLL4_CTR, SPEAR1340_PLL4_FRQ, pll4_rtbl,
506 			ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
507 	clk_register_clkdev(clk, "vco4_clk", NULL);
508 	clk_register_clkdev(clk1, "pll4_clk", NULL);
509 
510 	clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
511 			48000000);
512 	clk_register_clkdev(clk, "pll5_clk", NULL);
513 
514 	clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
515 			25000000);
516 	clk_register_clkdev(clk, "pll6_clk", NULL);
517 
518 	/* vco div n clocks */
519 	clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
520 			2);
521 	clk_register_clkdev(clk, "vco1div2_clk", NULL);
522 
523 	clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
524 			4);
525 	clk_register_clkdev(clk, "vco1div4_clk", NULL);
526 
527 	clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
528 			2);
529 	clk_register_clkdev(clk, "vco2div2_clk", NULL);
530 
531 	clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
532 			2);
533 	clk_register_clkdev(clk, "vco3div2_clk", NULL);
534 
535 	/* peripherals */
536 	clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
537 			128);
538 	clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
539 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
540 			&_lock);
541 	clk_register_clkdev(clk, NULL, "e07008c4.thermal");
542 
543 	/* clock derived from pll4 clk */
544 	clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
545 			1);
546 	clk_register_clkdev(clk, "ddr_clk", NULL);
547 
548 	/* clock derived from pll1 clk */
549 	clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0,
550 			SPEAR1340_SYS_CLK_SYNT, sys_synth_rtbl,
551 			ARRAY_SIZE(sys_synth_rtbl), &_lock);
552 	clk_register_clkdev(clk, "sys_syn_clk", NULL);
553 
554 	clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0,
555 			SPEAR1340_AMBA_CLK_SYNT, amba_synth_rtbl,
556 			ARRAY_SIZE(amba_synth_rtbl), &_lock);
557 	clk_register_clkdev(clk, "amba_syn_clk", NULL);
558 
559 	clk = clk_register_mux(NULL, "sys_mclk", sys_parents,
560 			ARRAY_SIZE(sys_parents), CLK_SET_RATE_NO_REPARENT,
561 			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_SCLK_SRC_SEL_SHIFT,
562 			SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
563 	clk_register_clkdev(clk, "sys_mclk", NULL);
564 
565 	clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
566 			2);
567 	clk_register_clkdev(clk, "cpu_clk", NULL);
568 
569 	clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1,
570 			3);
571 	clk_register_clkdev(clk, "cpu_div3_clk", NULL);
572 
573 	clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
574 			2);
575 	clk_register_clkdev(clk, NULL, "ec800620.wdt");
576 
577 	clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
578 			2);
579 	clk_register_clkdev(clk, NULL, "smp_twd");
580 
581 	clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
582 			ARRAY_SIZE(ahb_parents), CLK_SET_RATE_NO_REPARENT,
583 			SPEAR1340_SYS_CLK_CTRL, SPEAR1340_HCLK_SRC_SEL_SHIFT,
584 			SPEAR1340_HCLK_SRC_SEL_MASK, 0, &_lock);
585 	clk_register_clkdev(clk, "ahb_clk", NULL);
586 
587 	clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
588 			2);
589 	clk_register_clkdev(clk, "apb_clk", NULL);
590 
591 	/* gpt clocks */
592 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
593 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
594 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT0_CLK_SHIFT,
595 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
596 	clk_register_clkdev(clk, "gpt0_mclk", NULL);
597 	clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
598 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT0_CLK_ENB, 0,
599 			&_lock);
600 	clk_register_clkdev(clk, NULL, "gpt0");
601 
602 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
603 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
604 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT1_CLK_SHIFT,
605 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
606 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
607 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
608 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPT1_CLK_ENB, 0,
609 			&_lock);
610 	clk_register_clkdev(clk, NULL, "gpt1");
611 
612 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
613 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
614 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT2_CLK_SHIFT,
615 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
616 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
617 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
618 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT2_CLK_ENB, 0,
619 			&_lock);
620 	clk_register_clkdev(clk, NULL, "gpt2");
621 
622 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
623 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
624 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GPT3_CLK_SHIFT,
625 			SPEAR1340_GPT_CLK_MASK, 0, &_lock);
626 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
627 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
628 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_GPT3_CLK_ENB, 0,
629 			&_lock);
630 	clk_register_clkdev(clk, NULL, "gpt3");
631 
632 	/* others */
633 	clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk",
634 			"vco1div2_clk", 0, SPEAR1340_UART0_CLK_SYNT, NULL,
635 			aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
636 	clk_register_clkdev(clk, "uart0_syn_clk", NULL);
637 	clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
638 
639 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
640 			ARRAY_SIZE(uart0_parents),
641 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
642 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
643 			SPEAR1340_UART_CLK_MASK, 0, &_lock);
644 	clk_register_clkdev(clk, "uart0_mclk", NULL);
645 
646 	clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
647 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
648 			SPEAR1340_UART0_CLK_ENB, 0, &_lock);
649 	clk_register_clkdev(clk, NULL, "e0000000.serial");
650 
651 	clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
652 			"vco1div2_clk", 0, SPEAR1340_UART1_CLK_SYNT, NULL,
653 			aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
654 	clk_register_clkdev(clk, "uart1_syn_clk", NULL);
655 	clk_register_clkdev(clk1, "uart1_syn_gclk", NULL);
656 
657 	clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents,
658 			ARRAY_SIZE(uart1_parents), CLK_SET_RATE_NO_REPARENT,
659 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART1_CLK_SHIFT,
660 			SPEAR1340_UART_CLK_MASK, 0, &_lock);
661 	clk_register_clkdev(clk, "uart1_mclk", NULL);
662 
663 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
664 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_UART1_CLK_ENB, 0,
665 			&_lock);
666 	clk_register_clkdev(clk, NULL, "b4100000.serial");
667 
668 	clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
669 			"vco1div2_clk", 0, SPEAR1340_SDHCI_CLK_SYNT, NULL,
670 			aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
671 	clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
672 	clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
673 
674 	clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
675 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
676 			SPEAR1340_SDHCI_CLK_ENB, 0, &_lock);
677 	clk_register_clkdev(clk, NULL, "b3000000.sdhci");
678 
679 	clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
680 			0, SPEAR1340_CFXD_CLK_SYNT, NULL, aux_rtbl,
681 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
682 	clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
683 	clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
684 
685 	clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
686 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
687 			SPEAR1340_CFXD_CLK_ENB, 0, &_lock);
688 	clk_register_clkdev(clk, NULL, "b2800000.cf");
689 	clk_register_clkdev(clk, NULL, "arasan_xd");
690 
691 	clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0,
692 			SPEAR1340_C3_CLK_SYNT, NULL, aux_rtbl,
693 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
694 	clk_register_clkdev(clk, "c3_syn_clk", NULL);
695 	clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
696 
697 	clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
698 			ARRAY_SIZE(c3_parents),
699 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
700 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
701 			SPEAR1340_C3_CLK_MASK, 0, &_lock);
702 	clk_register_clkdev(clk, "c3_mclk", NULL);
703 
704 	clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT,
705 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
706 			&_lock);
707 	clk_register_clkdev(clk, NULL, "e1800000.c3");
708 
709 	/* gmac */
710 	clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
711 			ARRAY_SIZE(gmac_phy_input_parents),
712 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_GMAC_CLK_CFG,
713 			SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT,
714 			SPEAR1340_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
715 	clk_register_clkdev(clk, "phy_input_mclk", NULL);
716 
717 	clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
718 			0, SPEAR1340_GMAC_CLK_SYNT, NULL, gmac_rtbl,
719 			ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
720 	clk_register_clkdev(clk, "phy_syn_clk", NULL);
721 	clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
722 
723 	clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
724 			ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
725 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
726 			SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
727 	clk_register_clkdev(clk, "stmmacphy.0", NULL);
728 
729 	/* clcd */
730 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
731 			ARRAY_SIZE(clcd_synth_parents),
732 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_CLCD_CLK_SYNT,
733 			SPEAR1340_CLCD_SYNT_CLK_SHIFT,
734 			SPEAR1340_CLCD_SYNT_CLK_MASK, 0, &_lock);
735 	clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
736 
737 	clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
738 			SPEAR1340_CLCD_CLK_SYNT, clcd_rtbl,
739 			ARRAY_SIZE(clcd_rtbl), &_lock);
740 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
741 
742 	clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
743 			ARRAY_SIZE(clcd_pixel_parents),
744 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
745 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
746 			SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
747 	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
748 
749 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
750 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
751 			&_lock);
752 	clk_register_clkdev(clk, NULL, "e1000000.clcd");
753 
754 	/* i2s */
755 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
756 			ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
757 			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_SRC_CLK_SHIFT,
758 			SPEAR1340_I2S_SRC_CLK_MASK, 0, &_lock);
759 	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
760 
761 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
762 			CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG,
763 			&i2s_prs1_masks, i2s_prs1_rtbl,
764 			ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
765 	clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
766 
767 	clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
768 			ARRAY_SIZE(i2s_ref_parents),
769 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
770 			SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
771 			SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
772 	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
773 
774 	clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
775 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
776 			0, &_lock);
777 	clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
778 
779 	clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk",
780 			0, SPEAR1340_I2S_CLK_CFG, &i2s_sclk_masks,
781 			i2s_sclk_rtbl, ARRAY_SIZE(i2s_sclk_rtbl), &_lock,
782 			&clk1);
783 	clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
784 	clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
785 
786 	/* clock derived from ahb clk */
787 	clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
788 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2C0_CLK_ENB, 0,
789 			&_lock);
790 	clk_register_clkdev(clk, NULL, "e0280000.i2c");
791 
792 	clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0,
793 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_I2C1_CLK_ENB, 0,
794 			&_lock);
795 	clk_register_clkdev(clk, NULL, "b4000000.i2c");
796 
797 	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
798 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_DMA_CLK_ENB, 0,
799 			&_lock);
800 	clk_register_clkdev(clk, NULL, "ea800000.dma");
801 	clk_register_clkdev(clk, NULL, "eb000000.dma");
802 
803 	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
804 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GMAC_CLK_ENB, 0,
805 			&_lock);
806 	clk_register_clkdev(clk, NULL, "e2000000.eth");
807 
808 	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
809 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_FSMC_CLK_ENB, 0,
810 			&_lock);
811 	clk_register_clkdev(clk, NULL, "b0000000.flash");
812 
813 	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
814 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SMI_CLK_ENB, 0,
815 			&_lock);
816 	clk_register_clkdev(clk, NULL, "ea000000.flash");
817 
818 	clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
819 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
820 			&_lock);
821 	clk_register_clkdev(clk, NULL, "e4000000.ohci");
822 	clk_register_clkdev(clk, NULL, "e4800000.ehci");
823 
824 	clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
825 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
826 			&_lock);
827 	clk_register_clkdev(clk, NULL, "e5000000.ohci");
828 	clk_register_clkdev(clk, NULL, "e5800000.ehci");
829 
830 	clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
831 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
832 			&_lock);
833 	clk_register_clkdev(clk, NULL, "e3800000.otg");
834 
835 	clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
836 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
837 			0, &_lock);
838 	clk_register_clkdev(clk, NULL, "b1000000.pcie");
839 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
840 
841 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
842 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
843 			&_lock);
844 	clk_register_clkdev(clk, "sysram0_clk", NULL);
845 
846 	clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
847 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM1_CLK_ENB, 0,
848 			&_lock);
849 	clk_register_clkdev(clk, "sysram1_clk", NULL);
850 
851 	clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
852 			0, SPEAR1340_ADC_CLK_SYNT, NULL, adc_rtbl,
853 			ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
854 	clk_register_clkdev(clk, "adc_syn_clk", NULL);
855 	clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
856 
857 	clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
858 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
859 			SPEAR1340_ADC_CLK_ENB, 0, &_lock);
860 	clk_register_clkdev(clk, NULL, "e0080000.adc");
861 
862 	/* clock derived from apb clk */
863 	clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
864 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SSP_CLK_ENB, 0,
865 			&_lock);
866 	clk_register_clkdev(clk, NULL, "e0100000.spi");
867 
868 	clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
869 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO0_CLK_ENB, 0,
870 			&_lock);
871 	clk_register_clkdev(clk, NULL, "e0600000.gpio");
872 
873 	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
874 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_GPIO1_CLK_ENB, 0,
875 			&_lock);
876 	clk_register_clkdev(clk, NULL, "e0680000.gpio");
877 
878 	clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
879 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
880 			&_lock);
881 	clk_register_clkdev(clk, NULL, "b2400000.i2s-play");
882 
883 	clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
884 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
885 			&_lock);
886 	clk_register_clkdev(clk, NULL, "b2000000.i2s-rec");
887 
888 	clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
889 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
890 			&_lock);
891 	clk_register_clkdev(clk, NULL, "e0300000.kbd");
892 
893 	/* RAS clks */
894 	clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
895 			ARRAY_SIZE(gen_synth0_1_parents),
896 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
897 			SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
898 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
899 	clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
900 
901 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
902 			ARRAY_SIZE(gen_synth2_3_parents),
903 			CLK_SET_RATE_NO_REPARENT, SPEAR1340_PLL_CFG,
904 			SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
905 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
906 	clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
907 
908 	clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
909 			SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
910 			&_lock);
911 	clk_register_clkdev(clk, "gen_syn0_clk", NULL);
912 
913 	clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
914 			SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
915 			&_lock);
916 	clk_register_clkdev(clk, "gen_syn1_clk", NULL);
917 
918 	clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
919 			SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
920 			&_lock);
921 	clk_register_clkdev(clk, "gen_syn2_clk", NULL);
922 
923 	clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
924 			SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
925 			&_lock);
926 	clk_register_clkdev(clk, "gen_syn3_clk", NULL);
927 
928 	clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk",
929 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
930 			SPEAR1340_MALI_CLK_ENB, 0, &_lock);
931 	clk_register_clkdev(clk, NULL, "mali");
932 
933 	clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
934 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC0_CLK_ENB, 0,
935 			&_lock);
936 	clk_register_clkdev(clk, NULL, "spear_cec.0");
937 
938 	clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0,
939 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CEC1_CLK_ENB, 0,
940 			&_lock);
941 	clk_register_clkdev(clk, NULL, "spear_cec.1");
942 
943 	clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
944 			ARRAY_SIZE(spdif_out_parents),
945 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
946 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
947 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
948 	clk_register_clkdev(clk, "spdif_out_mclk", NULL);
949 
950 	clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk",
951 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
952 			SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock);
953 	clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
954 
955 	clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
956 			ARRAY_SIZE(spdif_in_parents),
957 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
958 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
959 			SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
960 	clk_register_clkdev(clk, "spdif_in_mclk", NULL);
961 
962 	clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk",
963 			CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
964 			SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
965 	clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
966 
967 	clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
968 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
969 			&_lock);
970 	clk_register_clkdev(clk, NULL, "acp_clk");
971 
972 	clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
973 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
974 			&_lock);
975 	clk_register_clkdev(clk, NULL, "e2800000.gpio");
976 
977 	clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
978 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
979 			0, &_lock);
980 	clk_register_clkdev(clk, NULL, "video_dec");
981 
982 	clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
983 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
984 			0, &_lock);
985 	clk_register_clkdev(clk, NULL, "video_enc");
986 
987 	clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
988 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
989 			&_lock);
990 	clk_register_clkdev(clk, NULL, "spear_vip");
991 
992 	clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
993 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
994 			&_lock);
995 	clk_register_clkdev(clk, NULL, "d0200000.cam0");
996 
997 	clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
998 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
999 			&_lock);
1000 	clk_register_clkdev(clk, NULL, "d0300000.cam1");
1001 
1002 	clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
1003 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
1004 			&_lock);
1005 	clk_register_clkdev(clk, NULL, "d0400000.cam2");
1006 
1007 	clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
1008 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
1009 			&_lock);
1010 	clk_register_clkdev(clk, NULL, "d0500000.cam3");
1011 
1012 	clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
1013 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
1014 			&_lock);
1015 	clk_register_clkdev(clk, NULL, "e0180000.pwm");
1016 }
1017