1 /*
2  * arch/arm/mach-spear13xx/spear1310_clock.c
3  *
4  * SPEAr1310 machine clock framework source file
5  *
6  * Copyright (C) 2012 ST Microelectronics
7  * Viresh Kumar <viresh.linux@gmail.com>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13 
14 #include <linux/clk.h>
15 #include <linux/clkdev.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/of_platform.h>
19 #include <linux/spinlock_types.h>
20 #include "clk.h"
21 
22 /* PLL related registers and bit values */
23 #define SPEAR1310_PLL_CFG			(misc_base + 0x210)
24 	/* PLL_CFG bit values */
25 	#define SPEAR1310_CLCD_SYNT_CLK_MASK		1
26 	#define SPEAR1310_CLCD_SYNT_CLK_SHIFT		31
27 	#define SPEAR1310_RAS_SYNT2_3_CLK_MASK		2
28 	#define SPEAR1310_RAS_SYNT2_3_CLK_SHIFT		29
29 	#define SPEAR1310_RAS_SYNT_CLK_MASK		2
30 	#define SPEAR1310_RAS_SYNT0_1_CLK_SHIFT		27
31 	#define SPEAR1310_PLL_CLK_MASK			2
32 	#define SPEAR1310_PLL3_CLK_SHIFT		24
33 	#define SPEAR1310_PLL2_CLK_SHIFT		22
34 	#define SPEAR1310_PLL1_CLK_SHIFT		20
35 
36 #define SPEAR1310_PLL1_CTR			(misc_base + 0x214)
37 #define SPEAR1310_PLL1_FRQ			(misc_base + 0x218)
38 #define SPEAR1310_PLL2_CTR			(misc_base + 0x220)
39 #define SPEAR1310_PLL2_FRQ			(misc_base + 0x224)
40 #define SPEAR1310_PLL3_CTR			(misc_base + 0x22C)
41 #define SPEAR1310_PLL3_FRQ			(misc_base + 0x230)
42 #define SPEAR1310_PLL4_CTR			(misc_base + 0x238)
43 #define SPEAR1310_PLL4_FRQ			(misc_base + 0x23C)
44 #define SPEAR1310_PERIP_CLK_CFG			(misc_base + 0x244)
45 	/* PERIP_CLK_CFG bit values */
46 	#define SPEAR1310_GPT_OSC24_VAL			0
47 	#define SPEAR1310_GPT_APB_VAL			1
48 	#define SPEAR1310_GPT_CLK_MASK			1
49 	#define SPEAR1310_GPT3_CLK_SHIFT		11
50 	#define SPEAR1310_GPT2_CLK_SHIFT		10
51 	#define SPEAR1310_GPT1_CLK_SHIFT		9
52 	#define SPEAR1310_GPT0_CLK_SHIFT		8
53 	#define SPEAR1310_UART_CLK_PLL5_VAL		0
54 	#define SPEAR1310_UART_CLK_OSC24_VAL		1
55 	#define SPEAR1310_UART_CLK_SYNT_VAL		2
56 	#define SPEAR1310_UART_CLK_MASK			2
57 	#define SPEAR1310_UART_CLK_SHIFT		4
58 
59 	#define SPEAR1310_AUX_CLK_PLL5_VAL		0
60 	#define SPEAR1310_AUX_CLK_SYNT_VAL		1
61 	#define SPEAR1310_CLCD_CLK_MASK			2
62 	#define SPEAR1310_CLCD_CLK_SHIFT		2
63 	#define SPEAR1310_C3_CLK_MASK			1
64 	#define SPEAR1310_C3_CLK_SHIFT			1
65 
66 #define SPEAR1310_GMAC_CLK_CFG			(misc_base + 0x248)
67 	#define SPEAR1310_GMAC_PHY_IF_SEL_MASK		3
68 	#define SPEAR1310_GMAC_PHY_IF_SEL_SHIFT		4
69 	#define SPEAR1310_GMAC_PHY_CLK_MASK		1
70 	#define SPEAR1310_GMAC_PHY_CLK_SHIFT		3
71 	#define SPEAR1310_GMAC_PHY_INPUT_CLK_MASK	2
72 	#define SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT	1
73 
74 #define SPEAR1310_I2S_CLK_CFG			(misc_base + 0x24C)
75 	/* I2S_CLK_CFG register mask */
76 	#define SPEAR1310_I2S_SCLK_X_MASK		0x1F
77 	#define SPEAR1310_I2S_SCLK_X_SHIFT		27
78 	#define SPEAR1310_I2S_SCLK_Y_MASK		0x1F
79 	#define SPEAR1310_I2S_SCLK_Y_SHIFT		22
80 	#define SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT		21
81 	#define SPEAR1310_I2S_SCLK_SYNTH_ENB		20
82 	#define SPEAR1310_I2S_PRS1_CLK_X_MASK		0xFF
83 	#define SPEAR1310_I2S_PRS1_CLK_X_SHIFT		12
84 	#define SPEAR1310_I2S_PRS1_CLK_Y_MASK		0xFF
85 	#define SPEAR1310_I2S_PRS1_CLK_Y_SHIFT		4
86 	#define SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT		3
87 	#define SPEAR1310_I2S_REF_SEL_MASK		1
88 	#define SPEAR1310_I2S_REF_SHIFT			2
89 	#define SPEAR1310_I2S_SRC_CLK_MASK		2
90 	#define SPEAR1310_I2S_SRC_CLK_SHIFT		0
91 
92 #define SPEAR1310_C3_CLK_SYNT			(misc_base + 0x250)
93 #define SPEAR1310_UART_CLK_SYNT			(misc_base + 0x254)
94 #define SPEAR1310_GMAC_CLK_SYNT			(misc_base + 0x258)
95 #define SPEAR1310_SDHCI_CLK_SYNT		(misc_base + 0x25C)
96 #define SPEAR1310_CFXD_CLK_SYNT			(misc_base + 0x260)
97 #define SPEAR1310_ADC_CLK_SYNT			(misc_base + 0x264)
98 #define SPEAR1310_AMBA_CLK_SYNT			(misc_base + 0x268)
99 #define SPEAR1310_CLCD_CLK_SYNT			(misc_base + 0x270)
100 #define SPEAR1310_RAS_CLK_SYNT0			(misc_base + 0x280)
101 #define SPEAR1310_RAS_CLK_SYNT1			(misc_base + 0x288)
102 #define SPEAR1310_RAS_CLK_SYNT2			(misc_base + 0x290)
103 #define SPEAR1310_RAS_CLK_SYNT3			(misc_base + 0x298)
104 	/* Check Fractional synthesizer reg masks */
105 
106 #define SPEAR1310_PERIP1_CLK_ENB		(misc_base + 0x300)
107 	/* PERIP1_CLK_ENB register masks */
108 	#define SPEAR1310_RTC_CLK_ENB			31
109 	#define SPEAR1310_ADC_CLK_ENB			30
110 	#define SPEAR1310_C3_CLK_ENB			29
111 	#define SPEAR1310_JPEG_CLK_ENB			28
112 	#define SPEAR1310_CLCD_CLK_ENB			27
113 	#define SPEAR1310_DMA_CLK_ENB			25
114 	#define SPEAR1310_GPIO1_CLK_ENB			24
115 	#define SPEAR1310_GPIO0_CLK_ENB			23
116 	#define SPEAR1310_GPT1_CLK_ENB			22
117 	#define SPEAR1310_GPT0_CLK_ENB			21
118 	#define SPEAR1310_I2S0_CLK_ENB			20
119 	#define SPEAR1310_I2S1_CLK_ENB			19
120 	#define SPEAR1310_I2C0_CLK_ENB			18
121 	#define SPEAR1310_SSP_CLK_ENB			17
122 	#define SPEAR1310_UART_CLK_ENB			15
123 	#define SPEAR1310_PCIE_SATA_2_CLK_ENB		14
124 	#define SPEAR1310_PCIE_SATA_1_CLK_ENB		13
125 	#define SPEAR1310_PCIE_SATA_0_CLK_ENB		12
126 	#define SPEAR1310_UOC_CLK_ENB			11
127 	#define SPEAR1310_UHC1_CLK_ENB			10
128 	#define SPEAR1310_UHC0_CLK_ENB			9
129 	#define SPEAR1310_GMAC_CLK_ENB			8
130 	#define SPEAR1310_CFXD_CLK_ENB			7
131 	#define SPEAR1310_SDHCI_CLK_ENB			6
132 	#define SPEAR1310_SMI_CLK_ENB			5
133 	#define SPEAR1310_FSMC_CLK_ENB			4
134 	#define SPEAR1310_SYSRAM0_CLK_ENB		3
135 	#define SPEAR1310_SYSRAM1_CLK_ENB		2
136 	#define SPEAR1310_SYSROM_CLK_ENB		1
137 	#define SPEAR1310_BUS_CLK_ENB			0
138 
139 #define SPEAR1310_PERIP2_CLK_ENB		(misc_base + 0x304)
140 	/* PERIP2_CLK_ENB register masks */
141 	#define SPEAR1310_THSENS_CLK_ENB		8
142 	#define SPEAR1310_I2S_REF_PAD_CLK_ENB		7
143 	#define SPEAR1310_ACP_CLK_ENB			6
144 	#define SPEAR1310_GPT3_CLK_ENB			5
145 	#define SPEAR1310_GPT2_CLK_ENB			4
146 	#define SPEAR1310_KBD_CLK_ENB			3
147 	#define SPEAR1310_CPU_DBG_CLK_ENB		2
148 	#define SPEAR1310_DDR_CORE_CLK_ENB		1
149 	#define SPEAR1310_DDR_CTRL_CLK_ENB		0
150 
151 #define SPEAR1310_RAS_CLK_ENB			(misc_base + 0x310)
152 	/* RAS_CLK_ENB register masks */
153 	#define SPEAR1310_SYNT3_CLK_ENB			17
154 	#define SPEAR1310_SYNT2_CLK_ENB			16
155 	#define SPEAR1310_SYNT1_CLK_ENB			15
156 	#define SPEAR1310_SYNT0_CLK_ENB			14
157 	#define SPEAR1310_PCLK3_CLK_ENB			13
158 	#define SPEAR1310_PCLK2_CLK_ENB			12
159 	#define SPEAR1310_PCLK1_CLK_ENB			11
160 	#define SPEAR1310_PCLK0_CLK_ENB			10
161 	#define SPEAR1310_PLL3_CLK_ENB			9
162 	#define SPEAR1310_PLL2_CLK_ENB			8
163 	#define SPEAR1310_C125M_PAD_CLK_ENB		7
164 	#define SPEAR1310_C30M_CLK_ENB			6
165 	#define SPEAR1310_C48M_CLK_ENB			5
166 	#define SPEAR1310_OSC_25M_CLK_ENB		4
167 	#define SPEAR1310_OSC_32K_CLK_ENB		3
168 	#define SPEAR1310_OSC_24M_CLK_ENB		2
169 	#define SPEAR1310_PCLK_CLK_ENB			1
170 	#define SPEAR1310_ACLK_CLK_ENB			0
171 
172 /* RAS Area Control Register */
173 #define SPEAR1310_RAS_CTRL_REG0			(ras_base + 0x000)
174 	#define SPEAR1310_SSP1_CLK_MASK			3
175 	#define SPEAR1310_SSP1_CLK_SHIFT		26
176 	#define SPEAR1310_TDM_CLK_MASK			1
177 	#define SPEAR1310_TDM2_CLK_SHIFT		24
178 	#define SPEAR1310_TDM1_CLK_SHIFT		23
179 	#define SPEAR1310_I2C_CLK_MASK			1
180 	#define SPEAR1310_I2C7_CLK_SHIFT		22
181 	#define SPEAR1310_I2C6_CLK_SHIFT		21
182 	#define SPEAR1310_I2C5_CLK_SHIFT		20
183 	#define SPEAR1310_I2C4_CLK_SHIFT		19
184 	#define SPEAR1310_I2C3_CLK_SHIFT		18
185 	#define SPEAR1310_I2C2_CLK_SHIFT		17
186 	#define SPEAR1310_I2C1_CLK_SHIFT		16
187 	#define SPEAR1310_GPT64_CLK_MASK		1
188 	#define SPEAR1310_GPT64_CLK_SHIFT		15
189 	#define SPEAR1310_RAS_UART_CLK_MASK		1
190 	#define SPEAR1310_UART5_CLK_SHIFT		14
191 	#define SPEAR1310_UART4_CLK_SHIFT		13
192 	#define SPEAR1310_UART3_CLK_SHIFT		12
193 	#define SPEAR1310_UART2_CLK_SHIFT		11
194 	#define SPEAR1310_UART1_CLK_SHIFT		10
195 	#define SPEAR1310_PCI_CLK_MASK			1
196 	#define SPEAR1310_PCI_CLK_SHIFT			0
197 
198 #define SPEAR1310_RAS_CTRL_REG1			(ras_base + 0x004)
199 	#define SPEAR1310_PHY_CLK_MASK			0x3
200 	#define SPEAR1310_RMII_PHY_CLK_SHIFT		0
201 	#define SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT	2
202 
203 #define SPEAR1310_RAS_SW_CLK_CTRL		(ras_base + 0x0148)
204 	#define SPEAR1310_CAN1_CLK_ENB			25
205 	#define SPEAR1310_CAN0_CLK_ENB			24
206 	#define SPEAR1310_GPT64_CLK_ENB			23
207 	#define SPEAR1310_SSP1_CLK_ENB			22
208 	#define SPEAR1310_I2C7_CLK_ENB			21
209 	#define SPEAR1310_I2C6_CLK_ENB			20
210 	#define SPEAR1310_I2C5_CLK_ENB			19
211 	#define SPEAR1310_I2C4_CLK_ENB			18
212 	#define SPEAR1310_I2C3_CLK_ENB			17
213 	#define SPEAR1310_I2C2_CLK_ENB			16
214 	#define SPEAR1310_I2C1_CLK_ENB			15
215 	#define SPEAR1310_UART5_CLK_ENB			14
216 	#define SPEAR1310_UART4_CLK_ENB			13
217 	#define SPEAR1310_UART3_CLK_ENB			12
218 	#define SPEAR1310_UART2_CLK_ENB			11
219 	#define SPEAR1310_UART1_CLK_ENB			10
220 	#define SPEAR1310_RS485_1_CLK_ENB		9
221 	#define SPEAR1310_RS485_0_CLK_ENB		8
222 	#define SPEAR1310_TDM2_CLK_ENB			7
223 	#define SPEAR1310_TDM1_CLK_ENB			6
224 	#define SPEAR1310_PCI_CLK_ENB			5
225 	#define SPEAR1310_GMII_CLK_ENB			4
226 	#define SPEAR1310_MII2_CLK_ENB			3
227 	#define SPEAR1310_MII1_CLK_ENB			2
228 	#define SPEAR1310_MII0_CLK_ENB			1
229 	#define SPEAR1310_ESRAM_CLK_ENB			0
230 
231 static DEFINE_SPINLOCK(_lock);
232 
233 /* pll rate configuration table, in ascending order of rates */
234 static struct pll_rate_tbl pll_rtbl[] = {
235 	/* PCLK 24MHz */
236 	{.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
237 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
238 	{.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
239 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
240 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
241 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
242 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
243 };
244 
245 /* vco-pll4 rate configuration table, in ascending order of rates */
246 static struct pll_rate_tbl pll4_rtbl[] = {
247 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
248 	{.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
249 	{.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x2}, /* vco 1600, pll 400 MHz */
250 	{.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x0}, /* vco 1, pll 1 GHz */
251 };
252 
253 /* aux rate configuration table, in ascending order of rates */
254 static struct aux_rate_tbl aux_rtbl[] = {
255 	/* For VCO1div2 = 500 MHz */
256 	{.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */
257 	{.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */
258 	{.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */
259 	{.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */
260 	{.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */
261 	{.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */
262 };
263 
264 /* gmac rate configuration table, in ascending order of rates */
265 static struct aux_rate_tbl gmac_rtbl[] = {
266 	/* For gmac phy input clk */
267 	{.xscale = 2, .yscale = 6, .eq = 0}, /* divided by 6 */
268 	{.xscale = 2, .yscale = 4, .eq = 0}, /* divided by 4 */
269 	{.xscale = 1, .yscale = 3, .eq = 1}, /* divided by 3 */
270 	{.xscale = 1, .yscale = 2, .eq = 1}, /* divided by 2 */
271 };
272 
273 /* clcd rate configuration table, in ascending order of rates */
274 static struct frac_rate_tbl clcd_rtbl[] = {
275 	{.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
276 	{.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
277 	{.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
278 	{.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
279 	{.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
280 	{.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
281 	{.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
282 	{.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
283 	{.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
284 	{.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
285 };
286 
287 /* i2s prescaler1 masks */
288 static struct aux_clk_masks i2s_prs1_masks = {
289 	.eq_sel_mask = AUX_EQ_SEL_MASK,
290 	.eq_sel_shift = SPEAR1310_I2S_PRS1_EQ_SEL_SHIFT,
291 	.eq1_mask = AUX_EQ1_SEL,
292 	.eq2_mask = AUX_EQ2_SEL,
293 	.xscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_X_MASK,
294 	.xscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_X_SHIFT,
295 	.yscale_sel_mask = SPEAR1310_I2S_PRS1_CLK_Y_MASK,
296 	.yscale_sel_shift = SPEAR1310_I2S_PRS1_CLK_Y_SHIFT,
297 };
298 
299 /* i2s sclk (bit clock) syynthesizers masks */
300 static struct aux_clk_masks i2s_sclk_masks = {
301 	.eq_sel_mask = AUX_EQ_SEL_MASK,
302 	.eq_sel_shift = SPEAR1310_I2S_SCLK_EQ_SEL_SHIFT,
303 	.eq1_mask = AUX_EQ1_SEL,
304 	.eq2_mask = AUX_EQ2_SEL,
305 	.xscale_sel_mask = SPEAR1310_I2S_SCLK_X_MASK,
306 	.xscale_sel_shift = SPEAR1310_I2S_SCLK_X_SHIFT,
307 	.yscale_sel_mask = SPEAR1310_I2S_SCLK_Y_MASK,
308 	.yscale_sel_shift = SPEAR1310_I2S_SCLK_Y_SHIFT,
309 	.enable_bit = SPEAR1310_I2S_SCLK_SYNTH_ENB,
310 };
311 
312 /* i2s prs1 aux rate configuration table, in ascending order of rates */
313 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
314 	/* For parent clk = 49.152 MHz */
315 	{.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
316 	{.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
317 	{.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
318 	{.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
319 
320 	/*
321 	 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
322 	 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
323 	 */
324 	{.xscale = 1, .yscale = 3, .eq = 0},
325 
326 	/* For parent clk = 49.152 MHz */
327 	{.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
328 
329 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
330 };
331 
332 /* i2s sclk aux rate configuration table, in ascending order of rates */
333 static struct aux_rate_tbl i2s_sclk_rtbl[] = {
334 	/* For i2s_ref_clk = 12.288MHz */
335 	{.xscale = 1, .yscale = 4, .eq = 0}, /* 1.53 MHz */
336 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 3.07 Mhz */
337 };
338 
339 /* adc rate configuration table, in ascending order of rates */
340 /* possible adc range is 2.5 MHz to 20 MHz. */
341 static struct aux_rate_tbl adc_rtbl[] = {
342 	/* For ahb = 166.67 MHz */
343 	{.xscale = 1, .yscale = 31, .eq = 0}, /* 2.68 MHz */
344 	{.xscale = 2, .yscale = 21, .eq = 0}, /* 7.94 MHz */
345 	{.xscale = 4, .yscale = 21, .eq = 0}, /* 15.87 MHz */
346 	{.xscale = 10, .yscale = 42, .eq = 0}, /* 19.84 MHz */
347 };
348 
349 /* General synth rate configuration table, in ascending order of rates */
350 static struct frac_rate_tbl gen_rtbl[] = {
351 	/* For vco1div4 = 250 MHz */
352 	{.div = 0x14000}, /* 25 MHz */
353 	{.div = 0x0A000}, /* 50 MHz */
354 	{.div = 0x05000}, /* 100 MHz */
355 	{.div = 0x02000}, /* 250 MHz */
356 };
357 
358 /* clock parents */
359 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
360 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
361 static const char *uart0_parents[] = { "pll5_clk", "uart_syn_gclk", };
362 static const char *c3_parents[] = { "pll5_clk", "c3_syn_gclk", };
363 static const char *gmac_phy_input_parents[] = { "gmii_pad_clk", "pll2_clk",
364 	"osc_25m_clk", };
365 static const char *gmac_phy_parents[] = { "phy_input_mclk", "phy_syn_gclk", };
366 static const char *clcd_synth_parents[] = { "vco1div4_clk", "pll2_clk", };
367 static const char *clcd_pixel_parents[] = { "pll5_clk", "clcd_syn_clk", };
368 static const char *i2s_src_parents[] = { "vco1div2_clk", "none", "pll3_clk",
369 	"i2s_src_pad_clk", };
370 static const char *i2s_ref_parents[] = { "i2s_src_mclk", "i2s_prs1_clk", };
371 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
372 	"pll3_clk", };
373 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
374 	"pll2_clk", };
375 static const char *rmii_phy_parents[] = { "ras_tx50_clk", "none",
376 	"ras_pll2_clk", "ras_syn0_clk", };
377 static const char *smii_rgmii_phy_parents[] = { "none", "ras_tx125_clk",
378 	"ras_pll2_clk", "ras_syn0_clk", };
379 static const char *uart_parents[] = { "ras_apb_clk", "gen_syn3_clk", };
380 static const char *i2c_parents[] = { "ras_apb_clk", "gen_syn1_clk", };
381 static const char *ssp1_parents[] = { "ras_apb_clk", "gen_syn1_clk",
382 	"ras_plclk0_clk", };
383 static const char *pci_parents[] = { "ras_pll3_clk", "gen_syn2_clk", };
384 static const char *tdm_parents[] = { "ras_pll3_clk", "gen_syn1_clk", };
385 
386 void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
387 {
388 	struct clk *clk, *clk1;
389 
390 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
391 			32000);
392 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
393 
394 	clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT,
395 			24000000);
396 	clk_register_clkdev(clk, "osc_24m_clk", NULL);
397 
398 	clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT,
399 			25000000);
400 	clk_register_clkdev(clk, "osc_25m_clk", NULL);
401 
402 	clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT,
403 			125000000);
404 	clk_register_clkdev(clk, "gmii_pad_clk", NULL);
405 
406 	clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL,
407 			CLK_IS_ROOT, 12288000);
408 	clk_register_clkdev(clk, "i2s_src_pad_clk", NULL);
409 
410 	/* clock derived from 32 KHz osc clk */
411 	clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
412 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
413 			&_lock);
414 	clk_register_clkdev(clk, NULL, "e0580000.rtc");
415 
416 	/* clock derived from 24 or 25 MHz osc clk */
417 	/* vco-pll */
418 	clk = clk_register_mux(NULL, "vco1_mclk", vco_parents,
419 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
420 			SPEAR1310_PLL_CFG, SPEAR1310_PLL1_CLK_SHIFT,
421 			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
422 	clk_register_clkdev(clk, "vco1_mclk", NULL);
423 	clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk",
424 			0, SPEAR1310_PLL1_CTR, SPEAR1310_PLL1_FRQ, pll_rtbl,
425 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
426 	clk_register_clkdev(clk, "vco1_clk", NULL);
427 	clk_register_clkdev(clk1, "pll1_clk", NULL);
428 
429 	clk = clk_register_mux(NULL, "vco2_mclk", vco_parents,
430 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
431 			SPEAR1310_PLL_CFG, SPEAR1310_PLL2_CLK_SHIFT,
432 			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
433 	clk_register_clkdev(clk, "vco2_mclk", NULL);
434 	clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk",
435 			0, SPEAR1310_PLL2_CTR, SPEAR1310_PLL2_FRQ, pll_rtbl,
436 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
437 	clk_register_clkdev(clk, "vco2_clk", NULL);
438 	clk_register_clkdev(clk1, "pll2_clk", NULL);
439 
440 	clk = clk_register_mux(NULL, "vco3_mclk", vco_parents,
441 			ARRAY_SIZE(vco_parents), CLK_SET_RATE_NO_REPARENT,
442 			SPEAR1310_PLL_CFG, SPEAR1310_PLL3_CLK_SHIFT,
443 			SPEAR1310_PLL_CLK_MASK, 0, &_lock);
444 	clk_register_clkdev(clk, "vco3_mclk", NULL);
445 	clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk",
446 			0, SPEAR1310_PLL3_CTR, SPEAR1310_PLL3_FRQ, pll_rtbl,
447 			ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL);
448 	clk_register_clkdev(clk, "vco3_clk", NULL);
449 	clk_register_clkdev(clk1, "pll3_clk", NULL);
450 
451 	clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk",
452 			0, SPEAR1310_PLL4_CTR, SPEAR1310_PLL4_FRQ, pll4_rtbl,
453 			ARRAY_SIZE(pll4_rtbl), &_lock, &clk1, NULL);
454 	clk_register_clkdev(clk, "vco4_clk", NULL);
455 	clk_register_clkdev(clk1, "pll4_clk", NULL);
456 
457 	clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0,
458 			48000000);
459 	clk_register_clkdev(clk, "pll5_clk", NULL);
460 
461 	clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0,
462 			25000000);
463 	clk_register_clkdev(clk, "pll6_clk", NULL);
464 
465 	/* vco div n clocks */
466 	clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1,
467 			2);
468 	clk_register_clkdev(clk, "vco1div2_clk", NULL);
469 
470 	clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1,
471 			4);
472 	clk_register_clkdev(clk, "vco1div4_clk", NULL);
473 
474 	clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1,
475 			2);
476 	clk_register_clkdev(clk, "vco2div2_clk", NULL);
477 
478 	clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1,
479 			2);
480 	clk_register_clkdev(clk, "vco3div2_clk", NULL);
481 
482 	/* peripherals */
483 	clk_register_fixed_factor(NULL, "thermal_clk", "osc_24m_clk", 0, 1,
484 			128);
485 	clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
486 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_THSENS_CLK_ENB, 0,
487 			&_lock);
488 	clk_register_clkdev(clk, NULL, "spear_thermal");
489 
490 	/* clock derived from pll4 clk */
491 	clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
492 			1);
493 	clk_register_clkdev(clk, "ddr_clk", NULL);
494 
495 	/* clock derived from pll1 clk */
496 	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
497 			CLK_SET_RATE_PARENT, 1, 2);
498 	clk_register_clkdev(clk, "cpu_clk", NULL);
499 
500 	clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
501 			2);
502 	clk_register_clkdev(clk, NULL, "ec800620.wdt");
503 
504 	clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
505 			2);
506 	clk_register_clkdev(clk, NULL, "smp_twd");
507 
508 	clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
509 			6);
510 	clk_register_clkdev(clk, "ahb_clk", NULL);
511 
512 	clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1,
513 			12);
514 	clk_register_clkdev(clk, "apb_clk", NULL);
515 
516 	/* gpt clocks */
517 	clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents,
518 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
519 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT0_CLK_SHIFT,
520 			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
521 	clk_register_clkdev(clk, "gpt0_mclk", NULL);
522 	clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0,
523 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT0_CLK_ENB, 0,
524 			&_lock);
525 	clk_register_clkdev(clk, NULL, "gpt0");
526 
527 	clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents,
528 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
529 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT1_CLK_SHIFT,
530 			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
531 	clk_register_clkdev(clk, "gpt1_mclk", NULL);
532 	clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
533 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPT1_CLK_ENB, 0,
534 			&_lock);
535 	clk_register_clkdev(clk, NULL, "gpt1");
536 
537 	clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents,
538 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
539 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT2_CLK_SHIFT,
540 			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
541 	clk_register_clkdev(clk, "gpt2_mclk", NULL);
542 	clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
543 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT2_CLK_ENB, 0,
544 			&_lock);
545 	clk_register_clkdev(clk, NULL, "gpt2");
546 
547 	clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents,
548 			ARRAY_SIZE(gpt_parents), CLK_SET_RATE_NO_REPARENT,
549 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GPT3_CLK_SHIFT,
550 			SPEAR1310_GPT_CLK_MASK, 0, &_lock);
551 	clk_register_clkdev(clk, "gpt3_mclk", NULL);
552 	clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
553 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_GPT3_CLK_ENB, 0,
554 			&_lock);
555 	clk_register_clkdev(clk, NULL, "gpt3");
556 
557 	/* others */
558 	clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk",
559 			0, SPEAR1310_UART_CLK_SYNT, NULL, aux_rtbl,
560 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
561 	clk_register_clkdev(clk, "uart_syn_clk", NULL);
562 	clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
563 
564 	clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
565 			ARRAY_SIZE(uart0_parents),
566 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
567 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
568 			SPEAR1310_UART_CLK_MASK, 0, &_lock);
569 	clk_register_clkdev(clk, "uart0_mclk", NULL);
570 
571 	clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
572 			CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
573 			SPEAR1310_UART_CLK_ENB, 0, &_lock);
574 	clk_register_clkdev(clk, NULL, "e0000000.serial");
575 
576 	clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
577 			"vco1div2_clk", 0, SPEAR1310_SDHCI_CLK_SYNT, NULL,
578 			aux_rtbl, ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
579 	clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
580 	clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
581 
582 	clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
583 			CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
584 			SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
585 	clk_register_clkdev(clk, NULL, "b3000000.sdhci");
586 
587 	clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
588 			0, SPEAR1310_CFXD_CLK_SYNT, NULL, aux_rtbl,
589 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
590 	clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
591 	clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
592 
593 	clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
594 			CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
595 			SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
596 	clk_register_clkdev(clk, NULL, "b2800000.cf");
597 	clk_register_clkdev(clk, NULL, "arasan_xd");
598 
599 	clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk",
600 			0, SPEAR1310_C3_CLK_SYNT, NULL, aux_rtbl,
601 			ARRAY_SIZE(aux_rtbl), &_lock, &clk1);
602 	clk_register_clkdev(clk, "c3_syn_clk", NULL);
603 	clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
604 
605 	clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
606 			ARRAY_SIZE(c3_parents),
607 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
608 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
609 			SPEAR1310_C3_CLK_MASK, 0, &_lock);
610 	clk_register_clkdev(clk, "c3_mclk", NULL);
611 
612 	clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
613 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_C3_CLK_ENB, 0,
614 			&_lock);
615 	clk_register_clkdev(clk, NULL, "c3");
616 
617 	/* gmac */
618 	clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
619 			ARRAY_SIZE(gmac_phy_input_parents),
620 			CLK_SET_RATE_NO_REPARENT, SPEAR1310_GMAC_CLK_CFG,
621 			SPEAR1310_GMAC_PHY_INPUT_CLK_SHIFT,
622 			SPEAR1310_GMAC_PHY_INPUT_CLK_MASK, 0, &_lock);
623 	clk_register_clkdev(clk, "phy_input_mclk", NULL);
624 
625 	clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk",
626 			0, SPEAR1310_GMAC_CLK_SYNT, NULL, gmac_rtbl,
627 			ARRAY_SIZE(gmac_rtbl), &_lock, &clk1);
628 	clk_register_clkdev(clk, "phy_syn_clk", NULL);
629 	clk_register_clkdev(clk1, "phy_syn_gclk", NULL);
630 
631 	clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents,
632 			ARRAY_SIZE(gmac_phy_parents), CLK_SET_RATE_NO_REPARENT,
633 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
634 			SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
635 	clk_register_clkdev(clk, "stmmacphy.0", NULL);
636 
637 	/* clcd */
638 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
639 			ARRAY_SIZE(clcd_synth_parents),
640 			CLK_SET_RATE_NO_REPARENT, SPEAR1310_CLCD_CLK_SYNT,
641 			SPEAR1310_CLCD_SYNT_CLK_SHIFT,
642 			SPEAR1310_CLCD_SYNT_CLK_MASK, 0, &_lock);
643 	clk_register_clkdev(clk, "clcd_syn_mclk", NULL);
644 
645 	clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0,
646 			SPEAR1310_CLCD_CLK_SYNT, clcd_rtbl,
647 			ARRAY_SIZE(clcd_rtbl), &_lock);
648 	clk_register_clkdev(clk, "clcd_syn_clk", NULL);
649 
650 	clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
651 			ARRAY_SIZE(clcd_pixel_parents),
652 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
653 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
654 			SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
655 	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
656 
657 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
658 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
659 			&_lock);
660 	clk_register_clkdev(clk, NULL, "e1000000.clcd");
661 
662 	/* i2s */
663 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
664 			ARRAY_SIZE(i2s_src_parents), CLK_SET_RATE_NO_REPARENT,
665 			SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_SRC_CLK_SHIFT,
666 			SPEAR1310_I2S_SRC_CLK_MASK, 0, &_lock);
667 	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
668 
669 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
670 			SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
671 			ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
672 	clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
673 
674 	clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
675 			ARRAY_SIZE(i2s_ref_parents),
676 			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
677 			SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
678 			SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
679 	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
680 
681 	clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
682 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
683 			0, &_lock);
684 	clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
685 
686 	clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
687 			"i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
688 			&i2s_sclk_masks, i2s_sclk_rtbl,
689 			ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
690 	clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
691 	clk_register_clkdev(clk1, "i2s_sclk_gclk", NULL);
692 
693 	/* clock derived from ahb clk */
694 	clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0,
695 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2C0_CLK_ENB, 0,
696 			&_lock);
697 	clk_register_clkdev(clk, NULL, "e0280000.i2c");
698 
699 	clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0,
700 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_DMA_CLK_ENB, 0,
701 			&_lock);
702 	clk_register_clkdev(clk, NULL, "ea800000.dma");
703 	clk_register_clkdev(clk, NULL, "eb000000.dma");
704 
705 	clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0,
706 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_JPEG_CLK_ENB, 0,
707 			&_lock);
708 	clk_register_clkdev(clk, NULL, "b2000000.jpeg");
709 
710 	clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0,
711 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GMAC_CLK_ENB, 0,
712 			&_lock);
713 	clk_register_clkdev(clk, NULL, "e2000000.eth");
714 
715 	clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0,
716 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_FSMC_CLK_ENB, 0,
717 			&_lock);
718 	clk_register_clkdev(clk, NULL, "b0000000.flash");
719 
720 	clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0,
721 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SMI_CLK_ENB, 0,
722 			&_lock);
723 	clk_register_clkdev(clk, NULL, "ea000000.flash");
724 
725 	clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
726 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
727 			&_lock);
728 	clk_register_clkdev(clk, NULL, "e4000000.ohci");
729 	clk_register_clkdev(clk, NULL, "e4800000.ehci");
730 
731 	clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
732 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
733 			&_lock);
734 	clk_register_clkdev(clk, NULL, "e5000000.ohci");
735 	clk_register_clkdev(clk, NULL, "e5800000.ehci");
736 
737 	clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
738 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
739 			&_lock);
740 	clk_register_clkdev(clk, NULL, "e3800000.otg");
741 
742 	clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
743 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
744 			0, &_lock);
745 	clk_register_clkdev(clk, NULL, "b1000000.pcie");
746 	clk_register_clkdev(clk, NULL, "b1000000.ahci");
747 
748 	clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
749 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
750 			0, &_lock);
751 	clk_register_clkdev(clk, NULL, "b1800000.pcie");
752 	clk_register_clkdev(clk, NULL, "b1800000.ahci");
753 
754 	clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
755 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
756 			0, &_lock);
757 	clk_register_clkdev(clk, NULL, "b4000000.pcie");
758 	clk_register_clkdev(clk, NULL, "b4000000.ahci");
759 
760 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
761 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
762 			&_lock);
763 	clk_register_clkdev(clk, "sysram0_clk", NULL);
764 
765 	clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0,
766 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM1_CLK_ENB, 0,
767 			&_lock);
768 	clk_register_clkdev(clk, "sysram1_clk", NULL);
769 
770 	clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk",
771 			0, SPEAR1310_ADC_CLK_SYNT, NULL, adc_rtbl,
772 			ARRAY_SIZE(adc_rtbl), &_lock, &clk1);
773 	clk_register_clkdev(clk, "adc_syn_clk", NULL);
774 	clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
775 
776 	clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
777 			CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
778 			SPEAR1310_ADC_CLK_ENB, 0, &_lock);
779 	clk_register_clkdev(clk, NULL, "e0080000.adc");
780 
781 	/* clock derived from apb clk */
782 	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
783 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SSP_CLK_ENB, 0,
784 			&_lock);
785 	clk_register_clkdev(clk, NULL, "e0100000.spi");
786 
787 	clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0,
788 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO0_CLK_ENB, 0,
789 			&_lock);
790 	clk_register_clkdev(clk, NULL, "e0600000.gpio");
791 
792 	clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0,
793 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_GPIO1_CLK_ENB, 0,
794 			&_lock);
795 	clk_register_clkdev(clk, NULL, "e0680000.gpio");
796 
797 	clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0,
798 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S0_CLK_ENB, 0,
799 			&_lock);
800 	clk_register_clkdev(clk, NULL, "e0180000.i2s");
801 
802 	clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0,
803 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_I2S1_CLK_ENB, 0,
804 			&_lock);
805 	clk_register_clkdev(clk, NULL, "e0200000.i2s");
806 
807 	clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
808 			SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_KBD_CLK_ENB, 0,
809 			&_lock);
810 	clk_register_clkdev(clk, NULL, "e0300000.kbd");
811 
812 	/* RAS clks */
813 	clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents,
814 			ARRAY_SIZE(gen_synth0_1_parents),
815 			CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
816 			SPEAR1310_RAS_SYNT0_1_CLK_SHIFT,
817 			SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
818 	clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
819 
820 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
821 			ARRAY_SIZE(gen_synth2_3_parents),
822 			CLK_SET_RATE_NO_REPARENT, SPEAR1310_PLL_CFG,
823 			SPEAR1310_RAS_SYNT2_3_CLK_SHIFT,
824 			SPEAR1310_RAS_SYNT_CLK_MASK, 0, &_lock);
825 	clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
826 
827 	clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
828 			SPEAR1310_RAS_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
829 			&_lock);
830 	clk_register_clkdev(clk, "gen_syn0_clk", NULL);
831 
832 	clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
833 			SPEAR1310_RAS_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
834 			&_lock);
835 	clk_register_clkdev(clk, "gen_syn1_clk", NULL);
836 
837 	clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
838 			SPEAR1310_RAS_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
839 			&_lock);
840 	clk_register_clkdev(clk, "gen_syn2_clk", NULL);
841 
842 	clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
843 			SPEAR1310_RAS_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
844 			&_lock);
845 	clk_register_clkdev(clk, "gen_syn3_clk", NULL);
846 
847 	clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0,
848 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_24M_CLK_ENB, 0,
849 			&_lock);
850 	clk_register_clkdev(clk, "ras_osc_24m_clk", NULL);
851 
852 	clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0,
853 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_25M_CLK_ENB, 0,
854 			&_lock);
855 	clk_register_clkdev(clk, "ras_osc_25m_clk", NULL);
856 
857 	clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0,
858 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_OSC_32K_CLK_ENB, 0,
859 			&_lock);
860 	clk_register_clkdev(clk, "ras_osc_32k_clk", NULL);
861 
862 	clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0,
863 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL2_CLK_ENB, 0,
864 			&_lock);
865 	clk_register_clkdev(clk, "ras_pll2_clk", NULL);
866 
867 	clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0,
868 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_PLL3_CLK_ENB, 0,
869 			&_lock);
870 	clk_register_clkdev(clk, "ras_pll3_clk", NULL);
871 
872 	clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0,
873 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_C125M_PAD_CLK_ENB, 0,
874 			&_lock);
875 	clk_register_clkdev(clk, "ras_tx125_clk", NULL);
876 
877 	clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0,
878 			30000000);
879 	clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0,
880 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_C30M_CLK_ENB, 0,
881 			&_lock);
882 	clk_register_clkdev(clk, "ras_30m_clk", NULL);
883 
884 	clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0,
885 			48000000);
886 	clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0,
887 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_C48M_CLK_ENB, 0,
888 			&_lock);
889 	clk_register_clkdev(clk, "ras_48m_clk", NULL);
890 
891 	clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0,
892 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_ACLK_CLK_ENB, 0,
893 			&_lock);
894 	clk_register_clkdev(clk, "ras_ahb_clk", NULL);
895 
896 	clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0,
897 			SPEAR1310_RAS_CLK_ENB, SPEAR1310_PCLK_CLK_ENB, 0,
898 			&_lock);
899 	clk_register_clkdev(clk, "ras_apb_clk", NULL);
900 
901 	clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT,
902 			50000000);
903 
904 	clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT,
905 			50000000);
906 
907 	clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0,
908 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN0_CLK_ENB, 0,
909 			&_lock);
910 	clk_register_clkdev(clk, NULL, "c_can_platform.0");
911 
912 	clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0,
913 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_CAN1_CLK_ENB, 0,
914 			&_lock);
915 	clk_register_clkdev(clk, NULL, "c_can_platform.1");
916 
917 	clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0,
918 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII0_CLK_ENB, 0,
919 			&_lock);
920 	clk_register_clkdev(clk, NULL, "5c400000.eth");
921 
922 	clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0,
923 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII1_CLK_ENB, 0,
924 			&_lock);
925 	clk_register_clkdev(clk, NULL, "5c500000.eth");
926 
927 	clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0,
928 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_MII2_CLK_ENB, 0,
929 			&_lock);
930 	clk_register_clkdev(clk, NULL, "5c600000.eth");
931 
932 	clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0,
933 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_GMII_CLK_ENB, 0,
934 			&_lock);
935 	clk_register_clkdev(clk, NULL, "5c700000.eth");
936 
937 	clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk",
938 			smii_rgmii_phy_parents,
939 			ARRAY_SIZE(smii_rgmii_phy_parents),
940 			CLK_SET_RATE_NO_REPARENT, SPEAR1310_RAS_CTRL_REG1,
941 			SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
942 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
943 	clk_register_clkdev(clk, "stmmacphy.1", NULL);
944 	clk_register_clkdev(clk, "stmmacphy.2", NULL);
945 	clk_register_clkdev(clk, "stmmacphy.4", NULL);
946 
947 	clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
948 			ARRAY_SIZE(rmii_phy_parents), CLK_SET_RATE_NO_REPARENT,
949 			SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
950 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
951 	clk_register_clkdev(clk, "stmmacphy.3", NULL);
952 
953 	clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
954 			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
955 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART1_CLK_SHIFT,
956 			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
957 	clk_register_clkdev(clk, "uart1_mclk", NULL);
958 
959 	clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0,
960 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART1_CLK_ENB, 0,
961 			&_lock);
962 	clk_register_clkdev(clk, NULL, "5c800000.serial");
963 
964 	clk = clk_register_mux(NULL, "uart2_mclk", uart_parents,
965 			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
966 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART2_CLK_SHIFT,
967 			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
968 	clk_register_clkdev(clk, "uart2_mclk", NULL);
969 
970 	clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0,
971 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART2_CLK_ENB, 0,
972 			&_lock);
973 	clk_register_clkdev(clk, NULL, "5c900000.serial");
974 
975 	clk = clk_register_mux(NULL, "uart3_mclk", uart_parents,
976 			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
977 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART3_CLK_SHIFT,
978 			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
979 	clk_register_clkdev(clk, "uart3_mclk", NULL);
980 
981 	clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0,
982 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART3_CLK_ENB, 0,
983 			&_lock);
984 	clk_register_clkdev(clk, NULL, "5ca00000.serial");
985 
986 	clk = clk_register_mux(NULL, "uart4_mclk", uart_parents,
987 			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
988 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART4_CLK_SHIFT,
989 			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
990 	clk_register_clkdev(clk, "uart4_mclk", NULL);
991 
992 	clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0,
993 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART4_CLK_ENB, 0,
994 			&_lock);
995 	clk_register_clkdev(clk, NULL, "5cb00000.serial");
996 
997 	clk = clk_register_mux(NULL, "uart5_mclk", uart_parents,
998 			ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
999 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_UART5_CLK_SHIFT,
1000 			SPEAR1310_RAS_UART_CLK_MASK, 0, &_lock);
1001 	clk_register_clkdev(clk, "uart5_mclk", NULL);
1002 
1003 	clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0,
1004 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_UART5_CLK_ENB, 0,
1005 			&_lock);
1006 	clk_register_clkdev(clk, NULL, "5cc00000.serial");
1007 
1008 	clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents,
1009 			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1010 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C1_CLK_SHIFT,
1011 			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1012 	clk_register_clkdev(clk, "i2c1_mclk", NULL);
1013 
1014 	clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0,
1015 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C1_CLK_ENB, 0,
1016 			&_lock);
1017 	clk_register_clkdev(clk, NULL, "5cd00000.i2c");
1018 
1019 	clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents,
1020 			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1021 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C2_CLK_SHIFT,
1022 			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1023 	clk_register_clkdev(clk, "i2c2_mclk", NULL);
1024 
1025 	clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0,
1026 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C2_CLK_ENB, 0,
1027 			&_lock);
1028 	clk_register_clkdev(clk, NULL, "5ce00000.i2c");
1029 
1030 	clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents,
1031 			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1032 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C3_CLK_SHIFT,
1033 			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1034 	clk_register_clkdev(clk, "i2c3_mclk", NULL);
1035 
1036 	clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0,
1037 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C3_CLK_ENB, 0,
1038 			&_lock);
1039 	clk_register_clkdev(clk, NULL, "5cf00000.i2c");
1040 
1041 	clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents,
1042 			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1043 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C4_CLK_SHIFT,
1044 			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1045 	clk_register_clkdev(clk, "i2c4_mclk", NULL);
1046 
1047 	clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0,
1048 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C4_CLK_ENB, 0,
1049 			&_lock);
1050 	clk_register_clkdev(clk, NULL, "5d000000.i2c");
1051 
1052 	clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents,
1053 			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1054 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C5_CLK_SHIFT,
1055 			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1056 	clk_register_clkdev(clk, "i2c5_mclk", NULL);
1057 
1058 	clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0,
1059 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C5_CLK_ENB, 0,
1060 			&_lock);
1061 	clk_register_clkdev(clk, NULL, "5d100000.i2c");
1062 
1063 	clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents,
1064 			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1065 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C6_CLK_SHIFT,
1066 			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1067 	clk_register_clkdev(clk, "i2c6_mclk", NULL);
1068 
1069 	clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0,
1070 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C6_CLK_ENB, 0,
1071 			&_lock);
1072 	clk_register_clkdev(clk, NULL, "5d200000.i2c");
1073 
1074 	clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents,
1075 			ARRAY_SIZE(i2c_parents), CLK_SET_RATE_NO_REPARENT,
1076 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_I2C7_CLK_SHIFT,
1077 			SPEAR1310_I2C_CLK_MASK, 0, &_lock);
1078 	clk_register_clkdev(clk, "i2c7_mclk", NULL);
1079 
1080 	clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0,
1081 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_I2C7_CLK_ENB, 0,
1082 			&_lock);
1083 	clk_register_clkdev(clk, NULL, "5d300000.i2c");
1084 
1085 	clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents,
1086 			ARRAY_SIZE(ssp1_parents), CLK_SET_RATE_NO_REPARENT,
1087 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_SSP1_CLK_SHIFT,
1088 			SPEAR1310_SSP1_CLK_MASK, 0, &_lock);
1089 	clk_register_clkdev(clk, "ssp1_mclk", NULL);
1090 
1091 	clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0,
1092 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_SSP1_CLK_ENB, 0,
1093 			&_lock);
1094 	clk_register_clkdev(clk, NULL, "5d400000.spi");
1095 
1096 	clk = clk_register_mux(NULL, "pci_mclk", pci_parents,
1097 			ARRAY_SIZE(pci_parents), CLK_SET_RATE_NO_REPARENT,
1098 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_PCI_CLK_SHIFT,
1099 			SPEAR1310_PCI_CLK_MASK, 0, &_lock);
1100 	clk_register_clkdev(clk, "pci_mclk", NULL);
1101 
1102 	clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0,
1103 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_PCI_CLK_ENB, 0,
1104 			&_lock);
1105 	clk_register_clkdev(clk, NULL, "pci");
1106 
1107 	clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents,
1108 			ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1109 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM1_CLK_SHIFT,
1110 			SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1111 	clk_register_clkdev(clk, "tdm1_mclk", NULL);
1112 
1113 	clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0,
1114 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM1_CLK_ENB, 0,
1115 			&_lock);
1116 	clk_register_clkdev(clk, NULL, "tdm_hdlc.0");
1117 
1118 	clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents,
1119 			ARRAY_SIZE(tdm_parents), CLK_SET_RATE_NO_REPARENT,
1120 			SPEAR1310_RAS_CTRL_REG0, SPEAR1310_TDM2_CLK_SHIFT,
1121 			SPEAR1310_TDM_CLK_MASK, 0, &_lock);
1122 	clk_register_clkdev(clk, "tdm2_mclk", NULL);
1123 
1124 	clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0,
1125 			SPEAR1310_RAS_SW_CLK_CTRL, SPEAR1310_TDM2_CLK_ENB, 0,
1126 			&_lock);
1127 	clk_register_clkdev(clk, NULL, "tdm_hdlc.1");
1128 }
1129