xref: /openbmc/linux/drivers/clk/socfpga/clk.c (revision afc98d90)
1 /*
2  *  Copyright 2011-2012 Calxeda, Inc.
3  *  Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * Based from clk-highbank.c
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 #include <linux/clk.h>
21 #include <linux/clkdev.h>
22 #include <linux/clk-provider.h>
23 #include <linux/io.h>
24 #include <linux/of.h>
25 
26 /* Clock Manager offsets */
27 #define CLKMGR_CTRL	0x0
28 #define CLKMGR_BYPASS	0x4
29 #define CLKMGR_L4SRC	0x70
30 #define CLKMGR_PERPLL_SRC	0xAC
31 
32 /* Clock bypass bits */
33 #define MAINPLL_BYPASS		(1<<0)
34 #define SDRAMPLL_BYPASS		(1<<1)
35 #define SDRAMPLL_SRC_BYPASS	(1<<2)
36 #define PERPLL_BYPASS		(1<<3)
37 #define PERPLL_SRC_BYPASS	(1<<4)
38 
39 #define SOCFPGA_PLL_BG_PWRDWN		0
40 #define SOCFPGA_PLL_EXT_ENA		1
41 #define SOCFPGA_PLL_PWR_DOWN		2
42 #define SOCFPGA_PLL_DIVF_MASK		0x0000FFF8
43 #define SOCFPGA_PLL_DIVF_SHIFT	3
44 #define SOCFPGA_PLL_DIVQ_MASK		0x003F0000
45 #define SOCFPGA_PLL_DIVQ_SHIFT	16
46 #define SOCFGPA_MAX_PARENTS	3
47 
48 #define SOCFPGA_L4_MP_CLK		"l4_mp_clk"
49 #define SOCFPGA_L4_SP_CLK		"l4_sp_clk"
50 #define SOCFPGA_NAND_CLK		"nand_clk"
51 #define SOCFPGA_NAND_X_CLK		"nand_x_clk"
52 #define SOCFPGA_MMC_CLK			"sdmmc_clk"
53 #define SOCFPGA_DB_CLK			"gpio_db_clk"
54 
55 #define div_mask(width)	((1 << (width)) - 1)
56 #define streq(a, b) (strcmp((a), (b)) == 0)
57 
58 extern void __iomem *clk_mgr_base_addr;
59 
60 struct socfpga_clk {
61 	struct clk_gate hw;
62 	char *parent_name;
63 	char *clk_name;
64 	u32 fixed_div;
65 	void __iomem *div_reg;
66 	u32 width;	/* only valid if div_reg != 0 */
67 	u32 shift;	/* only valid if div_reg != 0 */
68 };
69 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
70 
71 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
72 					 unsigned long parent_rate)
73 {
74 	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
75 	unsigned long divf, divq, vco_freq, reg;
76 	unsigned long bypass;
77 
78 	reg = readl(socfpgaclk->hw.reg);
79 	bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
80 	if (bypass & MAINPLL_BYPASS)
81 		return parent_rate;
82 
83 	divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
84 	divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
85 	vco_freq = parent_rate * (divf + 1);
86 	return vco_freq / (1 + divq);
87 }
88 
89 
90 static struct clk_ops clk_pll_ops = {
91 	.recalc_rate = clk_pll_recalc_rate,
92 };
93 
94 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
95 					     unsigned long parent_rate)
96 {
97 	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
98 	u32 div;
99 
100 	if (socfpgaclk->fixed_div)
101 		div = socfpgaclk->fixed_div;
102 	else
103 		div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1);
104 
105 	return parent_rate / div;
106 }
107 
108 static const struct clk_ops periclk_ops = {
109 	.recalc_rate = clk_periclk_recalc_rate,
110 };
111 
112 static __init struct clk *socfpga_clk_init(struct device_node *node,
113 	const struct clk_ops *ops)
114 {
115 	u32 reg;
116 	struct clk *clk;
117 	struct socfpga_clk *socfpga_clk;
118 	const char *clk_name = node->name;
119 	const char *parent_name;
120 	struct clk_init_data init;
121 	int rc;
122 	u32 fixed_div;
123 
124 	of_property_read_u32(node, "reg", &reg);
125 
126 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
127 	if (WARN_ON(!socfpga_clk))
128 		return NULL;
129 
130 	socfpga_clk->hw.reg = clk_mgr_base_addr + reg;
131 
132 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
133 	if (rc)
134 		socfpga_clk->fixed_div = 0;
135 	else
136 		socfpga_clk->fixed_div = fixed_div;
137 
138 	of_property_read_string(node, "clock-output-names", &clk_name);
139 
140 	init.name = clk_name;
141 	init.ops = ops;
142 	init.flags = 0;
143 	parent_name = of_clk_get_parent_name(node, 0);
144 	init.parent_names = &parent_name;
145 	init.num_parents = 1;
146 
147 	socfpga_clk->hw.hw.init = &init;
148 
149 	if (streq(clk_name, "main_pll") ||
150 		streq(clk_name, "periph_pll") ||
151 		streq(clk_name, "sdram_pll")) {
152 		socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
153 		clk_pll_ops.enable = clk_gate_ops.enable;
154 		clk_pll_ops.disable = clk_gate_ops.disable;
155 	}
156 
157 	clk = clk_register(NULL, &socfpga_clk->hw.hw);
158 	if (WARN_ON(IS_ERR(clk))) {
159 		kfree(socfpga_clk);
160 		return NULL;
161 	}
162 	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
163 	return clk;
164 }
165 
166 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
167 {
168 	u32 l4_src;
169 	u32 perpll_src;
170 
171 	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
172 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
173 		return l4_src &= 0x1;
174 	}
175 	if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
176 		l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
177 		return !!(l4_src & 2);
178 	}
179 
180 	perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
181 	if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
182 		return perpll_src &= 0x3;
183 	if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
184 			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
185 			return (perpll_src >> 2) & 3;
186 
187 	/* QSPI clock */
188 	return (perpll_src >> 4) & 3;
189 
190 }
191 
192 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
193 {
194 	u32 src_reg;
195 
196 	if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
197 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
198 		src_reg &= ~0x1;
199 		src_reg |= parent;
200 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
201 	} else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
202 		src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
203 		src_reg &= ~0x2;
204 		src_reg |= (parent << 1);
205 		writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
206 	} else {
207 		src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
208 		if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
209 			src_reg &= ~0x3;
210 			src_reg |= parent;
211 		} else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
212 			streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
213 			src_reg &= ~0xC;
214 			src_reg |= (parent << 2);
215 		} else {/* QSPI clock */
216 			src_reg &= ~0x30;
217 			src_reg |= (parent << 4);
218 		}
219 		writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
220 	}
221 
222 	return 0;
223 }
224 
225 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
226 	unsigned long parent_rate)
227 {
228 	struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
229 	u32 div = 1, val;
230 
231 	if (socfpgaclk->fixed_div)
232 		div = socfpgaclk->fixed_div;
233 	else if (socfpgaclk->div_reg) {
234 		val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
235 		val &= div_mask(socfpgaclk->width);
236 		if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
237 			div = val + 1;
238 		else
239 			div = (1 << val);
240 	}
241 
242 	return parent_rate / div;
243 }
244 
245 static struct clk_ops gateclk_ops = {
246 	.recalc_rate = socfpga_clk_recalc_rate,
247 	.get_parent = socfpga_clk_get_parent,
248 	.set_parent = socfpga_clk_set_parent,
249 };
250 
251 static void __init socfpga_gate_clk_init(struct device_node *node,
252 	const struct clk_ops *ops)
253 {
254 	u32 clk_gate[2];
255 	u32 div_reg[3];
256 	u32 fixed_div;
257 	struct clk *clk;
258 	struct socfpga_clk *socfpga_clk;
259 	const char *clk_name = node->name;
260 	const char *parent_name[SOCFGPA_MAX_PARENTS];
261 	struct clk_init_data init;
262 	int rc;
263 	int i = 0;
264 
265 	socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
266 	if (WARN_ON(!socfpga_clk))
267 		return;
268 
269 	rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
270 	if (rc)
271 		clk_gate[0] = 0;
272 
273 	if (clk_gate[0]) {
274 		socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
275 		socfpga_clk->hw.bit_idx = clk_gate[1];
276 
277 		gateclk_ops.enable = clk_gate_ops.enable;
278 		gateclk_ops.disable = clk_gate_ops.disable;
279 	}
280 
281 	rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
282 	if (rc)
283 		socfpga_clk->fixed_div = 0;
284 	else
285 		socfpga_clk->fixed_div = fixed_div;
286 
287 	rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
288 	if (!rc) {
289 		socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
290 		socfpga_clk->shift = div_reg[1];
291 		socfpga_clk->width = div_reg[2];
292 	} else {
293 		socfpga_clk->div_reg = NULL;
294 	}
295 
296 	of_property_read_string(node, "clock-output-names", &clk_name);
297 
298 	init.name = clk_name;
299 	init.ops = ops;
300 	init.flags = 0;
301 	while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
302 			of_clk_get_parent_name(node, i)) != NULL)
303 		i++;
304 
305 	init.parent_names = parent_name;
306 	init.num_parents = i;
307 	socfpga_clk->hw.hw.init = &init;
308 
309 	clk = clk_register(NULL, &socfpga_clk->hw.hw);
310 	if (WARN_ON(IS_ERR(clk))) {
311 		kfree(socfpga_clk);
312 		return;
313 	}
314 	rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
315 	if (WARN_ON(rc))
316 		return;
317 }
318 
319 static void __init socfpga_pll_init(struct device_node *node)
320 {
321 	socfpga_clk_init(node, &clk_pll_ops);
322 }
323 CLK_OF_DECLARE(socfpga_pll, "altr,socfpga-pll-clock", socfpga_pll_init);
324 
325 static void __init socfpga_periph_init(struct device_node *node)
326 {
327 	socfpga_clk_init(node, &periclk_ops);
328 }
329 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
330 
331 static void __init socfpga_gate_init(struct device_node *node)
332 {
333 	socfpga_gate_clk_init(node, &gateclk_ops);
334 }
335 CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
336 
337 void __init socfpga_init_clocks(void)
338 {
339 	struct clk *clk;
340 	int ret;
341 
342 	clk = clk_register_fixed_factor(NULL, "smp_twd", "mpuclk", 0, 1, 4);
343 	ret = clk_register_clkdev(clk, NULL, "smp_twd");
344 	if (ret)
345 		pr_err("smp_twd alias not registered\n");
346 }
347