1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017, Intel Corporation 4 */ 5 #include <linux/slab.h> 6 #include <linux/clk-provider.h> 7 #include <linux/of_device.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 11 #include <dt-bindings/clock/stratix10-clock.h> 12 13 #include "stratix10-clk.h" 14 15 static const struct clk_parent_data pll_mux[] = { 16 { .fw_name = "osc1", 17 .name = "osc1" }, 18 { .fw_name = "cb-intosc-hs-div2-clk", 19 .name = "cb-intosc-hs-div2-clk" }, 20 { .fw_name = "f2s-free-clk", 21 .name = "f2s-free-clk" }, 22 }; 23 24 static const struct clk_parent_data cntr_mux[] = { 25 { .fw_name = "main_pll", 26 .name = "main_pll", }, 27 { .fw_name = "periph_pll", 28 .name = "periph_pll", }, 29 { .fw_name = "osc1", 30 .name = "osc1", }, 31 { .fw_name = "cb-intosc-hs-div2-clk", 32 .name = "cb-intosc-hs-div2-clk", }, 33 { .fw_name = "f2s-free-clk", 34 .name = "f2s-free-clk", }, 35 }; 36 37 static const struct clk_parent_data boot_mux[] = { 38 { .fw_name = "osc1", 39 .name = "osc1" }, 40 { .fw_name = "cb-intosc-hs-div2-clk", 41 .name = "cb-intosc-hs-div2-clk" }, 42 }; 43 44 static const struct clk_parent_data noc_free_mux[] = { 45 { .fw_name = "main_noc_base_clk", 46 .name = "main_noc_base_clk", }, 47 { .fw_name = "peri_noc_base_clk", 48 .name = "peri_noc_base_clk", }, 49 { .fw_name = "osc1", 50 .name = "osc1", }, 51 { .fw_name = "cb-intosc-hs-div2-clk", 52 .name = "cb-intosc-hs-div2-clk", }, 53 { .fw_name = "f2s-free-clk", 54 .name = "f2s-free-clk", }, 55 }; 56 57 static const struct clk_parent_data emaca_free_mux[] = { 58 { .fw_name = "peri_emaca_clk", 59 .name = "peri_emaca_clk", }, 60 { .fw_name = "boot_clk", 61 .name = "boot_clk", }, 62 }; 63 64 static const struct clk_parent_data emacb_free_mux[] = { 65 { .fw_name = "peri_emacb_clk", 66 .name = "peri_emacb_clk", }, 67 { .fw_name = "boot_clk", 68 .name = "boot_clk", }, 69 }; 70 71 static const struct clk_parent_data emac_ptp_free_mux[] = { 72 { .fw_name = "peri_emac_ptp_clk", 73 .name = "peri_emac_ptp_clk", }, 74 { .fw_name = "boot_clk", 75 .name = "boot_clk", }, 76 }; 77 78 static const struct clk_parent_data gpio_db_free_mux[] = { 79 { .fw_name = "peri_gpio_db_clk", 80 .name = "peri_gpio_db_clk", }, 81 { .fw_name = "boot_clk", 82 .name = "boot_clk", }, 83 }; 84 85 static const struct clk_parent_data sdmmc_free_mux[] = { 86 { .fw_name = "main_sdmmc_clk", 87 .name = "main_sdmmc_clk", }, 88 { .fw_name = "boot_clk", 89 .name = "boot_clk", }, 90 }; 91 92 static const struct clk_parent_data s2f_usr1_free_mux[] = { 93 { .fw_name = "peri_s2f_usr1_clk", 94 .name = "peri_s2f_usr1_clk", }, 95 { .fw_name = "boot_clk", 96 .name = "boot_clk", }, 97 }; 98 99 static const struct clk_parent_data psi_ref_free_mux[] = { 100 { .fw_name = "peri_psi_ref_clk", 101 .name = "peri_psi_ref_clk", }, 102 { .fw_name = "boot_clk", 103 .name = "boot_clk", }, 104 }; 105 106 static const struct clk_parent_data mpu_mux[] = { 107 { .fw_name = "mpu_free_clk", 108 .name = "mpu_free_clk", }, 109 { .fw_name = "boot_clk", 110 .name = "boot_clk", }, 111 }; 112 113 static const struct clk_parent_data s2f_usr0_mux[] = { 114 { .fw_name = "f2s-free-clk", 115 .name = "f2s-free-clk", }, 116 { .fw_name = "boot_clk", 117 .name = "boot_clk", }, 118 }; 119 120 static const struct clk_parent_data emac_mux[] = { 121 { .fw_name = "emaca_free_clk", 122 .name = "emaca_free_clk", }, 123 { .fw_name = "emacb_free_clk", 124 .name = "emacb_free_clk", }, 125 }; 126 127 static const struct clk_parent_data noc_mux[] = { 128 { .fw_name = "noc_free_clk", 129 .name = "noc_free_clk", }, 130 { .fw_name = "boot_clk", 131 .name = "boot_clk", }, 132 }; 133 134 static const struct clk_parent_data mpu_free_mux[] = { 135 { .fw_name = "main_mpu_base_clk", 136 .name = "main_mpu_base_clk", }, 137 { .fw_name = "peri_mpu_base_clk", 138 .name = "peri_mpu_base_clk", }, 139 { .fw_name = "osc1", 140 .name = "osc1", }, 141 { .fw_name = "cb-intosc-hs-div2-clk", 142 .name = "cb-intosc-hs-div2-clk", }, 143 { .fw_name = "f2s-free-clk", 144 .name = "f2s-free-clk", }, 145 }; 146 147 /* clocks in AO (always on) controller */ 148 static const struct stratix10_pll_clock s10_pll_clks[] = { 149 { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, 150 0x0}, 151 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), 152 0, 0x74}, 153 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), 154 0, 0xe4}, 155 }; 156 157 static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = { 158 { STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84}, 159 { STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88}, 160 { STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0, 161 0xF4}, 162 { STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0, 163 0xF8}, 164 }; 165 166 static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = { 167 { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux), 168 0, 0x48, 0, 0, 0}, 169 { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux), 170 0, 0x4C, 0, 0, 0}, 171 { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0, 172 0x50, 0, 0, 0}, 173 { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0, 174 0x54, 0, 0, 0}, 175 { STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0, 176 0x58, 0, 0, 0}, 177 { STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0, 178 0x5C, 0, 0, 0}, 179 { STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0, 180 0x60, 0, 0, 0}, 181 { STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 182 0, 0x64, 0, 0, 0}, 183 { STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0, 184 0x68, 0, 0, 0}, 185 { STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0, 186 0x6C, 0, 0, 0}, 187 { STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 188 0, 0xBC, 0, 0, 0}, 189 { STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 190 0, 0xC0, 0, 0, 0}, 191 { STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 192 0, 0xC4, 0, 0, 0}, 193 { STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 194 0, 0xC8, 0, 0, 0}, 195 { STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 196 0, 0xCC, 0, 0, 0}, 197 { STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0, 198 0xD0, 0, 0, 0}, 199 { STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 200 0, 0xD4, 0, 0, 0}, 201 { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0, 202 0xD8, 0, 0, 0}, 203 { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0, 204 0, 4, 0, 0}, 205 { STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 206 0, 0, 0, 0x3C, 1}, 207 { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), 208 0, 0, 2, 0xB0, 0}, 209 { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), 210 0, 0, 2, 0xB0, 1}, 211 { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux, 212 ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 2, 0xB0, 2}, 213 { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux, 214 ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3}, 215 { STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, 216 ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4}, 217 { STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, 218 ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5}, 219 { STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux, 220 ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6}, 221 }; 222 223 static const struct stratix10_gate_clock s10_gate_clks[] = { 224 { STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30, 225 0, 0, 0, 0, 0x3C, 0, 0}, 226 { STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30, 227 0, 0, 0, 0, 0, 0, 4}, 228 { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30, 229 0, 0, 0, 0, 0, 0, 2}, 230 { STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30, 231 1, 0x70, 0, 2, 0, 0, 0}, 232 { STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30, 233 2, 0x70, 8, 2, 0, 0, 0}, 234 { STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30, 235 3, 0x70, 16, 2, 0, 0, 0}, 236 { STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30, 237 4, 0x70, 24, 2, 0, 0, 0}, 238 { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30, 239 4, 0x70, 26, 2, 0, 0, 0}, 240 { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30, 241 4, 0x70, 28, 1, 0, 0, 0}, 242 { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30, 243 5, 0, 0, 0, 0, 0, 0}, 244 { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30, 245 6, 0, 0, 0, 0, 0, 0}, 246 { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, 247 0, 0, 0, 0, 0xDC, 26, 0}, 248 { STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, 249 1, 0, 0, 0, 0xDC, 27, 0}, 250 { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, 251 2, 0, 0, 0, 0xDC, 28, 0}, 252 { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4, 253 3, 0, 0, 0, 0, 0, 0}, 254 { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4, 255 4, 0xE0, 0, 16, 0, 0, 0}, 256 { STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4, 257 5, 0, 0, 0, 0, 0, 4}, 258 { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4, 259 6, 0, 0, 0, 0, 0, 0}, 260 { STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4, 261 7, 0, 0, 0, 0, 0, 0}, 262 { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 263 8, 0, 0, 0, 0, 0, 0}, 264 { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 265 9, 0, 0, 0, 0, 0, 0}, 266 { STRATIX10_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 267 10, 0, 0, 0, 0, 0, 0}, 268 { STRATIX10_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0xA4, 269 10, 0, 0, 0, 0, 0, 4}, 270 { STRATIX10_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0xA4, 271 10, 0, 0, 0, 0, 0, 4}, 272 }; 273 274 static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, 275 int nums, struct stratix10_clock_data *data) 276 { 277 struct clk_hw *hw_clk; 278 void __iomem *base = data->base; 279 int i; 280 281 for (i = 0; i < nums; i++) { 282 hw_clk = s10_register_periph(&clks[i], base); 283 if (IS_ERR(hw_clk)) { 284 pr_err("%s: failed to register clock %s\n", 285 __func__, clks[i].name); 286 continue; 287 } 288 data->clk_data.hws[clks[i].id] = hw_clk; 289 } 290 return 0; 291 } 292 293 static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks, 294 int nums, struct stratix10_clock_data *data) 295 { 296 struct clk_hw *hw_clk; 297 void __iomem *base = data->base; 298 int i; 299 300 for (i = 0; i < nums; i++) { 301 hw_clk = s10_register_cnt_periph(&clks[i], base); 302 if (IS_ERR(hw_clk)) { 303 pr_err("%s: failed to register clock %s\n", 304 __func__, clks[i].name); 305 continue; 306 } 307 data->clk_data.hws[clks[i].id] = hw_clk; 308 } 309 310 return 0; 311 } 312 313 static int s10_clk_register_gate(const struct stratix10_gate_clock *clks, 314 int nums, struct stratix10_clock_data *data) 315 { 316 struct clk_hw *hw_clk; 317 void __iomem *base = data->base; 318 int i; 319 320 for (i = 0; i < nums; i++) { 321 hw_clk = s10_register_gate(&clks[i], base); 322 if (IS_ERR(hw_clk)) { 323 pr_err("%s: failed to register clock %s\n", 324 __func__, clks[i].name); 325 continue; 326 } 327 data->clk_data.hws[clks[i].id] = hw_clk; 328 } 329 330 return 0; 331 } 332 333 static int s10_clk_register_pll(const struct stratix10_pll_clock *clks, 334 int nums, struct stratix10_clock_data *data) 335 { 336 struct clk_hw *hw_clk; 337 void __iomem *base = data->base; 338 int i; 339 340 for (i = 0; i < nums; i++) { 341 hw_clk = s10_register_pll(&clks[i], base); 342 if (IS_ERR(hw_clk)) { 343 pr_err("%s: failed to register clock %s\n", 344 __func__, clks[i].name); 345 continue; 346 } 347 data->clk_data.hws[clks[i].id] = hw_clk; 348 } 349 350 return 0; 351 } 352 353 static int s10_clkmgr_init(struct platform_device *pdev) 354 { 355 struct device_node *np = pdev->dev.of_node; 356 struct device *dev = &pdev->dev; 357 struct stratix10_clock_data *clk_data; 358 struct resource *res; 359 void __iomem *base; 360 int i, num_clks; 361 362 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 363 base = devm_ioremap_resource(dev, res); 364 if (IS_ERR(base)) { 365 pr_err("%s: failed to map clock registers\n", __func__); 366 return PTR_ERR(base); 367 } 368 369 num_clks = STRATIX10_NUM_CLKS; 370 clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws, 371 num_clks), GFP_KERNEL); 372 if (!clk_data) 373 return -ENOMEM; 374 375 for (i = 0; i < num_clks; i++) 376 clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT); 377 378 clk_data->base = base; 379 clk_data->clk_data.num = num_clks; 380 381 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data); 382 383 s10_clk_register_c_perip(s10_main_perip_c_clks, 384 ARRAY_SIZE(s10_main_perip_c_clks), clk_data); 385 386 s10_clk_register_cnt_perip(s10_main_perip_cnt_clks, 387 ARRAY_SIZE(s10_main_perip_cnt_clks), 388 clk_data); 389 390 s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks), 391 clk_data); 392 393 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data); 394 return 0; 395 } 396 397 static int s10_clkmgr_probe(struct platform_device *pdev) 398 { 399 return s10_clkmgr_init(pdev); 400 } 401 402 static const struct of_device_id stratix10_clkmgr_match_table[] = { 403 { .compatible = "intel,stratix10-clkmgr", 404 .data = s10_clkmgr_init }, 405 { } 406 }; 407 408 static struct platform_driver stratix10_clkmgr_driver = { 409 .probe = s10_clkmgr_probe, 410 .driver = { 411 .name = "stratix10-clkmgr", 412 .suppress_bind_attrs = true, 413 .of_match_table = stratix10_clkmgr_match_table, 414 }, 415 }; 416 417 static int __init s10_clk_init(void) 418 { 419 return platform_driver_register(&stratix10_clkmgr_driver); 420 } 421 core_initcall(s10_clk_init); 422