1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017, Intel Corporation 4 */ 5 #include <linux/slab.h> 6 #include <linux/clk-provider.h> 7 #include <linux/of_device.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 11 #include <dt-bindings/clock/stratix10-clock.h> 12 13 #include "stratix10-clk.h" 14 15 static const char * const pll_mux[] = { "osc1", "cb-intosc-hs-div2-clk", 16 "f2s-free-clk",}; 17 static const char * const cntr_mux[] = { "main_pll", "periph_pll", 18 "osc1", "cb-intosc-hs-div2-clk", 19 "f2s-free-clk"}; 20 static const char * const boot_mux[] = { "osc1", "cb-intosc-hs-div2-clk",}; 21 22 static const char * const noc_free_mux[] = {"main_noc_base_clk", 23 "peri_noc_base_clk", 24 "osc1", "cb-intosc-hs-div2-clk", 25 "f2s-free-clk"}; 26 27 static const char * const emaca_free_mux[] = {"peri_emaca_clk", "boot_clk"}; 28 static const char * const emacb_free_mux[] = {"peri_emacb_clk", "boot_clk"}; 29 static const char * const emac_ptp_free_mux[] = {"peri_emac_ptp_clk", "boot_clk"}; 30 static const char * const gpio_db_free_mux[] = {"peri_gpio_db_clk", "boot_clk"}; 31 static const char * const sdmmc_free_mux[] = {"main_sdmmc_clk", "boot_clk"}; 32 static const char * const s2f_usr1_free_mux[] = {"peri_s2f_usr1_clk", "boot_clk"}; 33 static const char * const psi_ref_free_mux[] = {"peri_psi_ref_clk", "boot_clk"}; 34 static const char * const mpu_mux[] = { "mpu_free_clk", "boot_clk",}; 35 36 static const char * const s2f_usr0_mux[] = {"f2s-free-clk", "boot_clk"}; 37 static const char * const emac_mux[] = {"emaca_free_clk", "emacb_free_clk"}; 38 static const char * const noc_mux[] = {"noc_free_clk", "boot_clk"}; 39 40 static const char * const mpu_free_mux[] = {"main_mpu_base_clk", 41 "peri_mpu_base_clk", 42 "osc1", "cb-intosc-hs-div2-clk", 43 "f2s-free-clk"}; 44 45 /* clocks in AO (always on) controller */ 46 static const struct stratix10_pll_clock s10_pll_clks[] = { 47 { STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0, 48 0x0}, 49 { STRATIX10_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux), 50 0, 0x74}, 51 { STRATIX10_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux), 52 0, 0xe4}, 53 }; 54 55 static const struct stratix10_perip_c_clock s10_main_perip_c_clks[] = { 56 { STRATIX10_MAIN_MPU_BASE_CLK, "main_mpu_base_clk", "main_pll", NULL, 1, 0, 0x84}, 57 { STRATIX10_MAIN_NOC_BASE_CLK, "main_noc_base_clk", "main_pll", NULL, 1, 0, 0x88}, 58 { STRATIX10_PERI_MPU_BASE_CLK, "peri_mpu_base_clk", "periph_pll", NULL, 1, 0, 59 0xF4}, 60 { STRATIX10_PERI_NOC_BASE_CLK, "peri_noc_base_clk", "periph_pll", NULL, 1, 0, 61 0xF8}, 62 }; 63 64 static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = { 65 { STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux), 66 0, 0x48, 0, 0, 0}, 67 { STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux), 68 0, 0x4C, 0, 0, 0}, 69 { STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0, 70 0x50, 0, 0, 0}, 71 { STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0, 72 0x54, 0, 0, 0}, 73 { STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0, 74 0x58, 0, 0, 0}, 75 { STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0, 76 0x5C, 0, 0, 0}, 77 { STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0, 78 0x60, 0, 0, 0}, 79 { STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 80 0, 0x64, 0, 0, 0}, 81 { STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0, 82 0x68, 0, 0, 0}, 83 { STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0, 84 0x6C, 0, 0, 0}, 85 { STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 86 0, 0xBC, 0, 0, 0}, 87 { STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 88 0, 0xC0, 0, 0, 0}, 89 { STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 90 0, 0xC4, 0, 0, 0}, 91 { STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 92 0, 0xC8, 0, 0, 0}, 93 { STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 94 0, 0xCC, 0, 0, 0}, 95 { STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0, 96 0xD0, 0, 0, 0}, 97 { STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux), 98 0, 0xD4, 0, 0, 0}, 99 { STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0, 100 0xD8, 0, 0, 0}, 101 { STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0, 102 0, 4, 0, 0}, 103 { STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 104 0, 0, 0, 0x3C, 1}, 105 { STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux), 106 0, 0, 4, 0xB0, 0}, 107 { STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux), 108 0, 0, 4, 0xB0, 1}, 109 { STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux, 110 ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2}, 111 { STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux, 112 ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3}, 113 { STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, 114 ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4}, 115 { STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, 116 ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5}, 117 { STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux, 118 ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6}, 119 }; 120 121 static const struct stratix10_gate_clock s10_gate_clks[] = { 122 { STRATIX10_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x30, 123 0, 0, 0, 0, 0x3C, 0, 0}, 124 { STRATIX10_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x30, 125 0, 0, 0, 0, 0, 0, 4}, 126 { STRATIX10_MPU_L2RAM_CLK, "mpu_l2ram_clk", "mpu_clk", NULL, 1, 0, 0x30, 127 0, 0, 0, 0, 0, 0, 2}, 128 { STRATIX10_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x30, 129 1, 0x70, 0, 2, 0, 0, 0}, 130 { STRATIX10_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x30, 131 2, 0x70, 8, 2, 0, 0, 0}, 132 { STRATIX10_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x30, 133 3, 0x70, 16, 2, 0, 0, 0}, 134 { STRATIX10_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x30, 135 4, 0x70, 24, 2, 0, 0, 0}, 136 { STRATIX10_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x30, 137 4, 0x70, 26, 2, 0, 0, 0}, 138 { STRATIX10_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x30, 139 4, 0x70, 28, 1, 0, 0, 0}, 140 { STRATIX10_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x30, 141 5, 0, 0, 0, 0, 0, 0}, 142 { STRATIX10_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x30, 143 6, 0, 0, 0, 0, 0, 0}, 144 { STRATIX10_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, 145 0, 0, 0, 0, 0xDC, 26, 0}, 146 { STRATIX10_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, 147 1, 0, 0, 0, 0xDC, 27, 0}, 148 { STRATIX10_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0xA4, 149 2, 0, 0, 0, 0xDC, 28, 0}, 150 { STRATIX10_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0xA4, 151 3, 0, 0, 0, 0, 0, 0}, 152 { STRATIX10_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0xA4, 153 4, 0xE0, 0, 16, 0, 0, 0}, 154 { STRATIX10_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0xA4, 155 5, 0, 0, 0, 0, 0, 4}, 156 { STRATIX10_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0xA4, 157 6, 0, 0, 0, 0, 0, 0}, 158 { STRATIX10_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0xA4, 159 7, 0, 0, 0, 0, 0, 0}, 160 { STRATIX10_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 161 8, 0, 0, 0, 0, 0, 0}, 162 { STRATIX10_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0xA4, 163 9, 0, 0, 0, 0, 0, 0}, 164 { STRATIX10_NAND_CLK, "nand_clk", "l4_main_clk", NULL, 1, 0, 0xA4, 165 10, 0, 0, 0, 0, 0, 0}, 166 }; 167 168 static int s10_clk_register_c_perip(const struct stratix10_perip_c_clock *clks, 169 int nums, struct stratix10_clock_data *data) 170 { 171 struct clk *clk; 172 void __iomem *base = data->base; 173 int i; 174 175 for (i = 0; i < nums; i++) { 176 clk = s10_register_periph(clks[i].name, clks[i].parent_name, 177 clks[i].parent_names, clks[i].num_parents, 178 clks[i].flags, base, clks[i].offset); 179 if (IS_ERR(clk)) { 180 pr_err("%s: failed to register clock %s\n", 181 __func__, clks[i].name); 182 continue; 183 } 184 data->clk_data.clks[clks[i].id] = clk; 185 } 186 return 0; 187 } 188 189 static int s10_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks, 190 int nums, struct stratix10_clock_data *data) 191 { 192 struct clk *clk; 193 void __iomem *base = data->base; 194 int i; 195 196 for (i = 0; i < nums; i++) { 197 clk = s10_register_cnt_periph(clks[i].name, clks[i].parent_name, 198 clks[i].parent_names, 199 clks[i].num_parents, 200 clks[i].flags, base, 201 clks[i].offset, 202 clks[i].fixed_divider, 203 clks[i].bypass_reg, 204 clks[i].bypass_shift); 205 if (IS_ERR(clk)) { 206 pr_err("%s: failed to register clock %s\n", 207 __func__, clks[i].name); 208 continue; 209 } 210 data->clk_data.clks[clks[i].id] = clk; 211 } 212 213 return 0; 214 } 215 216 static int s10_clk_register_gate(const struct stratix10_gate_clock *clks, 217 int nums, struct stratix10_clock_data *data) 218 { 219 struct clk *clk; 220 void __iomem *base = data->base; 221 int i; 222 223 for (i = 0; i < nums; i++) { 224 clk = s10_register_gate(clks[i].name, clks[i].parent_name, 225 clks[i].parent_names, 226 clks[i].num_parents, 227 clks[i].flags, base, 228 clks[i].gate_reg, 229 clks[i].gate_idx, clks[i].div_reg, 230 clks[i].div_offset, clks[i].div_width, 231 clks[i].bypass_reg, 232 clks[i].bypass_shift, 233 clks[i].fixed_div); 234 if (IS_ERR(clk)) { 235 pr_err("%s: failed to register clock %s\n", 236 __func__, clks[i].name); 237 continue; 238 } 239 data->clk_data.clks[clks[i].id] = clk; 240 } 241 242 return 0; 243 } 244 245 static int s10_clk_register_pll(const struct stratix10_pll_clock *clks, 246 int nums, struct stratix10_clock_data *data) 247 { 248 struct clk *clk; 249 void __iomem *base = data->base; 250 int i; 251 252 for (i = 0; i < nums; i++) { 253 clk = s10_register_pll(clks[i].name, clks[i].parent_names, 254 clks[i].num_parents, 255 clks[i].flags, base, 256 clks[i].offset); 257 if (IS_ERR(clk)) { 258 pr_err("%s: failed to register clock %s\n", 259 __func__, clks[i].name); 260 continue; 261 } 262 data->clk_data.clks[clks[i].id] = clk; 263 } 264 265 return 0; 266 } 267 268 static struct stratix10_clock_data *__socfpga_s10_clk_init(struct platform_device *pdev, 269 int nr_clks) 270 { 271 struct device_node *np = pdev->dev.of_node; 272 struct device *dev = &pdev->dev; 273 struct stratix10_clock_data *clk_data; 274 struct clk **clk_table; 275 struct resource *res; 276 void __iomem *base; 277 278 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 279 base = devm_ioremap_resource(dev, res); 280 if (IS_ERR(base)) { 281 pr_err("%s: failed to map clock registers\n", __func__); 282 return ERR_CAST(base); 283 } 284 285 clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL); 286 if (!clk_data) 287 return ERR_PTR(-ENOMEM); 288 289 clk_data->base = base; 290 clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL); 291 if (!clk_table) 292 return ERR_PTR(-ENOMEM); 293 294 clk_data->clk_data.clks = clk_table; 295 clk_data->clk_data.clk_num = nr_clks; 296 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data); 297 return clk_data; 298 } 299 300 static int s10_clkmgr_init(struct platform_device *pdev) 301 { 302 struct stratix10_clock_data *clk_data; 303 304 clk_data = __socfpga_s10_clk_init(pdev, STRATIX10_NUM_CLKS); 305 if (IS_ERR(clk_data)) 306 return PTR_ERR(clk_data); 307 308 s10_clk_register_pll(s10_pll_clks, ARRAY_SIZE(s10_pll_clks), clk_data); 309 310 s10_clk_register_c_perip(s10_main_perip_c_clks, 311 ARRAY_SIZE(s10_main_perip_c_clks), clk_data); 312 313 s10_clk_register_cnt_perip(s10_main_perip_cnt_clks, 314 ARRAY_SIZE(s10_main_perip_cnt_clks), 315 clk_data); 316 317 s10_clk_register_gate(s10_gate_clks, ARRAY_SIZE(s10_gate_clks), 318 clk_data); 319 return 0; 320 } 321 322 static int s10_clkmgr_probe(struct platform_device *pdev) 323 { 324 return s10_clkmgr_init(pdev); 325 } 326 327 static const struct of_device_id stratix10_clkmgr_match_table[] = { 328 { .compatible = "intel,stratix10-clkmgr", 329 .data = s10_clkmgr_init }, 330 { } 331 }; 332 333 static struct platform_driver stratix10_clkmgr_driver = { 334 .probe = s10_clkmgr_probe, 335 .driver = { 336 .name = "stratix10-clkmgr", 337 .suppress_bind_attrs = true, 338 .of_match_table = stratix10_clkmgr_match_table, 339 }, 340 }; 341 342 static int __init s10_clk_init(void) 343 { 344 return platform_driver_register(&stratix10_clkmgr_driver); 345 } 346 core_initcall(s10_clk_init); 347