1 /* 2 * Copyright 2011-2012 Calxeda, Inc. 3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * Based from clk-highbank.c 16 * 17 */ 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/clk-provider.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 24 #include "clk.h" 25 26 /* Clock bypass bits */ 27 #define MAINPLL_BYPASS (1<<0) 28 #define SDRAMPLL_BYPASS (1<<1) 29 #define SDRAMPLL_SRC_BYPASS (1<<2) 30 #define PERPLL_BYPASS (1<<3) 31 #define PERPLL_SRC_BYPASS (1<<4) 32 33 #define SOCFPGA_PLL_BG_PWRDWN 0 34 #define SOCFPGA_PLL_EXT_ENA 1 35 #define SOCFPGA_PLL_PWR_DOWN 2 36 #define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8 37 #define SOCFPGA_PLL_DIVF_SHIFT 3 38 #define SOCFPGA_PLL_DIVQ_MASK 0x003F0000 39 #define SOCFPGA_PLL_DIVQ_SHIFT 16 40 41 #define CLK_MGR_PLL_CLK_SRC_SHIFT 22 42 #define CLK_MGR_PLL_CLK_SRC_MASK 0x3 43 44 #define to_socfpga_clk(p) container_of(p, struct socfpga_pll, hw.hw) 45 46 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, 47 unsigned long parent_rate) 48 { 49 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); 50 unsigned long divf, divq, reg; 51 unsigned long long vco_freq; 52 unsigned long bypass; 53 54 reg = readl(socfpgaclk->hw.reg); 55 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); 56 if (bypass & MAINPLL_BYPASS) 57 return parent_rate; 58 59 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; 60 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; 61 vco_freq = (unsigned long long)parent_rate * (divf + 1); 62 do_div(vco_freq, (1 + divq)); 63 return (unsigned long)vco_freq; 64 } 65 66 static u8 clk_pll_get_parent(struct clk_hw *hwclk) 67 { 68 u32 pll_src; 69 struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); 70 71 pll_src = readl(socfpgaclk->hw.reg); 72 return (pll_src >> CLK_MGR_PLL_CLK_SRC_SHIFT) & 73 CLK_MGR_PLL_CLK_SRC_MASK; 74 } 75 76 static struct clk_ops clk_pll_ops = { 77 .recalc_rate = clk_pll_recalc_rate, 78 .get_parent = clk_pll_get_parent, 79 }; 80 81 static __init struct clk *__socfpga_pll_init(struct device_node *node, 82 const struct clk_ops *ops) 83 { 84 u32 reg; 85 struct clk *clk; 86 struct socfpga_pll *pll_clk; 87 const char *clk_name = node->name; 88 const char *parent_name[SOCFPGA_MAX_PARENTS]; 89 struct clk_init_data init; 90 int rc; 91 int i = 0; 92 93 of_property_read_u32(node, "reg", ®); 94 95 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 96 if (WARN_ON(!pll_clk)) 97 return NULL; 98 99 pll_clk->hw.reg = clk_mgr_base_addr + reg; 100 101 of_property_read_string(node, "clock-output-names", &clk_name); 102 103 init.name = clk_name; 104 init.ops = ops; 105 init.flags = 0; 106 107 while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] = 108 of_clk_get_parent_name(node, i)) != NULL) 109 i++; 110 111 init.num_parents = i; 112 init.parent_names = parent_name; 113 pll_clk->hw.hw.init = &init; 114 115 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; 116 clk_pll_ops.enable = clk_gate_ops.enable; 117 clk_pll_ops.disable = clk_gate_ops.disable; 118 119 clk = clk_register(NULL, &pll_clk->hw.hw); 120 if (WARN_ON(IS_ERR(clk))) { 121 kfree(pll_clk); 122 return NULL; 123 } 124 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 125 return clk; 126 } 127 128 void __init socfpga_pll_init(struct device_node *node) 129 { 130 __socfpga_pll_init(node, &clk_pll_ops); 131 } 132