1 /* 2 * Copyright 2011-2012 Calxeda, Inc. 3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * Based from clk-highbank.c 16 * 17 */ 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/clk-provider.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 24 #include "clk.h" 25 26 #define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw) 27 28 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, 29 unsigned long parent_rate) 30 { 31 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); 32 u32 div; 33 34 if (socfpgaclk->fixed_div) 35 div = socfpgaclk->fixed_div; 36 else 37 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); 38 39 return parent_rate / div; 40 } 41 42 static const struct clk_ops periclk_ops = { 43 .recalc_rate = clk_periclk_recalc_rate, 44 }; 45 46 static __init void __socfpga_periph_init(struct device_node *node, 47 const struct clk_ops *ops) 48 { 49 u32 reg; 50 struct clk *clk; 51 struct socfpga_periph_clk *periph_clk; 52 const char *clk_name = node->name; 53 const char *parent_name; 54 struct clk_init_data init; 55 int rc; 56 u32 fixed_div; 57 58 of_property_read_u32(node, "reg", ®); 59 60 periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL); 61 if (WARN_ON(!periph_clk)) 62 return; 63 64 periph_clk->hw.reg = clk_mgr_base_addr + reg; 65 66 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 67 if (rc) 68 periph_clk->fixed_div = 0; 69 else 70 periph_clk->fixed_div = fixed_div; 71 72 of_property_read_string(node, "clock-output-names", &clk_name); 73 74 init.name = clk_name; 75 init.ops = ops; 76 init.flags = 0; 77 parent_name = of_clk_get_parent_name(node, 0); 78 init.parent_names = &parent_name; 79 init.num_parents = 1; 80 81 periph_clk->hw.hw.init = &init; 82 83 clk = clk_register(NULL, &periph_clk->hw.hw); 84 if (WARN_ON(IS_ERR(clk))) { 85 kfree(periph_clk); 86 return; 87 } 88 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 89 } 90 91 void __init socfpga_periph_init(struct device_node *node) 92 { 93 __socfpga_periph_init(node, &periclk_ops); 94 } 95