1 /* 2 * Copyright 2011-2012 Calxeda, Inc. 3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * Based from clk-highbank.c 16 * 17 */ 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/clk-provider.h> 21 #include <linux/io.h> 22 #include <linux/of.h> 23 24 #include "clk.h" 25 26 #define to_socfpga_periph_clk(p) container_of(p, struct socfpga_periph_clk, hw.hw) 27 28 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, 29 unsigned long parent_rate) 30 { 31 struct socfpga_periph_clk *socfpgaclk = to_socfpga_periph_clk(hwclk); 32 u32 div, val; 33 34 if (socfpgaclk->fixed_div) { 35 div = socfpgaclk->fixed_div; 36 } else { 37 if (socfpgaclk->div_reg) { 38 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 39 val &= div_mask(socfpgaclk->width); 40 parent_rate /= (val + 1); 41 } 42 div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); 43 } 44 45 return parent_rate / div; 46 } 47 48 static const struct clk_ops periclk_ops = { 49 .recalc_rate = clk_periclk_recalc_rate, 50 }; 51 52 static __init void __socfpga_periph_init(struct device_node *node, 53 const struct clk_ops *ops) 54 { 55 u32 reg; 56 struct clk *clk; 57 struct socfpga_periph_clk *periph_clk; 58 const char *clk_name = node->name; 59 const char *parent_name; 60 struct clk_init_data init; 61 int rc; 62 u32 fixed_div; 63 u32 div_reg[3]; 64 65 of_property_read_u32(node, "reg", ®); 66 67 periph_clk = kzalloc(sizeof(*periph_clk), GFP_KERNEL); 68 if (WARN_ON(!periph_clk)) 69 return; 70 71 periph_clk->hw.reg = clk_mgr_base_addr + reg; 72 73 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); 74 if (!rc) { 75 periph_clk->div_reg = clk_mgr_base_addr + div_reg[0]; 76 periph_clk->shift = div_reg[1]; 77 periph_clk->width = div_reg[2]; 78 } else { 79 periph_clk->div_reg = 0; 80 } 81 82 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 83 if (rc) 84 periph_clk->fixed_div = 0; 85 else 86 periph_clk->fixed_div = fixed_div; 87 88 of_property_read_string(node, "clock-output-names", &clk_name); 89 90 init.name = clk_name; 91 init.ops = ops; 92 init.flags = 0; 93 parent_name = of_clk_get_parent_name(node, 0); 94 init.parent_names = &parent_name; 95 init.num_parents = 1; 96 97 periph_clk->hw.hw.init = &init; 98 99 clk = clk_register(NULL, &periph_clk->hw.hw); 100 if (WARN_ON(IS_ERR(clk))) { 101 kfree(periph_clk); 102 return; 103 } 104 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 105 } 106 107 void __init socfpga_periph_init(struct device_node *node) 108 { 109 __socfpga_periph_init(node, &periclk_ops); 110 } 111