1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2011-2012 Calxeda, Inc. 4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 5 * 6 * Based from clk-highbank.c 7 */ 8 #include <linux/slab.h> 9 #include <linux/clk-provider.h> 10 #include <linux/io.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/regmap.h> 14 15 #include "clk.h" 16 17 #define SOCFPGA_L4_MP_CLK "l4_mp_clk" 18 #define SOCFPGA_L4_SP_CLK "l4_sp_clk" 19 #define SOCFPGA_NAND_CLK "nand_clk" 20 #define SOCFPGA_NAND_X_CLK "nand_x_clk" 21 #define SOCFPGA_MMC_CLK "sdmmc_clk" 22 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 23 24 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) 25 26 /* SDMMC Group for System Manager defines */ 27 #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 28 29 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) 30 { 31 u32 l4_src; 32 u32 perpll_src; 33 const char *name = clk_hw_get_name(hwclk); 34 35 if (streq(name, SOCFPGA_L4_MP_CLK)) { 36 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 37 return l4_src & 0x1; 38 } 39 if (streq(name, SOCFPGA_L4_SP_CLK)) { 40 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 41 return !!(l4_src & 2); 42 } 43 44 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 45 if (streq(name, SOCFPGA_MMC_CLK)) 46 return perpll_src & 0x3; 47 if (streq(name, SOCFPGA_NAND_CLK) || 48 streq(name, SOCFPGA_NAND_X_CLK)) 49 return (perpll_src >> 2) & 3; 50 51 /* QSPI clock */ 52 return (perpll_src >> 4) & 3; 53 54 } 55 56 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) 57 { 58 u32 src_reg; 59 const char *name = clk_hw_get_name(hwclk); 60 61 if (streq(name, SOCFPGA_L4_MP_CLK)) { 62 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 63 src_reg &= ~0x1; 64 src_reg |= parent; 65 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 66 } else if (streq(name, SOCFPGA_L4_SP_CLK)) { 67 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 68 src_reg &= ~0x2; 69 src_reg |= (parent << 1); 70 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 71 } else { 72 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 73 if (streq(name, SOCFPGA_MMC_CLK)) { 74 src_reg &= ~0x3; 75 src_reg |= parent; 76 } else if (streq(name, SOCFPGA_NAND_CLK) || 77 streq(name, SOCFPGA_NAND_X_CLK)) { 78 src_reg &= ~0xC; 79 src_reg |= (parent << 2); 80 } else {/* QSPI clock */ 81 src_reg &= ~0x30; 82 src_reg |= (parent << 4); 83 } 84 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 85 } 86 87 return 0; 88 } 89 90 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, 91 unsigned long parent_rate) 92 { 93 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 94 u32 div = 1, val; 95 96 if (socfpgaclk->fixed_div) 97 div = socfpgaclk->fixed_div; 98 else if (socfpgaclk->div_reg) { 99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 100 val &= GENMASK(socfpgaclk->width - 1, 0); 101 /* Check for GPIO_DB_CLK by its offset */ 102 if ((uintptr_t) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) 103 div = val + 1; 104 else 105 div = (1 << val); 106 } 107 108 return parent_rate / div; 109 } 110 111 static struct clk_ops gateclk_ops = { 112 .recalc_rate = socfpga_clk_recalc_rate, 113 .get_parent = socfpga_clk_get_parent, 114 .set_parent = socfpga_clk_set_parent, 115 }; 116 117 void __init socfpga_gate_init(struct device_node *node) 118 { 119 u32 clk_gate[2]; 120 u32 div_reg[3]; 121 u32 fixed_div; 122 struct clk_hw *hw_clk; 123 struct socfpga_gate_clk *socfpga_clk; 124 const char *clk_name = node->name; 125 const char *parent_name[SOCFPGA_MAX_PARENTS]; 126 struct clk_init_data init; 127 struct clk_ops *ops; 128 int rc; 129 130 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); 131 if (WARN_ON(!socfpga_clk)) 132 return; 133 134 ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL); 135 if (WARN_ON(!ops)) 136 goto err_kmemdup; 137 138 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); 139 if (rc) 140 clk_gate[0] = 0; 141 142 if (clk_gate[0]) { 143 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; 144 socfpga_clk->hw.bit_idx = clk_gate[1]; 145 146 ops->enable = clk_gate_ops.enable; 147 ops->disable = clk_gate_ops.disable; 148 } 149 150 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 151 if (rc) 152 socfpga_clk->fixed_div = 0; 153 else 154 socfpga_clk->fixed_div = fixed_div; 155 156 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); 157 if (!rc) { 158 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; 159 socfpga_clk->shift = div_reg[1]; 160 socfpga_clk->width = div_reg[2]; 161 } else { 162 socfpga_clk->div_reg = NULL; 163 } 164 165 of_property_read_string(node, "clock-output-names", &clk_name); 166 167 init.name = clk_name; 168 init.ops = ops; 169 init.flags = 0; 170 171 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); 172 if (init.num_parents < 2) { 173 ops->get_parent = NULL; 174 ops->set_parent = NULL; 175 } 176 177 init.parent_names = parent_name; 178 socfpga_clk->hw.hw.init = &init; 179 180 hw_clk = &socfpga_clk->hw.hw; 181 182 rc = clk_hw_register(NULL, hw_clk); 183 if (rc) { 184 pr_err("Could not register clock:%s\n", clk_name); 185 goto err_clk_hw_register; 186 } 187 188 rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw_clk); 189 if (rc) { 190 pr_err("Could not register clock provider for node:%s\n", 191 clk_name); 192 goto err_of_clk_add_hw_provider; 193 } 194 195 return; 196 197 err_of_clk_add_hw_provider: 198 clk_hw_unregister(hw_clk); 199 err_clk_hw_register: 200 kfree(ops); 201 err_kmemdup: 202 kfree(socfpga_clk); 203 } 204