1 /* 2 * Copyright 2011-2012 Calxeda, Inc. 3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * Based from clk-highbank.c 16 * 17 */ 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/clk-provider.h> 21 #include <linux/io.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/of.h> 24 #include <linux/regmap.h> 25 26 #include "clk.h" 27 28 #define SOCFPGA_L4_MP_CLK "l4_mp_clk" 29 #define SOCFPGA_L4_SP_CLK "l4_sp_clk" 30 #define SOCFPGA_NAND_CLK "nand_clk" 31 #define SOCFPGA_NAND_X_CLK "nand_x_clk" 32 #define SOCFPGA_MMC_CLK "sdmmc_clk" 33 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 34 35 #define div_mask(width) ((1 << (width)) - 1) 36 #define streq(a, b) (strcmp((a), (b)) == 0) 37 38 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) 39 40 /* SDMMC Group for System Manager defines */ 41 #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 42 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ 43 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0)) 44 45 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) 46 { 47 u32 l4_src; 48 u32 perpll_src; 49 50 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 51 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 52 return l4_src &= 0x1; 53 } 54 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 55 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 56 return !!(l4_src & 2); 57 } 58 59 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 60 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) 61 return perpll_src &= 0x3; 62 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 63 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) 64 return (perpll_src >> 2) & 3; 65 66 /* QSPI clock */ 67 return (perpll_src >> 4) & 3; 68 69 } 70 71 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) 72 { 73 u32 src_reg; 74 75 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 76 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 77 src_reg &= ~0x1; 78 src_reg |= parent; 79 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 80 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 81 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 82 src_reg &= ~0x2; 83 src_reg |= (parent << 1); 84 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 85 } else { 86 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 87 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) { 88 src_reg &= ~0x3; 89 src_reg |= parent; 90 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 91 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) { 92 src_reg &= ~0xC; 93 src_reg |= (parent << 2); 94 } else {/* QSPI clock */ 95 src_reg &= ~0x30; 96 src_reg |= (parent << 4); 97 } 98 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 99 } 100 101 return 0; 102 } 103 104 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, 105 unsigned long parent_rate) 106 { 107 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 108 u32 div = 1, val; 109 110 if (socfpgaclk->fixed_div) 111 div = socfpgaclk->fixed_div; 112 else if (socfpgaclk->div_reg) { 113 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 114 val &= div_mask(socfpgaclk->width); 115 /* Check for GPIO_DB_CLK by its offset */ 116 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) 117 div = val + 1; 118 else 119 div = (1 << val); 120 } 121 122 return parent_rate / div; 123 } 124 125 static int socfpga_clk_prepare(struct clk_hw *hwclk) 126 { 127 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 128 struct regmap *sys_mgr_base_addr; 129 int i; 130 u32 hs_timing; 131 u32 clk_phase[2]; 132 133 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { 134 sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); 135 if (IS_ERR(sys_mgr_base_addr)) { 136 pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); 137 return -EINVAL; 138 } 139 140 for (i = 0; i < 2; i++) { 141 switch (socfpgaclk->clk_phase[i]) { 142 case 0: 143 clk_phase[i] = 0; 144 break; 145 case 45: 146 clk_phase[i] = 1; 147 break; 148 case 90: 149 clk_phase[i] = 2; 150 break; 151 case 135: 152 clk_phase[i] = 3; 153 break; 154 case 180: 155 clk_phase[i] = 4; 156 break; 157 case 225: 158 clk_phase[i] = 5; 159 break; 160 case 270: 161 clk_phase[i] = 6; 162 break; 163 case 315: 164 clk_phase[i] = 7; 165 break; 166 default: 167 clk_phase[i] = 0; 168 break; 169 } 170 } 171 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); 172 regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, 173 hs_timing); 174 } 175 return 0; 176 } 177 178 static struct clk_ops gateclk_ops = { 179 .prepare = socfpga_clk_prepare, 180 .recalc_rate = socfpga_clk_recalc_rate, 181 .get_parent = socfpga_clk_get_parent, 182 .set_parent = socfpga_clk_set_parent, 183 }; 184 185 static void __init __socfpga_gate_init(struct device_node *node, 186 const struct clk_ops *ops) 187 { 188 u32 clk_gate[2]; 189 u32 div_reg[3]; 190 u32 clk_phase[2]; 191 u32 fixed_div; 192 struct clk *clk; 193 struct socfpga_gate_clk *socfpga_clk; 194 const char *clk_name = node->name; 195 const char *parent_name[SOCFPGA_MAX_PARENTS]; 196 struct clk_init_data init; 197 int rc; 198 int i = 0; 199 200 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); 201 if (WARN_ON(!socfpga_clk)) 202 return; 203 204 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); 205 if (rc) 206 clk_gate[0] = 0; 207 208 if (clk_gate[0]) { 209 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; 210 socfpga_clk->hw.bit_idx = clk_gate[1]; 211 212 gateclk_ops.enable = clk_gate_ops.enable; 213 gateclk_ops.disable = clk_gate_ops.disable; 214 } 215 216 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 217 if (rc) 218 socfpga_clk->fixed_div = 0; 219 else 220 socfpga_clk->fixed_div = fixed_div; 221 222 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); 223 if (!rc) { 224 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; 225 socfpga_clk->shift = div_reg[1]; 226 socfpga_clk->width = div_reg[2]; 227 } else { 228 socfpga_clk->div_reg = 0; 229 } 230 231 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); 232 if (!rc) { 233 socfpga_clk->clk_phase[0] = clk_phase[0]; 234 socfpga_clk->clk_phase[1] = clk_phase[1]; 235 } 236 237 of_property_read_string(node, "clock-output-names", &clk_name); 238 239 init.name = clk_name; 240 init.ops = ops; 241 init.flags = 0; 242 while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] = 243 of_clk_get_parent_name(node, i)) != NULL) 244 i++; 245 246 init.parent_names = parent_name; 247 init.num_parents = i; 248 socfpga_clk->hw.hw.init = &init; 249 250 clk = clk_register(NULL, &socfpga_clk->hw.hw); 251 if (WARN_ON(IS_ERR(clk))) { 252 kfree(socfpga_clk); 253 return; 254 } 255 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 256 if (WARN_ON(rc)) 257 return; 258 } 259 260 void __init socfpga_gate_init(struct device_node *node) 261 { 262 __socfpga_gate_init(node, &gateclk_ops); 263 } 264