1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2011-2012 Calxeda, Inc. 4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com> 5 * 6 * Based from clk-highbank.c 7 */ 8 #include <linux/slab.h> 9 #include <linux/clk-provider.h> 10 #include <linux/io.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/regmap.h> 14 15 #include "clk.h" 16 17 #define SOCFPGA_L4_MP_CLK "l4_mp_clk" 18 #define SOCFPGA_L4_SP_CLK "l4_sp_clk" 19 #define SOCFPGA_NAND_CLK "nand_clk" 20 #define SOCFPGA_NAND_X_CLK "nand_x_clk" 21 #define SOCFPGA_MMC_CLK "sdmmc_clk" 22 #define SOCFPGA_GPIO_DB_CLK_OFFSET 0xA8 23 24 #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) 25 26 /* SDMMC Group for System Manager defines */ 27 #define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x108 28 29 static u8 socfpga_clk_get_parent(struct clk_hw *hwclk) 30 { 31 u32 l4_src; 32 u32 perpll_src; 33 34 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 35 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 36 return l4_src &= 0x1; 37 } 38 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 39 l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 40 return !!(l4_src & 2); 41 } 42 43 perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 44 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) 45 return perpll_src &= 0x3; 46 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 47 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) 48 return (perpll_src >> 2) & 3; 49 50 /* QSPI clock */ 51 return (perpll_src >> 4) & 3; 52 53 } 54 55 static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent) 56 { 57 u32 src_reg; 58 59 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { 60 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 61 src_reg &= ~0x1; 62 src_reg |= parent; 63 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 64 } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { 65 src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC); 66 src_reg &= ~0x2; 67 src_reg |= (parent << 1); 68 writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC); 69 } else { 70 src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 71 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) { 72 src_reg &= ~0x3; 73 src_reg |= parent; 74 } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || 75 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) { 76 src_reg &= ~0xC; 77 src_reg |= (parent << 2); 78 } else {/* QSPI clock */ 79 src_reg &= ~0x30; 80 src_reg |= (parent << 4); 81 } 82 writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC); 83 } 84 85 return 0; 86 } 87 88 static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, 89 unsigned long parent_rate) 90 { 91 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 92 u32 div = 1, val; 93 94 if (socfpgaclk->fixed_div) 95 div = socfpgaclk->fixed_div; 96 else if (socfpgaclk->div_reg) { 97 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; 98 val &= GENMASK(socfpgaclk->width - 1, 0); 99 /* Check for GPIO_DB_CLK by its offset */ 100 if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) 101 div = val + 1; 102 else 103 div = (1 << val); 104 } 105 106 return parent_rate / div; 107 } 108 109 static int socfpga_clk_prepare(struct clk_hw *hwclk) 110 { 111 struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); 112 struct regmap *sys_mgr_base_addr; 113 int i; 114 u32 hs_timing; 115 u32 clk_phase[2]; 116 117 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { 118 sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); 119 if (IS_ERR(sys_mgr_base_addr)) { 120 pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); 121 return -EINVAL; 122 } 123 124 for (i = 0; i < 2; i++) { 125 switch (socfpgaclk->clk_phase[i]) { 126 case 0: 127 clk_phase[i] = 0; 128 break; 129 case 45: 130 clk_phase[i] = 1; 131 break; 132 case 90: 133 clk_phase[i] = 2; 134 break; 135 case 135: 136 clk_phase[i] = 3; 137 break; 138 case 180: 139 clk_phase[i] = 4; 140 break; 141 case 225: 142 clk_phase[i] = 5; 143 break; 144 case 270: 145 clk_phase[i] = 6; 146 break; 147 case 315: 148 clk_phase[i] = 7; 149 break; 150 default: 151 clk_phase[i] = 0; 152 break; 153 } 154 } 155 hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); 156 regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, 157 hs_timing); 158 } 159 return 0; 160 } 161 162 static struct clk_ops gateclk_ops = { 163 .prepare = socfpga_clk_prepare, 164 .recalc_rate = socfpga_clk_recalc_rate, 165 .get_parent = socfpga_clk_get_parent, 166 .set_parent = socfpga_clk_set_parent, 167 }; 168 169 void __init socfpga_gate_init(struct device_node *node) 170 { 171 u32 clk_gate[2]; 172 u32 div_reg[3]; 173 u32 clk_phase[2]; 174 u32 fixed_div; 175 struct clk *clk; 176 struct socfpga_gate_clk *socfpga_clk; 177 const char *clk_name = node->name; 178 const char *parent_name[SOCFPGA_MAX_PARENTS]; 179 struct clk_init_data init; 180 struct clk_ops *ops; 181 int rc; 182 183 socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); 184 if (WARN_ON(!socfpga_clk)) 185 return; 186 187 ops = kmemdup(&gateclk_ops, sizeof(gateclk_ops), GFP_KERNEL); 188 if (WARN_ON(!ops)) 189 return; 190 191 rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); 192 if (rc) 193 clk_gate[0] = 0; 194 195 if (clk_gate[0]) { 196 socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0]; 197 socfpga_clk->hw.bit_idx = clk_gate[1]; 198 199 ops->enable = clk_gate_ops.enable; 200 ops->disable = clk_gate_ops.disable; 201 } 202 203 rc = of_property_read_u32(node, "fixed-divider", &fixed_div); 204 if (rc) 205 socfpga_clk->fixed_div = 0; 206 else 207 socfpga_clk->fixed_div = fixed_div; 208 209 rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); 210 if (!rc) { 211 socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0]; 212 socfpga_clk->shift = div_reg[1]; 213 socfpga_clk->width = div_reg[2]; 214 } else { 215 socfpga_clk->div_reg = NULL; 216 } 217 218 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); 219 if (!rc) { 220 socfpga_clk->clk_phase[0] = clk_phase[0]; 221 socfpga_clk->clk_phase[1] = clk_phase[1]; 222 } 223 224 of_property_read_string(node, "clock-output-names", &clk_name); 225 226 init.name = clk_name; 227 init.ops = ops; 228 init.flags = 0; 229 230 init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); 231 if (init.num_parents < 2) { 232 ops->get_parent = NULL; 233 ops->set_parent = NULL; 234 } 235 236 init.parent_names = parent_name; 237 socfpga_clk->hw.hw.init = &init; 238 239 clk = clk_register(NULL, &socfpga_clk->hw.hw); 240 if (WARN_ON(IS_ERR(clk))) { 241 kfree(socfpga_clk); 242 return; 243 } 244 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); 245 if (WARN_ON(rc)) 246 return; 247 } 248