xref: /openbmc/linux/drivers/clk/socfpga/clk-agilex.c (revision 710b797c)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2019, Intel Corporation
4  */
5 #include <linux/slab.h>
6 #include <linux/clk-provider.h>
7 #include <linux/of_device.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 
11 #include <dt-bindings/clock/agilex-clock.h>
12 
13 #include "stratix10-clk.h"
14 
15 static const struct clk_parent_data pll_mux[] = {
16 	{ .fw_name = "osc1",
17 	  .name = "osc1", },
18 	{ .fw_name = "cb-intosc-hs-div2-clk",
19 	  .name = "cb-intosc-hs-div2-clk", },
20 	{ .fw_name = "f2s-free-clk",
21 	  .name = "f2s-free-clk", },
22 };
23 
24 static const struct clk_parent_data boot_mux[] = {
25 	{ .fw_name = "osc1",
26 	  .name = "osc1", },
27 	{ .fw_name = "cb-intosc-hs-div2-clk",
28 	  .name = "cb-intosc-hs-div2-clk", },
29 };
30 
31 static const struct clk_parent_data mpu_free_mux[] = {
32 	{ .fw_name = "main_pll_c0",
33 	  .name = "main_pll_c0", },
34 	{ .fw_name = "peri_pll_c0",
35 	  .name = "peri_pll_c0", },
36 	{ .fw_name = "osc1",
37 	  .name = "osc1", },
38 	{ .fw_name = "cb-intosc-hs-div2-clk",
39 	  .name = "cb-intosc-hs-div2-clk", },
40 	{ .fw_name = "f2s-free-clk",
41 	  .name = "f2s-free-clk", },
42 };
43 
44 static const struct clk_parent_data noc_free_mux[] = {
45 	{ .fw_name = "main_pll_c1",
46 	  .name = "main_pll_c1", },
47 	{ .fw_name = "peri_pll_c1",
48 	  .name = "peri_pll_c1", },
49 	{ .fw_name = "osc1",
50 	  .name = "osc1", },
51 	{ .fw_name = "cb-intosc-hs-div2-clk",
52 	  .name = "cb-intosc-hs-div2-clk", },
53 	{ .fw_name = "f2s-free-clk",
54 	  .name = "f2s-free-clk", },
55 };
56 
57 static const struct clk_parent_data emaca_free_mux[] = {
58 	{ .fw_name = "main_pll_c2",
59 	  .name = "main_pll_c2", },
60 	{ .fw_name = "peri_pll_c2",
61 	  .name = "peri_pll_c2", },
62 	{ .fw_name = "osc1",
63 	  .name = "osc1", },
64 	{ .fw_name = "cb-intosc-hs-div2-clk",
65 	  .name = "cb-intosc-hs-div2-clk", },
66 	{ .fw_name = "f2s-free-clk",
67 	  .name = "f2s-free-clk", },
68 };
69 
70 static const struct clk_parent_data emacb_free_mux[] = {
71 	{ .fw_name = "main_pll_c3",
72 	  .name = "main_pll_c3", },
73 	{ .fw_name = "peri_pll_c3",
74 	  .name = "peri_pll_c3", },
75 	{ .fw_name = "osc1",
76 	  .name = "osc1", },
77 	{ .fw_name = "cb-intosc-hs-div2-clk",
78 	  .name = "cb-intosc-hs-div2-clk", },
79 	{ .fw_name = "f2s-free-clk",
80 	  .name = "f2s-free-clk", },
81 };
82 
83 static const struct clk_parent_data emac_ptp_free_mux[] = {
84 	{ .fw_name = "main_pll_c3",
85 	  .name = "main_pll_c3", },
86 	{ .fw_name = "peri_pll_c3",
87 	  .name = "peri_pll_c3", },
88 	{ .fw_name = "osc1",
89 	  .name = "osc1", },
90 	{ .fw_name = "cb-intosc-hs-div2-clk",
91 	  .name = "cb-intosc-hs-div2-clk", },
92 	{ .fw_name = "f2s-free-clk",
93 	  .name = "f2s-free-clk", },
94 };
95 
96 static const struct clk_parent_data gpio_db_free_mux[] = {
97 	{ .fw_name = "main_pll_c3",
98 	  .name = "main_pll_c3", },
99 	{ .fw_name = "peri_pll_c3",
100 	  .name = "peri_pll_c3", },
101 	{ .fw_name = "osc1",
102 	  .name = "osc1", },
103 	{ .fw_name = "cb-intosc-hs-div2-clk",
104 	  .name = "cb-intosc-hs-div2-clk", },
105 	{ .fw_name = "f2s-free-clk",
106 	  .name = "f2s-free-clk", },
107 };
108 
109 static const struct clk_parent_data psi_ref_free_mux[] = {
110 	{ .fw_name = "main_pll_c3",
111 	  .name = "main_pll_c3", },
112 	{ .fw_name = "peri_pll_c3",
113 	  .name = "peri_pll_c3", },
114 	{ .fw_name = "osc1",
115 	  .name = "osc1", },
116 	{ .fw_name = "cb-intosc-hs-div2-clk",
117 	  .name = "cb-intosc-hs-div2-clk", },
118 	{ .fw_name = "f2s-free-clk",
119 	  .name = "f2s-free-clk", },
120 };
121 
122 static const struct clk_parent_data sdmmc_free_mux[] = {
123 	{ .fw_name = "main_pll_c3",
124 	  .name = "main_pll_c3", },
125 	{ .fw_name = "peri_pll_c3",
126 	  .name = "peri_pll_c3", },
127 	{ .fw_name = "osc1",
128 	  .name = "osc1", },
129 	{ .fw_name = "cb-intosc-hs-div2-clk",
130 	  .name = "cb-intosc-hs-div2-clk", },
131 	{ .fw_name = "f2s-free-clk",
132 	  .name = "f2s-free-clk", },
133 };
134 
135 static const struct clk_parent_data s2f_usr0_free_mux[] = {
136 	{ .fw_name = "main_pll_c2",
137 	  .name = "main_pll_c2", },
138 	{ .fw_name = "peri_pll_c2",
139 	  .name = "peri_pll_c2", },
140 	{ .fw_name = "osc1",
141 	  .name = "osc1", },
142 	{ .fw_name = "cb-intosc-hs-div2-clk",
143 	  .name = "cb-intosc-hs-div2-clk", },
144 	{ .fw_name = "f2s-free-clk",
145 	  .name = "f2s-free-clk", },
146 };
147 
148 static const struct clk_parent_data s2f_usr1_free_mux[] = {
149 	{ .fw_name = "main_pll_c2",
150 	  .name = "main_pll_c2", },
151 	{ .fw_name = "peri_pll_c2",
152 	  .name = "peri_pll_c2", },
153 	{ .fw_name = "osc1",
154 	  .name = "osc1", },
155 	{ .fw_name = "cb-intosc-hs-div2-clk",
156 	  .name = "cb-intosc-hs-div2-clk", },
157 	{ .fw_name = "f2s-free-clk",
158 	  .name = "f2s-free-clk", },
159 };
160 
161 static const struct clk_parent_data mpu_mux[] = {
162 	{ .fw_name = "mpu_free_clk",
163 	  .name = "mpu_free_clk", },
164 	{ .fw_name = "boot_clk",
165 	  .name = "boot_clk", },
166 };
167 
168 static const struct clk_parent_data s2f_usr0_mux[] = {
169 	{ .fw_name = "f2s-free-clk",
170 	  .name = "f2s-free-clk", },
171 	{ .fw_name = "boot_clk",
172 	  .name = "boot_clk", },
173 };
174 
175 static const struct clk_parent_data emac_mux[] = {
176 	{ .fw_name = "emaca_free_clk",
177 	  .name = "emaca_free_clk", },
178 	{ .fw_name = "emacb_free_clk",
179 	  .name = "emacb_free_clk", },
180 };
181 
182 static const struct clk_parent_data noc_mux[] = {
183 	{ .fw_name = "noc_free_clk",
184 	  .name = "noc_free_clk", },
185 	{ .fw_name = "boot_clk",
186 	  .name = "boot_clk", },
187 };
188 
189 /* clocks in AO (always on) controller */
190 static const struct stratix10_pll_clock agilex_pll_clks[] = {
191 	{ AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
192 	  0x0},
193 	{ AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
194 	  0, 0x48},
195 	{ AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
196 	  0, 0x9c},
197 };
198 
199 static const struct n5x_perip_c_clock n5x_main_perip_c_clks[] = {
200 	{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x54, 0},
201 	{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x54, 8},
202 	{ AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x54, 16},
203 	{ AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x54, 24},
204 	{ AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xA8, 0},
205 	{ AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xA8, 8},
206 	{ AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xA8, 16},
207 	{ AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xA8, 24},
208 };
209 
210 static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
211 	{ AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
212 	{ AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
213 	{ AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
214 	{ AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
215 	{ AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
216 	{ AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
217 	{ AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
218 	{ AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
219 };
220 
221 static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
222 	{ AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
223 	   0, 0x3C, 0, 0, 0},
224 	{ AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
225 	  0, 0x40, 0, 0, 1},
226 	{ AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
227 	  0, 4, 0, 0},
228 	{ AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
229 	  0, 0, 0, 0x30, 1},
230 	{ AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
231 	  0, 0xD4, 0, 0x88, 0},
232 	{ AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
233 	  0, 0xD8, 0, 0x88, 1},
234 	{ AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
235 	  ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
236 	{ AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
237 	  ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
238 	{ AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
239 	  ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4},
240 	{ AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
241 	  ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
242 	{ AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
243 	  ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
244 	{ AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
245 	  ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
246 };
247 
248 static const struct stratix10_gate_clock agilex_gate_clks[] = {
249 	{ AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
250 	  0, 0, 0, 0, 0x30, 0, 0},
251 	{ AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
252 	  0, 0, 0, 0, 0, 0, 4},
253 	{ AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
254 	  0, 0, 0, 0, 0, 0, 2},
255 	{ AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
256 	  1, 0x44, 0, 2, 0, 0, 0},
257 	{ AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24,
258 	  2, 0x44, 8, 2, 0, 0, 0},
259 	/*
260 	 * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
261 	 * being the SP timers, thus cannot get gated.
262 	 */
263 	{ AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24,
264 	  3, 0x44, 16, 2, 0, 0, 0},
265 	{ AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24,
266 	  4, 0x44, 24, 2, 0, 0, 0},
267 	{ AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24,
268 	  4, 0x44, 26, 2, 0, 0, 0},
269 	{ AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
270 	  4, 0x44, 28, 1, 0, 0, 0},
271 	{ AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24,
272 	  5, 0, 0, 0, 0, 0, 0},
273 	{ AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24,
274 	  6, 0, 0, 0, 0, 0, 0},
275 	{ AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
276 	  0, 0, 0, 0, 0x94, 26, 0},
277 	{ AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
278 	  1, 0, 0, 0, 0x94, 27, 0},
279 	{ AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
280 	  2, 0, 0, 0, 0x94, 28, 0},
281 	{ AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0x7C,
282 	  3, 0, 0, 0, 0, 0, 0},
283 	{ AGILEX_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0x7C,
284 	  4, 0x98, 0, 16, 0, 0, 0},
285 	{ AGILEX_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0x7C,
286 	  5, 0, 0, 0, 0, 0, 4},
287 	{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0x7C,
288 	  6, 0, 0, 0, 0, 0, 0},
289 	{ AGILEX_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0x7C,
290 	  7, 0, 0, 0, 0, 0, 0},
291 	{ AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
292 	  8, 0, 0, 0, 0, 0, 0},
293 	{ AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
294 	  9, 0, 0, 0, 0, 0, 0},
295 	{ AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
296 	  10, 0, 0, 0, 0, 0, 0},
297 	{ AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
298 	  10, 0, 0, 0, 0, 0, 4},
299 	{ AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
300 	  10, 0, 0, 0, 0, 0, 4},
301 };
302 
303 static int n5x_clk_register_c_perip(const struct n5x_perip_c_clock *clks,
304 				       int nums, struct stratix10_clock_data *data)
305 {
306 	struct clk_hw *hw_clk;
307 	void __iomem *base = data->base;
308 	int i;
309 
310 	for (i = 0; i < nums; i++) {
311 		hw_clk = n5x_register_periph(&clks[i], base);
312 		if (IS_ERR(hw_clk)) {
313 			pr_err("%s: failed to register clock %s\n",
314 			       __func__, clks[i].name);
315 			continue;
316 		}
317 		data->clk_data.hws[clks[i].id] = hw_clk;
318 	}
319 	return 0;
320 }
321 
322 static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
323 				       int nums, struct stratix10_clock_data *data)
324 {
325 	struct clk_hw *hw_clk;
326 	void __iomem *base = data->base;
327 	int i;
328 
329 	for (i = 0; i < nums; i++) {
330 		hw_clk = s10_register_periph(&clks[i], base);
331 		if (IS_ERR(hw_clk)) {
332 			pr_err("%s: failed to register clock %s\n",
333 			       __func__, clks[i].name);
334 			continue;
335 		}
336 		data->clk_data.hws[clks[i].id] = hw_clk;
337 	}
338 	return 0;
339 }
340 
341 static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
342 					 int nums, struct stratix10_clock_data *data)
343 {
344 	struct clk_hw *hw_clk;
345 	void __iomem *base = data->base;
346 	int i;
347 
348 	for (i = 0; i < nums; i++) {
349 		hw_clk = s10_register_cnt_periph(&clks[i], base);
350 		if (IS_ERR(hw_clk)) {
351 			pr_err("%s: failed to register clock %s\n",
352 			       __func__, clks[i].name);
353 			continue;
354 		}
355 		data->clk_data.hws[clks[i].id] = hw_clk;
356 	}
357 
358 	return 0;
359 }
360 
361 static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,
362 				    int nums, struct stratix10_clock_data *data)
363 {
364 	struct clk_hw *hw_clk;
365 	void __iomem *base = data->base;
366 	int i;
367 
368 	for (i = 0; i < nums; i++) {
369 		hw_clk = s10_register_gate(&clks[i], base);
370 		if (IS_ERR(hw_clk)) {
371 			pr_err("%s: failed to register clock %s\n",
372 			       __func__, clks[i].name);
373 			continue;
374 		}
375 		data->clk_data.hws[clks[i].id] = hw_clk;
376 	}
377 
378 	return 0;
379 }
380 
381 static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
382 				 int nums, struct stratix10_clock_data *data)
383 {
384 	struct clk_hw *hw_clk;
385 	void __iomem *base = data->base;
386 	int i;
387 
388 	for (i = 0; i < nums; i++) {
389 		hw_clk = agilex_register_pll(&clks[i], base);
390 		if (IS_ERR(hw_clk)) {
391 			pr_err("%s: failed to register clock %s\n",
392 			       __func__, clks[i].name);
393 			continue;
394 		}
395 		data->clk_data.hws[clks[i].id] = hw_clk;
396 	}
397 
398 	return 0;
399 }
400 
401 static int n5x_clk_register_pll(const struct stratix10_pll_clock *clks,
402 				 int nums, struct stratix10_clock_data *data)
403 {
404 	struct clk_hw *hw_clk;
405 	void __iomem *base = data->base;
406 	int i;
407 
408 	for (i = 0; i < nums; i++) {
409 		hw_clk = n5x_register_pll(&clks[i], base);
410 		if (IS_ERR(hw_clk)) {
411 			pr_err("%s: failed to register clock %s\n",
412 			       __func__, clks[i].name);
413 			continue;
414 		}
415 		data->clk_data.hws[clks[i].id] = hw_clk;
416 	}
417 
418 	return 0;
419 }
420 
421 static int agilex_clkmgr_init(struct platform_device *pdev)
422 {
423 	struct device_node *np = pdev->dev.of_node;
424 	struct device *dev = &pdev->dev;
425 	struct stratix10_clock_data *clk_data;
426 	struct resource *res;
427 	void __iomem *base;
428 	int i, num_clks;
429 
430 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
431 	base = devm_ioremap_resource(dev, res);
432 	if (IS_ERR(base))
433 		return PTR_ERR(base);
434 
435 	num_clks = AGILEX_NUM_CLKS;
436 
437 	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
438 				num_clks), GFP_KERNEL);
439 	if (!clk_data)
440 		return -ENOMEM;
441 
442 	for (i = 0; i < num_clks; i++)
443 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
444 
445 	clk_data->base = base;
446 	clk_data->clk_data.num = num_clks;
447 
448 	agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
449 
450 	agilex_clk_register_c_perip(agilex_main_perip_c_clks,
451 				 ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
452 
453 	agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
454 				   ARRAY_SIZE(agilex_main_perip_cnt_clks),
455 				   clk_data);
456 
457 	agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
458 			      clk_data);
459 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
460 	return 0;
461 }
462 
463 static int n5x_clkmgr_init(struct platform_device *pdev)
464 {
465 	struct device_node *np = pdev->dev.of_node;
466 	struct device *dev = &pdev->dev;
467 	struct stratix10_clock_data *clk_data;
468 	struct resource *res;
469 	void __iomem *base;
470 	int i, num_clks;
471 
472 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
473 	base = devm_ioremap_resource(dev, res);
474 	if (IS_ERR(base))
475 		return PTR_ERR(base);
476 
477 	num_clks = AGILEX_NUM_CLKS;
478 
479 	clk_data = devm_kzalloc(dev, struct_size(clk_data, clk_data.hws,
480 				num_clks), GFP_KERNEL);
481 	if (!clk_data)
482 		return -ENOMEM;
483 
484 	for (i = 0; i < num_clks; i++)
485 		clk_data->clk_data.hws[i] = ERR_PTR(-ENOENT);
486 
487 	clk_data->base = base;
488 	clk_data->clk_data.num = num_clks;
489 
490 	n5x_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
491 
492 	n5x_clk_register_c_perip(n5x_main_perip_c_clks,
493 				 ARRAY_SIZE(n5x_main_perip_c_clks), clk_data);
494 
495 	agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
496 				   ARRAY_SIZE(agilex_main_perip_cnt_clks),
497 				   clk_data);
498 
499 	agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
500 			      clk_data);
501 	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data->clk_data);
502 	return 0;
503 }
504 
505 static int agilex_clkmgr_probe(struct platform_device *pdev)
506 {
507 	int (*probe_func)(struct platform_device *init_func);
508 
509 	probe_func = of_device_get_match_data(&pdev->dev);
510 	if (!probe_func)
511 		return -ENODEV;
512 	return	probe_func(pdev);
513 }
514 
515 static const struct of_device_id agilex_clkmgr_match_table[] = {
516 	{ .compatible = "intel,agilex-clkmgr",
517 	  .data = agilex_clkmgr_init },
518 	{ .compatible = "intel,easic-n5x-clkmgr",
519 	  .data = n5x_clkmgr_init },
520 	{ }
521 };
522 
523 static struct platform_driver agilex_clkmgr_driver = {
524 	.probe		= agilex_clkmgr_probe,
525 	.driver		= {
526 		.name	= "agilex-clkmgr",
527 		.suppress_bind_attrs = true,
528 		.of_match_table = agilex_clkmgr_match_table,
529 	},
530 };
531 
532 static int __init agilex_clk_init(void)
533 {
534 	return platform_driver_register(&agilex_clkmgr_driver);
535 }
536 core_initcall(agilex_clk_init);
537